Main_16Bit_RAM Project Status
Project File: Main_16Bit_RAM.ise Implementation State: Programming File Generated
Module Name: main
  • Errors:
 
Target Device: xc3s700an-4fgg484
  • Warnings:
 
Product Version:ISE 11.5
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
0 (Setup: 0, Hold: 0, Component Switching Limit: 0) (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 284 11,776 2%  
Number of 4 input LUTs 456 11,776 3%  
Number of occupied Slices 332 5,888 5%  
    Number of Slices containing only related logic 332 332 100%  
    Number of Slices containing unrelated logic 0 332 0%  
Total Number of 4 input LUTs 487 11,776 4%  
    Number used as logic 456      
    Number used as a route-thru 31      
Number of bonded IOBs 157 372 42%  
    IOB Flip Flops 20      
    IOB Master Pads 9      
    IOB Slave Pads 9      
Number of ODDR2s used 24      
Number of BUFGMUXs 3 24 12%  
Number of DCMs 1 8 12%  
Average Fanout of Non-Clock Nets 3.02      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentDi 2. Nov 16:42:21 2010   
Translation ReportCurrentDi 2. Nov 16:42:35 2010   
Map ReportCurrentDi 2. Nov 16:42:46 2010   
Place and Route ReportCurrentDi 2. Nov 16:43:14 2010   
Power Report     
Post-PAR Static Timing ReportCurrentDi 2. Nov 16:43:28 2010   
Bitgen ReportCurrentDi 2. Nov 16:43:46 2010   
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateSa 6. Nov 16:09:20 2010

Date Generated: 02/03/2011 - 10:06:44