// // Dual-Port Block RAM with Two Write Ports, Write First // module dualport_wf #( parameter data_bits = 32, parameter addr_bits = 9, parameter memfile = 0 ) ( input [data_bits-1:0] dia, input [data_bits-1:0] dib, input [addr_bits-1:0] addra, input [addr_bits-1:0] addrb, input wea, input web, input clka, input clkb, input ena, input enb, output [data_bits-1:0] doa, output [data_bits-1:0] dob ); reg [data_bits-1:0] ram[0:(1<>8 & 8'hff, // ram[i]>>16 & 8'hff, ram[i]>>24 & 8'hff); end always @(posedge clka) begin if (ena) begin if (wea) ram[addra] <= dia; addra_reg <= addra; end end always @(posedge clkb) begin if (enb) begin if (web) ram[addrb] <= dib; addrb_reg <= addrb; end end assign doa = ram[addra_reg]; assign dob = ram[addrb_reg]; endmodule