library IEEE; use IEEE.std_logic_1164.all; use work.std_arith.all; entity COUNT is port( CLK, ENA : in std_logic; Q : buffer std_logic_vector(3 downto 0); UEB : out std_logic); end COUNT; architecture A1 of COUNT is begin P1: process( CLK ) begin if( CLK'event and CLK = '1' ) then if( ENA = '1' ) then Q <= Q + 1; end if; end if; end process; UEB <= '1' when Q = "1111" else '0'; end A1;