LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY TL_transmitter IS PORT( -- Globals Reset : IN STD_LOGIC; -- Global reset -- ethernet serial interface Eth_Reset : IN STD_LOGIC; -- LXT905 '1'=PowerOFF Eth_TxClk : IN STD_LOGIC; -- LXT905 transmit clock Eth_Tx : OUT STD_LOGIC; -- LXT905 transmit data Eth_TxEn : OUT STD_LOGIC; -- LXT905 transmit enable Eth_TxOn : OUT STD_LOGIC; -- LXT905 transmit switch on -- ethernet parallel interface Tx_DEU_Number : IN bus4; -- Transmit Unit number Tx_Port_Number : IN bus7; -- Transmit port number Disc_DEUtoDIR_Data : IN array_10x16; -- Disc Data do_Tx : IN STD_LOGIC; -- start transmission Output_en : IN std_logic ; -- first Superframe received Test : OUT bus8 -- Test signals ); END TL_transmitter ; ARCHITECTURE spec OF TL_transmitter IS TYPE TxStateType IS (Idle, SENDSync, SENDSOF, SENDMAC, SENDQuelle, SendVlan, SENDTyp, SENDData, SENDCRC, SwitchOn); SIGNAL TxState : TxStateType; -- Transmit State Machine State SIGNAL NextTxState : TxStateType; -- Next Transmit State Machine State SIGNAL BitCtr : bus5; -- Transmit Bit Counter SIGNAL WordCtr : bus6; -- Word Counter SIGNAL WordCtrEn : STD_LOGIC; -- Word Counter Enable SIGNAL WordCtrRes : STD_LOGIC; -- Word Counter Reset SIGNAL BitCtrRes : STD_LOGIC; -- Bit Counter Reset SIGNAL Shifter : bus17; -- Transmit Shift Register SIGNAL ShifterCRC : bus32; -- Transmit Shift Register SIGNAL CRCdo : STD_LOGIC; -- hilfsvariable SIGNAL ShiftLd : STD_LOGIC; -- Load Transmit Shift Register SIGNAL TxWord : bus17; -- Transmit Data IN Parallel Format SIGNAL doTxold : STD_LOGIC; -- start transmisson internal SIGNAL doTx : STD_LOGIC; -- start transmisson internal SIGNAL startTx : STD_LOGIC; -- start transmisson internal SUBTYPE delay_range IS NATURAL RANGE 0 TO 8000001; SIGNAL delay : delay_range; --------------------------------------------------------------------------------------------------- CONSTANT MAC : std_logic_vector(47 DOWNTO 0) := x"0014380F5FC3"; -- Mac Adresse BULA900062974 CONSTANT Quelle : std_logic_vector(47 DOWNTO 0) := x"0040F6445566"; -- Mac Quelladresse irgendwas.... CONSTANT Typ : std_logic_vector(15 DOWNTO 0) := x"0800"; -- Typen Feld... CONSTANT VLANTAG : std_LOGIC_VECTOR(31 downto 0) :=x"81000301"; -- Vlantag SIGNAL Data : array_48x8; ------------------------------------------------------------------------------------- function crctest (data_in:std_logic_vector (7 downto 0); crc_value:std_logic_vector(31 downto 0)) return std_logic_vector is --G(X)=x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1 variable crc_out: std_logic_vector(31 downto 0); begin crc_out:=crc_value; for k in 0 to 7 loop if crc_out(0) /=data_in(k) then crc_out:=('0'& crc_out(31 downto 1)) xor X"EDB88320"; else crc_out:=('0'& crc_out(31 downto 1)); end if; end loop; return crc_out; end crctest; ----------------------------------------------------------------- BEGIN -- transmit shift register ----------------------------------------------- PROCESS (Eth_TxClk, Reset) BEGIN IF (RESET='0') THEN Shifter <= (OTHERS => '0'); ELSIF (Eth_TxClk'EVENT AND Eth_TxClk='0') THEN IF ShiftLd='1' THEN Shifter <= TxWord; ELSE Shifter <= '0' & Shifter(16 DOWNTO 1); END IF; END IF; END PROCESS; Eth_Tx <= Shifter(0); -- Create CRC32------------------------------------------------------------ PROCESS (Eth_TxClk, Reset) BEGIN IF (RESET = '0') THEN ShifterCRC <= (OTHERS => '1'); ELSIF (Eth_TxClk'EVENT AND Eth_TxClk='0') THEN IF (TxState=Idle) THEN ShifterCRC <= (OTHERS => '1'); ELSIF (CRCdo = '1') THEN ShifterCRC <= crctest(Txword(7 downto 0), ShifterCRC); END IF; END IF; END PROCESS; -- transmit state machine, synchron part --------------------------------- -- generate ethernet transmit enable and counter for the transmit state machine TxState_P : PROCESS (Eth_TxClk, Reset) BEGIN IF (RESET='0') THEN TxState <= Idle; BitCtr <= (OTHERS => '0'); WordCtr <= (OTHERS => '0'); Eth_TxEn <= '0'; Eth_TxOn <= '0'; Data <= (OTHERS => (OTHERS => '0')); Delay <= Tx_Delay_Cnt; -- wait for 8 ms -> 80000 @ 10 MHz ELSIF (Eth_TxClk'EVENT AND Eth_TxClk='0') THEN TxState <= NextTxState; IF (WordCtrRes = '1') THEN WordCtr <= "000000"; ELSIF (WordCtrEn='1') THEN WordCtr <= WordCtr + "01"; END IF; IF (BitCtrRes = '1') THEN BitCtr <= "00000"; ELSE BitCtr <= BitCtr + "01"; END IF; IF (NextTxState=Idle) OR (NextTxState=SwitchOn) THEN Eth_TxEn<='0'; ELSE Eth_TxEn<='1'; END IF; IF (NextTxState=Idle) THEN Eth_TxOn<='0'; ELSE Eth_TxOn<='1'; END IF; IF (Output_en = '1') THEN Delay <= Delay + 1; END IF; IF (Delay=8000000) THEN Delay <= 8000000; END IF; IF (Eth_Reset='1') THEN Delay <= 0; END IF; END IF; END PROCESS; -- catch transmission with tx clock startTx_P : PROCESS (Eth_TxClk, Reset) BEGIN IF (RESET='0') THEN doTxold <= '0'; doTx <= '0'; startTx <= '0'; ELSIF (Eth_TxClk'EVENT AND Eth_TxClk='0') THEN startTx <= '0'; doTx <= do_Tx; doTxold <= doTx; IF (doTxold='0') AND (doTx='1') THEN startTx <= '1'; END IF; END IF; END PROCESS; -- transmit state machine, combinatorial part --------------------------- -- generate transmission frame NextTxState_P : PROCESS (TxState, startTx, WordCtr, BitCtr, Delay, Disc_DEUtoDIR_Data, ShifterCRC) BEGIN ShiftLd <= '0'; WordCtrRes <= '0'; BitCtrRes <= '0'; WordCtrEn <= '0'; TxWord <= (OTHERS => '0'); CRCdo <= '0'; CASE TxState IS WHEN Idle => NextTxState <= Idle; BitCtrRes <= '1'; IF (startTx='1') AND (Delay=8000000) THEN NextTxState <= SENDSync; TxWord(7 DOWNTO 0) <= "01010101"; ShiftLd <= '1'; BitCtrRes <= '1'; WordCtrRes <= '1'; END IF; WHEN SENDSync => NextTxState <= SENDSync; IF (BitCtr="00111") THEN TxWord(7 DOWNTO 0) <= "01010101"; ShiftLd <= '1'; BitCtrRes <= '1'; WordCtrEn <= '1'; END IF; IF (BitCtr="00111") AND (WordCtr="00110") THEN NextTxState <= SENDSOF; TxWord(7 DOWNTO 0) <= "11010101"; ShiftLd <= '1'; BitCtrRes <= '1'; WordCtrRes <= '1'; END IF; IF (startTx='1') THEN NextTxState <= SENDSync; TxWord(7 DOWNTO 0) <= "01010101"; ShiftLd <= '1'; BitCtrRes <= '1'; WordCtrRes <= '1'; END IF; WHEN SENDSOF => NextTxState <= SENDSOF; IF (BitCtr="00111" AND WordCtr = "000000") THEN NextTxState <= SENDMAC; TxWord(7 DOWNTO 0) <= MAC(47 downto 40); ShiftLd <= '1'; BitCtrRes <= '1'; WordCtrEn <= '1'; CRCdo <= '1'; END IF; IF (startTx='1') THEN NextTxState <= SENDSync; TxWord(7 DOWNTO 0) <= "01010101"; ShiftLd <= '1'; BitCtrRes <= '1'; WordCtrRes <= '1'; END IF; WHEN SENDMAC => NextTxState <= SENDMAC; IF (BitCtr="00111" AND WordCtr = "000001") THEN TxWord(7 DOWNTO 0) <= MAC(39 downto 32); ShiftLd <= '1'; BitCtrRes <= '1'; WordCtrEn <= '1'; CRCdo <= '1'; END IF; IF (BitCtr="00111" AND WordCtr = "000010") THEN TxWord(7 DOWNTO 0) <= MAC(31 downto 24); ShiftLd <= '1'; BitCtrRes <= '1'; WordCtrEn <= '1'; CRCdo <= '1'; END IF; IF (BitCtr="00111" AND WordCtr = "000011") THEN TxWord(7 DOWNTO 0) <= MAC(23 downto 16); ShiftLd <= '1'; BitCtrRes <= '1'; WordCtrEn <= '1'; CRCdo <= '1'; END IF; IF (BitCtr="00111" AND WordCtr = "000100") THEN TxWord(7 DOWNTO 0) <= MAC(15 downto 8); ShiftLd <= '1'; BitCtrRes <= '1'; WordCtrEn <= '1'; CRCdo <= '1'; END IF; IF (BitCtr="00111" AND WordCtr = "000101") THEN TxWord(7 DOWNTO 0) <= MAC(7 downto 0); ShiftLd <= '1'; BitCtrRes <= '1'; WordCtrRes <= '1'; CRCdo <= '1'; END IF; IF (BitCtr="00111" AND WordCtr = "000000") THEN TxWord(7 DOWNTO 0) <= Quelle(47 downto 40); NextTxState <= SendQuelle ; ShiftLd <= '1'; BitCtrRes <= '1'; WordCtrEn <= '1'; CRCdo <= '1'; END IF; IF (startTx='1') THEN NextTxState <= SENDSync; TxWord(7 DOWNTO 0) <= "01010101"; ShiftLd <= '1'; BitCtrRes <= '1'; WordCtrRes <= '1'; END IF; WHEN SENDQuelle => NextTxState <= SENDQuelle; IF (BitCtr="00111" AND WordCtr = "000001") THEN TxWord(7 DOWNTO 0) <= Quelle(39 downto 32); ShiftLd <= '1'; BitCtrRes <= '1'; WordCtrEn <= '1'; CRCdo <= '1'; END IF; IF (BitCtr="00111" AND WordCtr = "000010") THEN TxWord(7 DOWNTO 0) <= Quelle(31 downto 24); ShiftLd <= '1'; BitCtrRes <= '1'; WordCtrEn <= '1'; CRCdo <= '1'; END IF; IF (BitCtr="00111" AND WordCtr = "000011") THEN TxWord(7 DOWNTO 0) <= Quelle(23 downto 16); ShiftLd <= '1'; BitCtrRes <= '1'; WordCtrEn <= '1'; CRCdo <= '1'; END IF; IF (BitCtr="00111" AND WordCtr = "000100") THEN TxWord(7 DOWNTO 0) <= Quelle(15 downto 8); ShiftLd <= '1'; BitCtrRes <= '1'; WordCtrEn <= '1'; CRCdo <= '1'; END IF; IF (BitCtr="00111" AND WordCtr = "000101") THEN TxWord(7 DOWNTO 0) <= Quelle(7 downto 0); ShiftLd <= '1'; BitCtrRes <= '1'; WordCtrRes <= '1'; CRCdo <= '1'; END IF; IF (BitCtr="00111" AND WordCtr = "000000") THEN TxWord(7 DOWNTO 0) <= Vlantag(31 downto 24); NextTxState <= SendVlan ; ShiftLd <= '1'; BitCtrRes <= '1'; WordCtrEn <= '1'; CRCdo <= '1'; END IF; IF (startTx='1') THEN NextTxState <= SENDSync; TxWord(7 DOWNTO 0) <= "01010101"; ShiftLd <= '1'; BitCtrRes <= '1'; WordCtrRes <= '1'; END IF; WHEN SENDVlan => NextTxState <= SENDVlan; IF (BitCtr="00111" AND WordCtr = "000001") THEN TxWord(7 DOWNTO 0) <= Vlantag(23 downto 16); ShiftLd <= '1'; BitCtrRes <= '1'; WordCtrEn <= '1'; CRCdo <= '1'; END IF; IF (BitCtr="00111" AND WordCtr = "000010") THEN TxWord(7 DOWNTO 0) <= Vlantag(15 downto 8); ShiftLd <= '1'; BitCtrRes <= '1'; WordCtrEn <= '1'; CRCdo <= '1'; END IF; IF (BitCtr="00111" AND WordCtr = "000011") THEN TxWord(7 DOWNTO 0) <= Vlantag(7 downto 0); ShiftLd <= '1'; BitCtrRes <= '1'; WordCtrRes <= '1'; CRCdo <= '1'; END IF; IF (BitCtr="00111" AND WordCtr = "000000") THEN TxWord(7 DOWNTO 0) <= Typ(15 downto 8); NextTxState <= SendTyp ; ShiftLd <= '1'; BitCtrRes <= '1'; WordCtrEn <= '1'; CRCdo <= '1'; END IF; IF (startTx='1') THEN NextTxState <= SENDSync; TxWord(7 DOWNTO 0) <= "01010101"; ShiftLd <= '1'; BitCtrRes <= '1'; WordCtrRes <= '1'; END IF; WHEN SENDTyp => NextTxState <= SENDLength; IF (BitCtr="00111" AND WordCtr = "000001") THEN TxWord(7 DOWNTO 0) <= Typ(7 downto 0); ShiftLd <= '1'; BitCtrRes <= '1'; WordCtrRes <= '1'; CRCdo <= '1'; END IF; IF (BitCtr="00111" AND WordCtr = "000000") THEN TxWord(7 DOWNTO 0) <= Data(conv_integer(unsigned(Wordctr(5 downto 0))))(7 DOWNTO 1) &'1'; NextTxState <= SENDData; ShiftLd <= '1'; BitCtrRes <= '1'; WordCtrRes <= '1'; CRCdo <= '1'; END IF; WHEN SENDData => NextTxState <= SENDData; IF (BitCtr="00111" AND WordCtr /= "101101") THEN TxWord(7 DOWNTO 0) <= Data(conv_integer(unsigned(Wordctr(5 downto 0)))+1)(7 DOWNTO 1) & '1'; ShiftLd <= '1'; BitCtrRes <= '1'; WordCtrEn <= '1'; CRCdo <= '1'; END IF; IF (BitCtr="00111" AND WordCtr = "101101") THEN TxWord(7 DOWNTO 0) <= NOT(ShifterCRC(24) & ShifterCRC(25) & ShifterCRC(26) & ShifterCRC(27) & ShifterCRC(28) & ShifterCRC(29) & ShifterCRC(30) & ShifterCRC(31)); NextTxState <= SENDCRC; ShiftLd <= '1'; BitCtrRes <= '1'; WordCtrRes <= '1'; END IF; IF (startTx='1') THEN NextTxState <= SENDSync; TxWord(7 DOWNTO 0) <= "01010101"; ShiftLd <= '1'; BitCtrRes <= '1'; WordCtrRes <= '1'; END IF; WHEN SENDCRC => NextTxState <= SENDCRC; IF (BitCtr="00111" AND WordCtr = "000000") THEN TxWord(7 DOWNTO 0) <= NOT(ShifterCRC(16) & ShifterCRC(17) & ShifterCRC(18) & ShifterCRC(19) & ShifterCRC(20) & ShifterCRC(21) & ShifterCRC(22) & ShifterCRC(23)); ShiftLd <= '1'; BitCtrRes <= '1'; WordCtrEn <= '1'; END IF; IF (BitCtr="00111" AND WordCtr = "000001") THEN TxWord(7 DOWNTO 0) <= NOT(ShifterCRC(8) & ShifterCRC(9) & ShifterCRC(10) & ShifterCRC(11) & ShifterCRC(12) & ShifterCRC(13) & ShifterCRC(14) & ShifterCRC(15)); ShiftLd <= '1'; BitCtrRes <= '1'; WordCtrEn <= '1'; END IF; IF (BitCtr="00111" AND WordCtr = "000010") THEN TxWord(7 DOWNTO 0) <= NOT(ShifterCRC(0) & ShifterCRC(1) & ShifterCRC(2) & ShifterCRC(3) & ShifterCRC(4) & ShifterCRC(5) & ShifterCRC(6) & ShifterCRC(7)); ShiftLd <= '1'; BitCtrRes <= '1'; WordCtrEn <= '1'; END IF; IF (BitCtr="00111" AND WordCtr = "000011") THEN NextTxState <= SwitchOn; TxWord(7 DOWNTO 0) <= "00000000"; BitCtrRes <= '1'; WordCtrRes <= '1'; END IF; IF (startTx='1') THEN NextTxState <= SENDSync; TxWord(7 DOWNTO 0) <= "01010101"; ShiftLd <= '1'; BitCtrRes <= '1'; WordCtrRes <= '1'; END IF; WHEN SwitchOn => NextTxState <= SwitchOn; IF (BitCtr="00111") THEN -- 00011 NextTxState <= Idle; TxWord <= (OTHERS => '0'); ShiftLd <= '1'; BitCtrRes <= '1'; WordCtrRes <= '1'; END IF; IF (startTx='1') THEN NextTxState <= SENDSync; TxWord(7 DOWNTO 0) <= "01010101"; ShiftLd <= '1'; BitCtrRes <= '1'; WordCtrRes <= '1'; END IF; -- WHEN OTHERS => NULL; END CASE; END PROCESS; END spec;