library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity segcontrol is port ( clk : in std_logic; rst_n : in std_logic; isneg : in std_logic; nmb : in std_logic_vector(11 downto 0); dpvec : in std_logic_vector(3 downto 0); an : out std_logic_vector(3 downto 0); seg : out std_logic_vector(6 downto 0); dp : out std_logic ); end segcontrol; architecture Behavioral of segcontrol is type hex2segtype is array(0 to 15) of STD_LOGIC_VECTOR(6 downto 0); constant hex2seg : hex2segtype := ( "1000000", "1111001", "0100100", "0110000", "0011001", "0010010", "0000010", "1111000", "0000000", "0010000", "0001000", "0000011", "1000110", "0100001", "0000110", "0001110" ); signal ancnt : integer range 0 to 50000-1; signal anzw : std_logic_vector(3 downto 0); signal seg1 : std_logic_vector(6 downto 0); signal seg2 : std_logic_vector(6 downto 0); signal seg3 : std_logic_vector(6 downto 0); signal seg4 : std_logic_vector(6 downto 0); begin an <= anzw; seg1 <= hex2seg(to_integer(unsigned(nmb(3 downto 0)))); seg2 <= hex2seg(to_integer(unsigned(nmb(7 downto 4)))); seg3 <= hex2seg(to_integer(unsigned(nmb(11 downto 8)))); seg4 <= "0111111" when (isneg = '1') else "1111111"; anodecounter : process begin wait until rising_edge(clk); if (rst_n = '0') then ancnt <= 0; anzw <= "1111"; else if (ancnt = 50000-1) then -- bei 50 Mhz -> 1 ms ancnt <= 0; case anzw is when "1111" => anzw <= "1110"; seg <= seg1; dp <= dpvec(0); when "1110" => anzw <= "1101"; seg <= seg2; dp <= dpvec(1); when "1101" => anzw <= "1011"; seg <= seg3; dp <= dpvec(2); when "1011" => anzw <= "0111"; seg <= seg4; dp <= dpvec(3); when "0111" => anzw <= "1110"; seg <= seg1; dp <= dpvec(0); when others => anzw <= "1111"; seg <= "1111111"; dp <= '1'; end case; else ancnt <= ancnt + 1; end if; end if; end process; end Behavioral;