#####################################################################################################################################################################################

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity write_c is
Port ( write_start, clk, reset : in std_logic;
		db : in std_logic_vector (7 downto 0);
		write_done, lcd_e_w, lcd_rw : out std_logic;
		lcd_db_w : out std_logic_vector (3 downto 0));
end write_c;

architecture Behavioral of write_c is
type state_sequence is (idle, s1, s2, s3, s4, s5, s6, s7, s8, done);
signal state : state_sequence := idle;
signal i: integer range 0 to 7500000:=0;
begin

process(clk, reset)
begin
	if reset = '1' then 
		state <= idle;
		elsif (clk'event and clk = '1') then
			case state is
				when idle =>
					if write_start = '1' then 	
					state <= s1;
					i <= 2;
					end if;
				when s1 =>
					if i = 0 then 
					state <= s2;
					i <= 12;
					else i <= i-1;
					end if;
				when s2 =>
					if i = 0 then 
					state <= s3;
					i <=1;
					else i <= i-1;
					end if;
				when s3 =>
					if i = 0 then 
					state <= s4;
					i <=50;
					else i <= i-1;
					end if;
				when s4 =>
					if i = 0 then 
					state <= s5;
					i <=2;
					else i <= i-1;
					end if;
				when s5 =>
					if i = 0 then 
					state <= s6;
					i <=12;
					else i <= i-1;
					end if;
				when s6 =>
					if i = 0 then 
					state <= s7;
					i <=1;
					else i <= i-1;
					end if;
				when s7 =>
					if i = 0 then 
					state <= s8;
					i <=2;
					else i <= i-1;
					end if;
				when s8 =>
					if i = 0 then 
					state <= done;
					else i <= i-1;
					end if;
				when done => 
					state <= idle;
				end case;
			end if;
end process;

with state select
	write_done <= '1' when done,
	'0' when others;
	
with state select
	lcd_e_w <= '1' when s2|s6,
	'0' when others;
	
with state select
	lcd_rw <= '1' when idle|s4|s8|done,
	'0' when others;
	
with state select
	lcd_db_w <= db(7 downto 4) when s1|s2|s3,
					db(3 downto 0) when s5|s6|s7,
	"0000" when others;
	
end Behavioral;

###############################################################################################################################################################

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use IEEE.STD_LOGIC_ARITH.ALL;

entity power_on_init is
    Port ( init_start : in  STD_LOGIC;
           init_done : out  STD_LOGIC;
           clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           lcd_db_i : out  STD_LOGIC_VECTOR (3 downto 0);
           lcd_e_i : out  STD_LOGIC);
end power_on_init;

architecture Behavioral of power_on_init is

type state_sequence is (idle,s1,s2,s3,s4,s5,s6,s7,s8,s9,done);
signal state : state_sequence := idle;
signal i : integer range 0 to 750000;

begin

asm: process(clk,reset,init_start)
begin
	if (reset='1') then State <= idle;
	elsif clk'event and (clk='1') then
				case state is
					  when idle=>
						if (init_start='1')then state <= s1;
						i<=0;
						else i<=i+1;
						end if;
					 when s1=>
						if (i=750000)then state <= s2;
						i<=0;
						else i<=i+1;
						end if;
					 when s2=>
						if (i=12)then state <= s3;
						i<=0;
						else i<=i+1;
						end if;
					 when s3=>
						if (i=205000)then state <= s4;
						i<=0;
						else i<=i+1;
						end if;
					 when s4=>
						if (i=12)then state <= s5;
						i<=0;
						else i<=i+1;
						end if;
					 when s5=>
						if (i=5000)then state <= s6;
						i<=0;
						else i<=i+1;
						end if;
					 when s6=>
						if (i=12)then state <= s7;
						i<=0;
						else i<=i+1;
						end if;
					 when s7=>
						if (i=2000)then state <= s8;
						i<=0;
						else i<=i+1;
						end if;
					 when s8=>
						if (i=12)then state <= s9;
						i<=0;
						else i<=i+1;
						end if;
					 when s9=>
						if (i=2000)then state <= done;
						i<=0;
						else i<=i+1;
						end if;	
					 when done=>
						if (i=1)then state <= idle;
						i<=0;
						else i<=i+1;
						end if;	
			end case;
		end if;
	
end process;

with state select
		lcd_e_i <= '1' when s2|s4|s6|s8,
				     '0' when others;
with state select
		lcd_db_i <= "0011" when s2|s4|s6,
				     "0010" when s8,
				     "0000" when others;
with state select
		init_done <= '1' when done,
				     '0' when others;
				     


end Behavioral;

#######################################################################################################################################################################

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Mux1 is
    Port ( lcd_e_i : in  STD_LOGIC;
           lcd_e_w : in  STD_LOGIC;
           MuxS : in  STD_LOGIC;
           lcd_e : out  STD_LOGIC);
end Mux1;

architecture Mux1_a of Mux1 is

begin
with MuxS select
lcd_e <= lcd_e_i when '0',
			lcd_e_w when others;


end Mux1_a;

#######################################################################################################################################################################

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Mux4 is
    Port ( lcd_db_i : in  STD_LOGIC_VECTOR(3 downto 0);
           lcd_db_w : in  STD_LOGIC_VECTOR(3 downto 0);
           MuxS : in  STD_LOGIC;
           lcd_db : out  STD_LOGIC_VECTOR(3 downto 0));
end Mux4;

architecture Mux4_a of Mux4 is

begin
with MuxS select
lcd_db <= lcd_db_i when '0',
			 lcd_db_w when others;


end Mux4_a;