-- vlib work -- vcom pong_480x640.vhd -- vcom pong_480x640_tb.vhd -- vsim -gui pong_480x640_tb -- add wave * -- run 200 ms library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity pong_480x640_tb is end entity pong_480x640_tb; architecture testbench of pong_480x640_tb is constant tb_clk_period : time := 1 sec / 50_000_000; component Basys is port ( clk : in std_logic; --50mhz red : out std_logic_vector(2 downto 0) := "000"; grn : out std_logic_vector(2 downto 0) := "000"; blue : out std_logic_vector(1 downto 0) := "00"; vs : out std_logic := '0'; hs : out std_logic := '0'; taste_hoch : in std_logic; taste_runter : in std_logic ); end component Basys; signal tb_clk : std_logic := '0'; signal tb_red : std_logic_vector(2 downto 0); signal tb_grn : std_logic_vector(2 downto 0); signal tb_blue : std_logic_vector(1 downto 0); signal tb_vs : std_logic; signal tb_hs : std_logic; signal tb_taste_hoch : std_logic := '0'; signal tb_taste_runter : std_logic := '0'; begin tb_clk <= not tb_clk after tb_clk_period / 2; basys_i0 : basys port map ( clk => tb_clk, -- : in std_logic; --50mhz red => tb_red, -- : out std_logic_vector(2 downto 0) := "000"; grn => tb_grn, -- : out std_logic_vector(2 downto 0) := "000"; blue => tb_blue, -- : out std_logic_vector(1 downto 0) := "00"; vs => tb_vs, -- : out std_logic := '0'; hs => tb_hs, -- : out std_logic := '0'; taste_hoch => tb_taste_hoch, -- : in std_logic; taste_runter => tb_taste_runter -- : in std_logic ); end architecture testbench;