Prj_07_DDR2 Project Status
Project File:	Prj_07_DDR2.ise	Implementation State:	New
Module Name:	Top_Modul_VHDL	Errors:
Target Device:	xc3s700a-4fg484	Warnings:
Product Version:	ISE 11.1	Routing Results:
Design Goal:	Balanced	Timing Constraints:
Design Strategy:	Xilinx Default (unlocked)	Final Timing Score:

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report
Translation Report
Map Report
Place and Route Report
Power Report
Post-PAR Static Timing Report
Bitgen Report

 

Secondary Reports			[-]
Report Name	Status	Generated

Date Generated: 03/29/2011 - 18:06:14