library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity bitcnt is generic( InputWidth: integer := 8; -- Input Vektor Größe = 2**InputWidth SliceWidth: integer := 16 -- 1,2,4,8,16,32,64,128,256 -> Bits die kombinatorisch gezählt werden ); port( Clock: in std_logic; Start: in std_logic; Ready: out std_logic; Input: in std_logic_vector(2**InputWidth -1 downto 0); Count: out std_logic_vector(InputWidth downto 0) ); end; architecture behave of bitcnt is type StateType is (stIdle, stCounting, stReady); signal State: StateType; signal BitCount: integer range 0 to Input'Length; signal BitSlice: integer range 0 to SliceWidth; signal Counter: integer range 0 to Input'Length / SliceWidth -1; begin process(Clock) begin if Clock'Event and Clock = '1' then case State is when stIdle => BitCount <= 0; Counter <= 0; if Start = '1' then State <= stCounting; end if; when stCounting => BitCount <= BitCount + BitSlice; if Counter < Counter'High then Counter <= Counter +1; else State <= stReady; end if; when stReady => if Start = '1' then State <= stIdle; end if; end case; end if; end process; process(Input, Counter) variable R: integer range 0 to SliceWidth; variable I: integer range 0 to SliceWidth -1; variable C: integer range Input'Low to Input'High; begin C := Input'Low + Counter * SliceWidth; R := 0; for I in I'Low to I'High loop if Input(C) = '1' then R := R +1; end if; C := C +1; end loop; BitSlice <= R; end process; Count <= conv_std_logic_vector(BitCount, Count'Length) when State = stReady else (others => '0'); Ready <= '1' when State = stReady else '0'; end;