entity counter_g is generic( BIT_WIDTH : positive := 8; CLOCK_ENABLE : boolean := true; DOWN_COUNTER : boolean := false; LOADABLE : boolean := false; RESET_ACTIVE : std_logic := '1' ); port( clk : in std_logic; -- rising edge trigger count reset : in std_logic; -- asynchronous reset en : in std_logic := '0'; -- clock enable, high active ld : in std_logic := '0'; -- data load with rising edge data : in std_logic_vector(BIT_WIDTH-1 downto 0) := (others => '0'); -- preload data count : out std_logic_vector(BIT_WIDTH-1 downto 0) -- counter output ); end counter_g; architecture behavioral of counter_g is signal m_count : std_logic_vector(BIT_WIDTH - 1 downto 0); begin process(clk, reset) begin if (reset = RESET_ACTIVE) then m_count <= (others => '0'); elsif rising_edge(clk) then if LOADABLE and ld = '1' then m_count <= data; end if; if (CLOCK_ENABLE and en = '1') or (not CLOCK_ENABLE) then if (not DOWN_COUNTER) then m_count <= m_count + 1; else m_count <= m_count - 1; end if; end if; end if; end process; count <= m_count; end behavioral;