library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity simple_osc is port (clk50m : in std_logic; res : in std_logic; wave_frq : in std_logic_vector (15 downto 0); wave_form : in std_logic_vector ( 1 downto 0); wave_vol : in std_logic_vector ( 7 downto 0); pwmout : out std_logic ); end simple_osc; architecture Behavioral of simple_osc is component audio_pwm1 is port ( clk50m : in std_logic; res : in std_logic; newdata : out std_logic; dataout : in std_logic_vector (7 downto 0); pwmout : out std_logic ); end component; signal do_wave : std_logic; -- oszillator signal osc_count : std_logic_vector (15 downto 0); signal osc_fsm : std_logic_vector ( 1 downto 0); -- wellenformer signal wave_outv : std_logic_vector (15 downto 0); -- nach volume signal wave_out : std_logic_vector ( 7 downto 0); -- nach volume begin a_out1 : audio_pwm1 port map ( clk50m => clk50m, res => res, newdata => do_wave, dataout => wave_out, pwmout => pwmout ); process (clk50m, res, do_wave) begin if res = '1' then osc_count <= (others => '0'); osc_fsm <= "10"; wave_out <= X"80"; wave_outv <= X"0000"; elsif clk50m'event and clk50m = '1' then if do_wave = '1' then osc_count <= osc_count + wave_frq; osc_fsm <= "01"; end if; case osc_fsm is when "00" => null; -- wait when "01" => case wave_form is --- wellenform berechnen -- saw when "00" => wave_out <= osc_count (15 downto 8); -- sqr when "01" => if osc_count (15) = '1' then wave_out <= (others => '1'); else wave_out <= (others => '0'); end if; -- tri when "10" => if osc_count (15) = '0' then -- steigend -- aktueller wert * 2 wave_out <= osc_count (14 downto 7); else -- fallend -- aktueller wert wave_out <= X"FF" - (osc_count (14 downto 7)); end if; when others => null; end case; osc_fsm <= "10"; when "10" => --wave_outv <= wave_out * wave_vol; osc_fsm <= "11"; when "11" => wave_out <= wave_outv (15 downto 8); osc_fsm <= "00"; when others => null; -- wait end case; end if; wave_outv <= wave_out * wave_vol; -- & "00000000"; end process; end Behavioral;