// MasterOutSlaveIn
#define DD_MOSI DDB2
// MasterInSlaveOut
#define DD_MISO DDB3
// SourceClock
#define DD_SCK	DDB1
// SlaveSelect
#define DD_SS	DDB0

void SPI_MasterInit(void)
{
	/* Set MOSI and SCK and SS to output, all others input */
	DDRB = (1<<DD_MOSI)|(0<<DD_MISO)|(1<<DD_SCK)|(1<<DD_SS);
	
	/* Set SS to '1' (low-active) */
	PORTB = (1<<SS);
		
	/* Enable SPI, Master, set clock rate fck/16  */
	SPCR = (1<<SPE)|(0<<CPHA)|(1<<CPOL)|(1<<MSTR)|(1<<SPR0);
}

char SPI_putc(char data)
{
	/* Start transmission of (Dummy-)Byte */
	SPDR = data;
	/* Wait for transmission complete */
	while(!(SPSR & (1<<SPIF)));
		
	return SPDR;
}