/*
 * owdevice.c
 *
 * Created: 24.01.2012 14:11:43
 *  Author: Tobias Mueller, mail(at)tobynet.de
 */



#include <avr/io.h>
#include <avr/interrupt.h>
#ifdef __AVR_ATmega32__
#include "uart.h"
#include <util/delay.h>
#endif
//DEVICES 
#ifdef __AVR_ATtiny13A__ 
#define OW_PORT PORTB
#define OW_PIN PINB
#define OW_PORTN (1<<PINB3)
#define OW_PINN (1<<PINB3)
#define OW_DDR DDRB

#define SET_LOW OW_DDR|=OW_PINN;OW_PORT&=~OW_PORTN;
#define RESET_LOW OW_DDR&=~OW_PINN;
#define EN_OWINT {GIMSK|=(1<<PCIE);GIFR|=(1<<PCIF);}
#define DIS_OWINT  GIMSK&=~(1<<PCIE);
#define EN_TIMER {TIMSK0 |= (1<<TOIE0); TIFR0|=(1<<TOV0);}
#define DIS_TIMER TIMSK0  &= ~(1<<TOIE0); 


#define OWT_MAX_RESET 82
#define OWT_MIN_RESET 50

#define OWT_RESET_PRESENT 4
#define OWT_PRESENT 20 //144
#define OWT_READLINE 3
#define OWT_LOWTIME 6 //60 Gemessen 58


#define TIMER_INT ISR(TIM0_OVF_vect)
#define PIN_INT ISR(PCINT0_vect)

#define TCNT1 TCNT0

#define DBH PORTB|=(1<<PORTB4);
#define DBL PORTB&=~(1<<PORTB4);

#endif


#ifdef __AVR_ATmega32__
		
#define OW_PORT PORTD
#define OW_PIN PIND
#define OW_PORTN (1<<PIND2)
#define OW_PINN (1<<PIND2)
#define OW_DDR DDRD

#define SET_LOW OW_DDR|=OW_PINN;OW_PORT&=~OW_PORTN;
#define RESET_LOW OW_DDR&=~OW_PINN;
#define EN_OWINT {GICR|=(1<<INT0);GIFR&=~(1<<INTF0);}
#define DIS_OWINT GICR&=~(1<<INT0);
#define EN_TIMER {TIMSK |=(1<<TOIE1);TIFR&=~(TOV1);}
#define DIS_TIMER TIMSK &=~(1<<TOIE1);


#define OWT_MAX_RESET 660
#define OWT_MIN_RESET 400
#define OWT_RESET_PRESENT 30
#define OWT_PRESENT 160 //144
#define OWT_READLINE 40
#define OWT_LOWTIME 43 //60 Gemessen 58
#define OWT_HIGHTTIME 64
#define OWT_PAUSE 10

#define TIMER_INT ISR(TIMER1_OVF_vect) 
#define PIN_INT ISR(INT0_vect)

#define DBH PORTD|=(1<<PORTD4);
#define DBL PORTD&=~(1<<PORTD4);

#define DBH1 PORTD|=(1<<PORTD3);
#define DBL1 PORTD&=~(1<<PORTD3);

#include "uart.h"
volatile uint8_t dbbuf[256];
volatile uint8_t b1,b2;
#endif //ATmega32

volatile uint8_t cbuf; //Empfangspuffer fuer einen Befehl

const uint8_t owid[8]={0x28,0xA2,0xD9,0x84,0x02,0x00,0x00,0x19};
volatile uint8_t bitp;  //Zeiger auf das aktuelle Byte
volatile uint8_t bytep; //Zeuger auf das aktuelle Bit

volatile uint8_t scratchpad[9]={0x50,0x05,0x0,0x0,0x7f,0xff,0x00,0x10,0x0};
volatile uint8_t scrc; //CRC berechnung

volatile uint8_t mode; //Zustand
volatile uint8_t wmode; //wenn 0 wird bei naechsten fallenden Flanke ein 0-Bit geschrieben
volatile uint8_t actbit; //aktuelles Bit
volatile uint8_t srcount; //Zaehler fur search rom

#define OWM_SLEEP 0  
#define OWM_RESET 1
#define OWM_PRESENT 2
#define OWM_READ_COMMAND 3
#define OWM_SEARCH_ROM 4
#define OWM_MATCH_ROM 5
#define OWM_READ_SCRATCHPAD 6
#define OWM_WRITE_SCRATCHPAD 7


#define OWW_NO_WRITE 2
#define OWW_WRITE_1 1
#define OWW_WRITE_0 0

PIN_INT {
	uint8_t p=OW_PIN&OW_PINN;  //Zuerst Flanke abfragen
	uint8_t lwmode=wmode;
	uint8_t lmode=mode;
	if ((lwmode==OWW_WRITE_0)&&(p==0)) {SET_LOW;}   //Wenn notwenig 0-Bit setzten
	//DBL1;
	if (p==0) {
		//if (TCNT1>20024) {TCNT1=0;lmode=OWM_SLEEP;}
		TCNT1=0;
		DIS_OWINT;
		switch (lmode) {
			case OWM_SLEEP:
				TCNT1=0;
				EN_OWINT;
				break;
			case OWM_MATCH_ROM:
			case OWM_WRITE_SCRATCHPAD:
			case OWM_READ_COMMAND: TCNT1=~(OWT_READLINE);
				break;
			case OWM_SEARCH_ROM:
				if (srcount<2) {
					TCNT1=~(OWT_LOWTIME);
					lwmode=OWW_NO_WRITE;		
				} else 
					TCNT1=~(OWT_READLINE);
				break;
			case OWM_READ_SCRATCHPAD:
				TCNT1=~(OWT_LOWTIME);
				lwmode=OWW_NO_WRITE;
				break;
				
		}
		if (lmode!=OWM_SLEEP) EN_TIMER;
	} else { //Steigente flanke 
		if ((TCNT1>OWT_MIN_RESET)&&(TCNT1<OWT_MAX_RESET)) {
			lmode=OWM_RESET; 
			TCNT1=~(OWT_RESET_PRESENT);
			EN_TIMER;
			DIS_OWINT;
		} 
	}
	//_delay_us(6);
	//DBH1;
	mode=lmode;
	wmode=lwmode;
	
}			

	

TIMER_INT {
	uint8_t lwmode=wmode;
	uint8_t lmode=mode;
	uint8_t lbytep=bytep;
	uint8_t lbitp=bitp;
	uint8_t lsrcount=srcount;
	uint8_t lactbit=actbit;
	uint8_t lscrc=scrc;
	
	DIS_TIMER;	
	uint8_t p=((OW_PIN&OW_PINN)==OW_PINN);
	switch (lmode) {
		case OWM_RESET:
			lmode=OWM_PRESENT;
			SET_LOW;
			TCNT1=~(OWT_PRESENT);
			EN_TIMER; //Ueberschreiben vom Hauptprogrammm
			DIS_OWINT;
			break;
		case OWM_PRESENT:
			lmode=OWM_READ_COMMAND;
			//DBH;
			RESET_LOW;
			cbuf=0;lbitp=1;
			break;
		case OWM_READ_COMMAND:
			if (p) {
				cbuf|=lbitp;
			} 
			lbitp=(lbitp<<1);
			if (!lbitp) {
				lbitp=1;
				switch (cbuf) {
					case 0x55:lbytep=0;lmode=OWM_MATCH_ROM;break;
					//case 0xc0:
					case 0xF0:
						lmode=OWM_SEARCH_ROM;
						lsrcount=0;
						lbytep=0;
						lactbit=(owid[lbytep]&lbitp)==lbitp;
						lwmode=lactbit;
						break;
					case 0x4E:
						lmode=OWM_WRITE_SCRATCHPAD;
						lbytep=2;scratchpad[2]=0;
						break;
					case 0x44:  //Start Convert 
					case 0x64:
						ADCSRA|=(1<<ADSC);
						while ((ADCSRA&(1<<ADSC))!=0) {}
						scratchpad[0]=ADCL;
						scratchpad[1]=ADCH;
						lmode=OWM_SLEEP;
						break;
					case 0xBE:
						lmode=OWM_READ_SCRATCHPAD;
						lbytep=0;lscrc=0;
						lactbit=(lbitp&scratchpad[0])==lbitp;
						lwmode=lactbit;
						break;
					default: lmode=OWM_SLEEP;
				}			
				//dbbuf[b1]=cbuf;b1++;
				//if (cbuf==0xC0) 
				//DBL;
			}			
			break;
		case OWM_SEARCH_ROM:
			RESET_LOW;
			lsrcount++;
			switch (lsrcount) {
				case 1:lwmode=!lactbit;break;
				case 3:
					if (p!=(lactbit==1)) {
						lmode=OWM_SLEEP;
					} else {
						lbitp=(lbitp<<1);
						if (lbitp==0) {
							lbitp=1;
							lbytep++;
							if (lbytep>=8) {
								lmode=OWM_SLEEP;
								break;
							}
						}				
						lsrcount=0;
						lactbit=(owid[lbytep]&lbitp)==lbitp;
						lwmode=lactbit;
					}			
					break;			
								
			}
			break;
		case OWM_MATCH_ROM:
			if (p==((owid[lbytep]&lbitp)==lbitp)) {
				lbitp=(lbitp<<1);
				if (!lbitp) {
					lbytep++;
					lbitp=1;
					if (lbytep>=8) {
						lmode=OWM_READ_COMMAND;
						
						cbuf=0;
						break;			
					}
				} 
			} else {
				lmode=OWM_SLEEP;
			}
			break;
		case OWM_WRITE_SCRATCHPAD:
			if (p) {
				scratchpad[lbytep]|=lbitp;
			} 
			lbitp=(lbitp<<1);
			if (!lbitp) {		
				lbytep++;
				lbitp=1;
				if (lbytep==5) {
					lmode=OWM_SLEEP;
					break;
				} else scratchpad[lbytep]=0;
			}			
			break;	
		case OWM_READ_SCRATCHPAD:
			RESET_LOW;
			if ((lscrc&1)!=lactbit) lscrc=(lscrc>>1)^0x8c; else lscrc >>=1;
			lbitp=(lbitp<<1);
			if (!lbitp) {		
				lbytep++;
				lbitp=1;
				if (lbytep>=9) {
					lmode=OWM_SLEEP;
					break;			
				} else if (lbytep==8) scratchpad[8]=lscrc;
			}					
			lactbit=(lbitp&scratchpad[lbytep])==lbitp;
			lwmode=lactbit;
			
			break;
		}
		if (lmode!=OWM_PRESENT) EN_OWINT;
		mode=lmode;
		wmode=lwmode;
		bytep=lbytep;
		bitp=lbitp;
		srcount=lsrcount;
		actbit=lactbit;
		scrc=lscrc;
		
#ifdef _DB_
//					dbbuf[b1]=lmode;b1++;
#endif					
}


int main(void) {
	mode=OWM_SLEEP;
	wmode=OWW_NO_WRITE;
	OW_DDR&=~OW_PINN;
	
	MCUCR=(1<<ISC00); //Any logical change  with attiny13 and atmega32
	
#ifdef __AVR_ATtiny13A__
	CLKPR=0; //9.6Mhz
	//DDRB|=(1<<PORTB4);//DEBUG PORT
	//PORTB|=(1<<PORTB4);
	TIMSK0=0;

	GIMSK=(1<<PCIE);
	PCMSK=(1<<PCINT3);
	TCCR0B=(1<<CS00)|(1<<CS01); //9.6mhz /64 wegen 8 bit Timer also aller 6,666us

    DDRB&=~(1<<PINB2);
	ADMUX=(1<<MUX0);
     ADCSRA= (1<<ADEN) | (1<<ADPS2) | (1<<ADPS1) | (1<<ADPS0);
	 GIMSK|=(1<<PCIE);

#endif

#ifdef __AVR_ATmega32__
	GICR|=(1<<INT0);
	TCCR1B=0x00;
	TCCR1B|=(1<<CS11); //Systemtackt durch 8 also 1 us
	TCNT1=0;
	DDRA&=~(1<<PINA0);
	ADMUX=(1<<REFS0);
    ADCSRA= (1<<ADEN) | (1<<ADPS2) | (1<<ADPS1) | (1<<ADPS0);
	b1=b2=0;
	
	init_uart0(0);
	uart_puts("\nHallo\n");
	char s[16];
	b1=b2=0;
	DDRD|=(1<<PIND4);
	PORTD|=(1<<PORTD4);	
	
	DDRD|=(1<<PIND3);
	PORTD|=(1<<PORTD3);	
	EN_OWINT;
	
#endif

	

	DIS_TIMER;
	
	sei();
		
   
	while(1){
#ifdef __AVR_ATmega32__		
		while(b1!=b2) {
			/*switch (dbbuf[b2]) {
				case OWM_SLEEP:uart_puts("S ");break;
				case 0x81:uart_puts("I");break;
				case 0x82:uart_puts("T");break;
				case 0x83:uart_puts("STRES ");break;
				case 0x84:uart_puts("TSLERR ");break;
				case 0x88:uart_puts("MATCH ");break;
				case OWM_RESET:uart_puts("R ");break;
				case OWM_PRESENT:uart_puts("P ");break;
				case OWM_READ_COMMAND:uart_puts("RC ");break;
				case OWM_SEARCH_ROM:uart_puts("SR ");break;
				default: uart_puts("N");uart_puts(utoa(dbbuf[b2],s,16));uart_puts(" ");
			}*/
			uart_puts(utoa(dbbuf[b2],s,16));uart_puts(" ");
			b2++;
			
		}

#endif
	}

}