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-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:46:29 02/16/2012 
-- Design Name: 
-- Module Name:    main_src - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.definitions.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity main_src is
port (CLK: in std_logic;
      LCD_E: out std_logic;
	  LCD_RS: out std_logic;
	  LCD_RW: out std_logic;
	  SF_D:   out std_logic_vector (7 downto 0);
	  I_DATA: in DATA;
	  TRIGGER: in std_logic;
	  SF_CE0: out std_logic);
end main_src;

architecture Behavioral of main_src is

type RAM_TYPE is array (0 to 35) of std_logic_vector (7 downto 0);
	  signal RAM: RAM_TYPE :=(x"28",x"06",x"0C",x"01", others => x"14");	
	  
	  type DELAY_TYPE is array (0 to 36) of integer range 0 to 1000000;
	  signal DELAY: DELAY_TYPE := (750000,3000,3000,3000,100000,3000,3000,3000,3000,3000,
	                               3000,3000,3000,3000,3000,3000,3000,3000,3000,3000,3000,
											 3000,3000,3000,3000,3000,3000,3000,3000,3000,3000,3000,
											 3000,3000,3000,3000,3000
											 );
								   
	  signal VERZOEGERUNG: INTEGER range 0 to 750 := 0;
	  
	  signal I1: integer range 0 to 36:= 0;
     signal I2: integer range 0 to 37:=0;
	  signal NR: integer range 0 to 31:=0;
     signal ZAEHLER: integer range 0 to 750000;
     signal INKREMENT: std_logic:= '0';
	  signal START:std_logic:='0';
	  signal HELP:std_logic_vector(7 downto 0):=x"00";
	  signal COUNT:integer range 0 to 3000;
	  begin
	  
	  
	  LCD_RW <='0';
	  SF_CE0 <='1';
	  
	  Nummer: process (CLK)
	  begin
 if rising_edge(CLK) then
    if Start='0' and TRIGGER='1' then
	 if COUNT< 3000 then
	 COUNT<=COUNT+1;
	 HELP<=I_DATA(NR);
	 else
	  RAM(2*NR+4)<=HELP(7 downto 4) & "0000";
	  RAM(2*NR+5)<=HELP(3 downto 0) & "0000";
	 if I_DATA(NR+1) /= x"00" then
	 NR<=NR+1;
	 COUNT<=0;
	 else
	 START<='1';
	 end if;
	 end if;
	 end if;
end if;
	 
	 
	
	 
	 
	  end process;
	  
	  DISPLAY: process (CLK)
	  	  
	  begin
	  
if rising_edge(CLK) then
 
	  
	if I1<(2*NR+6) and START='1' then
	
	  if ZAEHLER= DELAY(I2) then
	     if I1 > 3 then
	        LCD_RS<='1';

	     else
	        LCD_RS<='0';
	     end if;
		  
		  if VERZOEGERUNG >10 and VERZOEGERUNG < 740 then
		     LCD_E<='1';
		  else
		  
		     LCD_E<='0';
		  end if;
		  
	  SF_D<=RAM(I1);
	  
	     if VERZOEGERUNG=750 then
	        ZAEHLER<=0;
	        INKREMENT<='1';
	        VERZOEGERUNG<= 0;
	     else
	        VERZOEGERUNG<= VERZOEGERUNG+1;
	     end if;
	  
	  else
	  LCD_E<='0';
	  ZAEHLER<= ZAEHLER+1;
	  INKREMENT<='0';
	  
	  end if;
	  
	  
	  
	  if INKREMENT = '1' then
	  I1<=I1+1;
	  I2<=I2+1;
	  end if;
  end if;	  
end if;
	
end process DISPLAY;
	


end Behavioral;