-- Module Name: square_wave - Behavioral library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity square_wave is port( -- 4 Bit High Steuersignal -- high_in : in unsigned range 1 to 16 := 2; -- 4 Bit Low Steuersignal -- low_in : in unsigned range 1 to 16 := 3; -- Frequenzgeteilte Clock clk_neu : in std_logic; -- Output wave : out std_logic --für testzwecke --q_high : out std_logic_vector(3 downto 0) --q_low : out std_logic_vector(3 downto 0) ; reset_high_temp : in std_logic; reset_low_temp : in std_logic; tick_high_temp: out std_logic; tick_low_temp: out std_logic; raus_temp: out std_logic ); end square_wave; architecture Behavioral of square_wave is -- Toogle: 0 fuer low, 1 fuer high signal tick_high: std_logic; signal tick_low: std_logic; signal raus: std_logic; --signal reset_high_temp: std_logic; --signal reset_low_temp: std_logic; --reset_high, reset_low, high_in, low_in, begin -- Start Wert -> Reset_low = '1' -- process -- sequential statement -- begin -- test vector 1 -- raus <= '0'; -- wait for 50 ns; -- test vector 2 -- raus <= '1'; -- wait for 50 ns; -- end process; -- high counter counter_high: entity work.counter(arch) -- generic map( -- M => high_in, -- N => 4 -- ) Port map ( reset => reset_high_temp,-- or raus, clk => clk_neu, max_tick => tick_high -- q=>q_high ); -- low counter counter_low: entity work.counter(arch) -- generic map( -- M => low_in, -- N => 4 -- ) Port map ( reset => reset_low_temp,-- or not(raus), clk => clk_neu, max_tick => tick_low -- q=>q_low ); -- RS_FF -- RS_FF_Toogle: entity work.RS_FF(arch) -- Port map ( -- s => tick_high, -- r => tick_low, -- clk => clk_neu, -- q_ff => raus -- ); -- RS_FF_Takt RS_FF_Toogle: entity work.RS_FF_Takt(arch) Port map ( s => tick_high, r => tick_low, q_ff => raus ); -- Output tick_high_temp <= tick_high; tick_low_temp <= tick_low; raus_temp <= raus; wave <= raus; end Behavioral;