00001 /*----------------------------------------------------------------------------- 00002 * Copyright (C) 2010 ARM Limited. All rights reserved. 00003 * 00004 * $Date: 29. November 2010 00005 * $Revision: V1.0.3 00006 * 00007 * Project: CMSIS DSP Library 00008 * Title: arm_biquad_cascade_df1_init_f32.c 00009 * 00010 * Description: floating-point Biquad cascade DirectFormI(DF1) filter initialization function. 00011 * 00012 * Target Processor: Cortex-M4/Cortex-M3 00013 * 00014 * Version 1.0.3 2010/11/29 00015 * Re-organized the CMSIS folders and updated documentation. 00016 * 00017 * Version 1.0.2 2010/11/11 00018 * Documentation updated. 00019 * 00020 * Version 1.0.1 2010/10/05 00021 * Production release and review comments incorporated. 00022 * 00023 * Version 1.0.0 2010/09/20 00024 * Production release and review comments incorporated. 00025 * 00026 * Version 0.0.5 2010/04/26 00027 * incorporated review comments and updated with latest CMSIS layer 00028 * 00029 * Version 0.0.3 2010/03/10 00030 * Initial version 00031 * ---------------------------------------------------------------------------*/ 00032 00033 #include "arm_math.h" 00034 00080 void arm_biquad_cascade_df1_init_f32( 00081 arm_biquad_casd_df1_inst_f32 * S, 00082 uint8_t numStages, 00083 float32_t * pCoeffs, 00084 float32_t * pState) 00085 { 00086 /* Assign filter stages */ 00087 S->numStages = numStages; 00088 00089 /* Assign coefficient pointer */ 00090 S->pCoeffs = pCoeffs; 00091 00092 /* Clear state buffer and size is always 4 * numStages */ 00093 memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(float32_t)); 00094 00095 /* Assign state pointer */ 00096 S->pState = pState; 00097 } 00098