cpldfit: version I.26 Xilinx Inc. Fitter Report Design Name: CONTROLLER Date: 2-15-2006, 7:13PM Device Used: XC95144XL-10-TQ100 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 44 /144 ( 31%) 158 /720 ( 22%) 141/432 ( 33%) 44 /144 ( 31%) 35 /81 ( 43%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 11/18 18/54 46/90 4/11 FB2 3/18 19/54 18/90 3/10 FB3 5/18 18/54 16/90 4/10 FB4 5/18 11/54 10/90 5/10 FB5 8/18 17/54 15/90 5/10 FB6 4/18 20/54 20/90 4/10 FB7 4/18 19/54 19/90 4/10 FB8 4/18 19/54 14/90 4/10 ----- ----- ----- ----- 44/144 141/432 158/720 33/81 * - Resource is exhausted ** Global Control Resources ** Signal 'CLK' mapped onto global clock net GCK1. Global output enable net(s) unused. Signal 'RESET' mapped onto global set/reset net GSR. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 36 36 | I/O : 64 73 Output : 33 33 | GCK/IO : 3 3 Bidirectional : 0 0 | GTS/IO : 3 4 GCK : 1 1 | GSR/IO : 1 1 GTS : 0 0 | GSR : 1 1 | ---- ---- Total 71 71 ** Power Data ** There are 44 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************* Summary of Mapped Logic ************************ ** 33 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State RAM_A<2> 8 13 FB1_2 11 I/O O STD FAST RESET RAM_A<1> 8 13 FB1_6 14 I/O O STD FAST RESET RAM_E 5 9 FB1_11 17 I/O O STD FAST RESET PORT1_E 1 6 FB1_15 20 I/O O STD FAST RESET RAM_A<0> 8 13 FB2_11 6 I/O O STD FAST RESET RAM_DO<0> 5 11 FB2_15 9 I/O O STD FAST RESET RAM_DO<1> 5 11 FB2_17 10 I/O O STD FAST RESET RAM_DO<6> 5 11 FB3_5 24 I/O O STD FAST RESET RAM_WR 5 7 FB3_9 28 I/O O STD FAST SET PORT0_E 2 8 FB3_14 32 I/O O STD FAST RESET PORT0_DO<0> 3 9 FB3_17 34 I/O O STD FAST RESET PORT1_DO<0> 2 7 FB4_2 87 I/O O STD FAST RESET PORT1_DO<1> 2 7 FB4_6 90 I/O O STD FAST RESET PORT1_DO<4> 2 7 FB4_9 92 I/O O STD FAST RESET PORT1_DO<5> 2 7 FB4_12 94 I/O O STD FAST RESET PORT1_DO<6> 2 7 FB4_15 96 I/O O STD FAST RESET PORT0_DO<2> 3 9 FB5_2 35 I/O O STD FAST RESET PORT0_DO<7> 3 9 FB5_6 37 I/O O STD FAST RESET PORT1_DO<2> 2 7 FB5_9 40 I/O O STD FAST RESET PORT1_DO<3> 2 7 FB5_12 42 I/O O STD FAST RESET PORT1_DO<7> 2 7 FB5_15 46 I/O O STD FAST RESET RAM_DO<2> 5 11 FB6_2 74 I/O O STD FAST RESET RAM_DO<3> 5 11 FB6_8 78 I/O O STD FAST RESET RAM_DO<4> 5 11 FB6_12 81 I/O O STD FAST RESET RAM_DO<5> 5 11 FB6_17 86 I/O O STD FAST RESET RAM_RD 5 7 FB7_6 53 I/O O STD FAST SET PORT0_DO<3> 3 9 FB7_9 55 I/O O STD FAST RESET PORT0_DO<6> 3 9 FB7_12 58 I/O O STD FAST RESET RAM_A<3> 8 13 FB7_17 61 I/O O STD FAST RESET RAM_DO<7> 5 11 FB8_2 63 I/O O STD FAST RESET PORT0_DO<1> 3 9 FB8_8 66 I/O O STD FAST RESET PORT0_DO<4> 3 9 FB8_11 68 I/O O STD FAST RESET PORT0_DO<5> 3 9 FB8_15 72 I/O O STD FAST RESET ** 11 Buried Nodes ** Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State SM2<0> 2 5 FB1_10 STD RESET SM1_FFd1 2 4 FB1_12 STD RESET PORT1_MODUS<0> 3 7 FB1_13 STD RESET PORT0_MODUS<0> 3 8 FB1_14 STD RESET SM1_FFd4 4 7 FB1_16 STD RESET SM1_FFd2 4 6 FB1_17 STD RESET SM1_FFd3 6 10 FB1_18 STD RESET PORT0_RD_S 1 1 FB3_18 STD RESET PORT1_WR_S 1 1 FB5_16 STD RESET PORT1_RD_S 1 1 FB5_17 STD RESET PORT0_WR_S 1 1 FB5_18 STD RESET ** 38 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use PORT1_A<2> FB1_3 12 I/O I PORT1_DI<2> FB1_9 16 I/O I PORT1_DI<1> FB1_12 18 I/O I RAM_DI<4> FB1_14 19 I/O I CLK FB1_17 22~ GCK/I/O GCK RESET FB2_2 99~ GSR/I/O GSR RAM_DI<6> FB2_5 1 GTS/I/O I PORT0_DI<2> FB2_8 3 GTS/I/O I PORT0_DI<0> FB2_9 4 GTS/I/O I RAM_DI<1> FB2_12 7 I/O I PORT0_DI<1> FB2_14 8 I/O I PORT0_DI<6> FB3_2 23 GCK/I/O I PORT1_A<3> FB3_6 25 I/O I PORT1_DI<3> FB3_8 27 GCK/I/O I PORT0_DI<5> FB3_11 29 I/O I PORT1_DI<4> FB3_12 30 I/O I RAM_DI<5> FB3_15 33 I/O I PORT0_DI<4> FB4_5 89 I/O I PORT0_A<2> FB4_8 91 I/O I PORT0_A<0> FB4_11 93 I/O I PORT0_A<3> FB4_14 95 I/O I PORT0_DI<7> FB4_17 97 I/O I RAM_DI<2> FB5_5 36 I/O I PORT1_DI<7> FB5_11 41 I/O I PORT1_WR FB5_14 43 I/O I PORT1_A<0> FB6_6 77 I/O I PORT0_RD FB6_11 80 I/O I PORT1_DI<6> FB6_15 85 I/O I PORT0_A<1> FB7_2 50 I/O I PORT1_A<1> FB7_5 52 I/O I PORT1_RD FB7_8 54 I/O I RAM_DI<0> FB7_14 59 I/O I PORT0_DI<3> FB8_5 64 I/O I RAM_DI<7> FB8_6 65 I/O I PORT1_DI<0> FB8_9 67 I/O I RAM_DI<3> FB8_12 70 I/O I PORT1_DI<5> FB8_14 71 I/O I PORT0_WR FB8_17 73 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X - Signal used as input to the macrocell logic. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 18/36 Number of signals used by logic mapping into function block: 18 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 \/2 3 FB1_1 (b) (b) RAM_A<2> 8 3<- 0 0 FB1_2 11 I/O O (unused) 0 0 /\1 4 FB1_3 12 I/O I (unused) 0 0 0 5 FB1_4 (b) (unused) 0 0 \/2 3 FB1_5 13 I/O (b) RAM_A<1> 8 3<- 0 0 FB1_6 14 I/O O (unused) 0 0 /\1 4 FB1_7 (b) (b) (unused) 0 0 0 5 FB1_8 15 I/O (unused) 0 0 0 5 FB1_9 16 I/O I SM2<0> 2 0 0 3 FB1_10 (b) (b) RAM_E 5 0 0 0 FB1_11 17 I/O O SM1_FFd1 2 0 0 3 FB1_12 18 I/O I PORT1_MODUS<0> 3 0 0 2 FB1_13 (b) (b) PORT0_MODUS<0> 3 0 0 2 FB1_14 19 I/O I PORT1_E 1 0 0 4 FB1_15 20 I/O O SM1_FFd4 4 0 0 1 FB1_16 (b) (b) SM1_FFd2 4 0 \/1 0 FB1_17 22 GCK/I/O GCK SM1_FFd3 6 1<- 0 0 FB1_18 (b) (b) Signals Used by Logic in Function Block 1: PORT0_A<1> 7: PORT1_A<2> 13: RAM_E 2: PORT0_A<2> 8: PORT1_MODUS<0> 14: SM1_FFd1 3: PORT0_MODUS<0> 9: PORT1_RD_S 15: SM1_FFd2 4: PORT0_RD_S 10: PORT1_WR_S 16: SM1_FFd3 5: PORT0_WR_S 11: RAM_A<1> 17: SM1_FFd4 6: PORT1_A<1> 12: RAM_A<2> 18: SM2<0> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs RAM_A<2> .XXXX.XXXX.X.XXXX....................... 13 RAM_A<1> X.XXXX.XXXX..XXXX....................... 13 SM2<0> ...XX...XX.......X...................... 5 RAM_E ..X.X..X.X..XXXXX....................... 9 SM1_FFd1 .............XXXX....................... 4 PORT1_MODUS<0> .......XXX...XXXX....................... 7 PORT0_MODUS<0> ..XXX........XXXXX...................... 8 PORT1_E .......XX....XXXX....................... 6 SM1_FFd4 ..XXX........XXXX....................... 7 SM1_FFd2 .......XXX....XXX....................... 6 SM1_FFd3 ..XXX..XXX...XXXX....................... 10 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 19/35 Number of signals used by logic mapping into function block: 19 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB2_1 (b) (unused) 0 0 0 5 FB2_2 99 GSR/I/O GSR (unused) 0 0 0 5 FB2_3 (b) (unused) 0 0 0 5 FB2_4 (b) (unused) 0 0 0 5 FB2_5 1 GTS/I/O I (unused) 0 0 0 5 FB2_6 2 GTS/I/O (unused) 0 0 0 5 FB2_7 (b) (unused) 0 0 0 5 FB2_8 3 GTS/I/O I (unused) 0 0 0 5 FB2_9 4 GTS/I/O I (unused) 0 0 \/2 3 FB2_10 (b) (b) RAM_A<0> 8 3<- 0 0 FB2_11 6 I/O O (unused) 0 0 /\1 4 FB2_12 7 I/O I (unused) 0 0 0 5 FB2_13 (b) (unused) 0 0 0 5 FB2_14 8 I/O I RAM_DO<0> 5 0 0 0 FB2_15 9 I/O O (unused) 0 0 0 5 FB2_16 (b) RAM_DO<1> 5 0 0 0 FB2_17 10 I/O O (unused) 0 0 0 5 FB2_18 (b) Signals Used by Logic in Function Block 1: PORT0_A<0> 8: PORT1_DI<0> 14: RAM_DO<0> 2: PORT0_DI<0> 9: PORT1_DI<1> 15: RAM_DO<1> 3: PORT0_DI<1> 10: PORT1_MODUS<0> 16: SM1_FFd1 4: PORT0_MODUS<0> 11: PORT1_RD_S 17: SM1_FFd2 5: PORT0_RD_S 12: PORT1_WR_S 18: SM1_FFd3 6: PORT0_WR_S 13: RAM_A<0> 19: SM1_FFd4 7: PORT1_A<0> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs RAM_A<0> X..XXXX..XXXX..XXXX..................... 13 RAM_DO<0> .X.X.X.X.X.X.X.XXXX..................... 11 RAM_DO<1> ..XX.X..XX.X..XXXXX..................... 11 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB3 *********************************** Number of function block inputs used/remaining: 18/36 Number of signals used by logic mapping into function block: 18 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB3_1 (b) (unused) 0 0 0 5 FB3_2 23 GCK/I/O I (unused) 0 0 0 5 FB3_3 (b) (unused) 0 0 0 5 FB3_4 (b) RAM_DO<6> 5 0 0 0 FB3_5 24 I/O O (unused) 0 0 0 5 FB3_6 25 I/O I (unused) 0 0 0 5 FB3_7 (b) (unused) 0 0 0 5 FB3_8 27 GCK/I/O I RAM_WR 5 0 0 0 FB3_9 28 I/O O (unused) 0 0 0 5 FB3_10 (b) (unused) 0 0 0 5 FB3_11 29 I/O I (unused) 0 0 0 5 FB3_12 30 I/O I (unused) 0 0 0 5 FB3_13 (b) PORT0_E 2 0 0 3 FB3_14 32 I/O O (unused) 0 0 0 5 FB3_15 33 I/O I (unused) 0 0 0 5 FB3_16 (b) PORT0_DO<0> 3 0 0 2 FB3_17 34 I/O O PORT0_RD_S 1 0 0 4 FB3_18 (b) (b) Signals Used by Logic in Function Block 1: PORT0_DI<6> 7: PORT0_WR_S 13: RAM_WR 2: PORT0_DO<0> 8: PORT1_DI<6> 14: SM1_FFd1 3: PORT0_E 9: PORT1_MODUS<0> 15: SM1_FFd2 4: PORT0_MODUS<0> 10: PORT1_WR_S 16: SM1_FFd3 5: PORT0_RD 11: RAM_DI<0> 17: SM1_FFd4 6: PORT0_RD_S 12: RAM_DO<6> 18: SM2<0> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs RAM_DO<6> X..X..XXXX.X.XXXX....................... 11 RAM_WR ......X..X..XXXXX....................... 7 PORT0_E ..XX.X.......XXXXX...................... 8 PORT0_DO<0> .X.X.X....X..XXXXX...................... 9 PORT0_RD_S ....X................................... 1 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** Number of function block inputs used/remaining: 11/43 Number of signals used by logic mapping into function block: 11 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB4_1 (b) PORT1_DO<0> 2 0 0 3 FB4_2 87 I/O O (unused) 0 0 0 5 FB4_3 (b) (unused) 0 0 0 5 FB4_4 (b) (unused) 0 0 0 5 FB4_5 89 I/O I PORT1_DO<1> 2 0 0 3 FB4_6 90 I/O O (unused) 0 0 0 5 FB4_7 (b) (unused) 0 0 0 5 FB4_8 91 I/O I PORT1_DO<4> 2 0 0 3 FB4_9 92 I/O O (unused) 0 0 0 5 FB4_10 (b) (unused) 0 0 0 5 FB4_11 93 I/O I PORT1_DO<5> 2 0 0 3 FB4_12 94 I/O O (unused) 0 0 0 5 FB4_13 (b) (unused) 0 0 0 5 FB4_14 95 I/O I PORT1_DO<6> 2 0 0 3 FB4_15 96 I/O O (unused) 0 0 0 5 FB4_16 (b) (unused) 0 0 0 5 FB4_17 97 I/O I (unused) 0 0 0 5 FB4_18 (b) Signals Used by Logic in Function Block 1: PORT1_MODUS<0> 5: RAM_DI<4> 9: SM1_FFd2 2: PORT1_RD_S 6: RAM_DI<5> 10: SM1_FFd3 3: RAM_DI<0> 7: RAM_DI<6> 11: SM1_FFd4 4: RAM_DI<1> 8: SM1_FFd1 Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs PORT1_DO<0> XXX....XXXX............................. 7 PORT1_DO<1> XX.X...XXXX............................. 7 PORT1_DO<4> XX..X..XXXX............................. 7 PORT1_DO<5> XX...X.XXXX............................. 7 PORT1_DO<6> XX....XXXXX............................. 7 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB5 *********************************** Number of function block inputs used/remaining: 17/37 Number of signals used by logic mapping into function block: 17 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB5_1 (b) PORT0_DO<2> 3 0 0 2 FB5_2 35 I/O O (unused) 0 0 0 5 FB5_3 (b) (unused) 0 0 0 5 FB5_4 (b) (unused) 0 0 0 5 FB5_5 36 I/O I PORT0_DO<7> 3 0 0 2 FB5_6 37 I/O O (unused) 0 0 0 5 FB5_7 (b) (unused) 0 0 0 5 FB5_8 39 I/O PORT1_DO<2> 2 0 0 3 FB5_9 40 I/O O (unused) 0 0 0 5 FB5_10 (b) (unused) 0 0 0 5 FB5_11 41 I/O I PORT1_DO<3> 2 0 0 3 FB5_12 42 I/O O (unused) 0 0 0 5 FB5_13 (b) (unused) 0 0 0 5 FB5_14 43 I/O I PORT1_DO<7> 2 0 0 3 FB5_15 46 I/O O PORT1_WR_S 1 0 0 4 FB5_16 (b) (b) PORT1_RD_S 1 0 0 4 FB5_17 49 I/O (b) PORT0_WR_S 1 0 0 4 FB5_18 (b) (b) Signals Used by Logic in Function Block 1: PORT0_DO<2> 7: PORT1_RD 13: SM1_FFd1 2: PORT0_DO<7> 8: PORT1_RD_S 14: SM1_FFd2 3: PORT0_MODUS<0> 9: PORT1_WR 15: SM1_FFd3 4: PORT0_RD_S 10: RAM_DI<2> 16: SM1_FFd4 5: PORT0_WR 11: RAM_DI<3> 17: SM2<0> 6: PORT1_MODUS<0> 12: RAM_DI<7> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs PORT0_DO<2> X.XX.....X..XXXXX....................... 9 PORT0_DO<7> .XXX.......XXXXXX....................... 9 PORT1_DO<2> .....X.X.X..XXXX........................ 7 PORT1_DO<3> .....X.X..X.XXXX........................ 7 PORT1_DO<7> .....X.X...XXXXX........................ 7 PORT1_WR_S ........X............................... 1 PORT1_RD_S ......X................................. 1 PORT0_WR_S ....X................................... 1 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB6 *********************************** Number of function block inputs used/remaining: 20/34 Number of signals used by logic mapping into function block: 20 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB6_1 (b) RAM_DO<2> 5 0 0 0 FB6_2 74 I/O O (unused) 0 0 0 5 FB6_3 (b) (unused) 0 0 0 5 FB6_4 (b) (unused) 0 0 0 5 FB6_5 76 I/O (unused) 0 0 0 5 FB6_6 77 I/O I (unused) 0 0 0 5 FB6_7 (b) RAM_DO<3> 5 0 0 0 FB6_8 78 I/O O (unused) 0 0 0 5 FB6_9 79 I/O (unused) 0 0 0 5 FB6_10 (b) (unused) 0 0 0 5 FB6_11 80 I/O I RAM_DO<4> 5 0 0 0 FB6_12 81 I/O O (unused) 0 0 0 5 FB6_13 (b) (unused) 0 0 0 5 FB6_14 82 I/O (unused) 0 0 0 5 FB6_15 85 I/O I (unused) 0 0 0 5 FB6_16 (b) RAM_DO<5> 5 0 0 0 FB6_17 86 I/O O (unused) 0 0 0 5 FB6_18 (b) Signals Used by Logic in Function Block 1: PORT0_DI<2> 8: PORT1_DI<3> 15: RAM_DO<4> 2: PORT0_DI<3> 9: PORT1_DI<4> 16: RAM_DO<5> 3: PORT0_DI<4> 10: PORT1_DI<5> 17: SM1_FFd1 4: PORT0_DI<5> 11: PORT1_MODUS<0> 18: SM1_FFd2 5: PORT0_MODUS<0> 12: PORT1_WR_S 19: SM1_FFd3 6: PORT0_WR_S 13: RAM_DO<2> 20: SM1_FFd4 7: PORT1_DI<2> 14: RAM_DO<3> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs RAM_DO<2> X...XXX...XXX...XXXX.................... 11 RAM_DO<3> .X..XX.X..XX.X..XXXX.................... 11 RAM_DO<4> ..X.XX..X.XX..X.XXXX.................... 11 RAM_DO<5> ...XXX...XXX...XXXXX.................... 11 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB7 *********************************** Number of function block inputs used/remaining: 19/35 Number of signals used by logic mapping into function block: 19 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB7_1 (b) (unused) 0 0 0 5 FB7_2 50 I/O I (unused) 0 0 0 5 FB7_3 (b) (unused) 0 0 0 5 FB7_4 (b) (unused) 0 0 0 5 FB7_5 52 I/O I RAM_RD 5 0 0 0 FB7_6 53 I/O O (unused) 0 0 0 5 FB7_7 (b) (unused) 0 0 0 5 FB7_8 54 I/O I PORT0_DO<3> 3 0 0 2 FB7_9 55 I/O O (unused) 0 0 0 5 FB7_10 (b) (unused) 0 0 0 5 FB7_11 56 I/O PORT0_DO<6> 3 0 0 2 FB7_12 58 I/O O (unused) 0 0 0 5 FB7_13 (b) (unused) 0 0 0 5 FB7_14 59 I/O I (unused) 0 0 0 5 FB7_15 60 I/O (unused) 0 0 \/2 3 FB7_16 (b) (b) RAM_A<3> 8 3<- 0 0 FB7_17 61 I/O O (unused) 0 0 /\1 4 FB7_18 (b) (b) Signals Used by Logic in Function Block 1: PORT0_A<3> 8: PORT1_MODUS<0> 14: RAM_RD 2: PORT0_DO<3> 9: PORT1_RD_S 15: SM1_FFd1 3: PORT0_DO<6> 10: PORT1_WR_S 16: SM1_FFd2 4: PORT0_MODUS<0> 11: RAM_A<3> 17: SM1_FFd3 5: PORT0_RD_S 12: RAM_DI<3> 18: SM1_FFd4 6: PORT0_WR_S 13: RAM_DI<6> 19: SM2<0> 7: PORT1_A<3> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs RAM_RD ....X...X....XXXXX...................... 7 PORT0_DO<3> .X.XX......X..XXXXX..................... 9 PORT0_DO<6> ..XXX.......X.XXXXX..................... 9 RAM_A<3> X..XXXXXXXX...XXXX...................... 13 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB8 *********************************** Number of function block inputs used/remaining: 19/35 Number of signals used by logic mapping into function block: 19 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB8_1 (b) RAM_DO<7> 5 0 0 0 FB8_2 63 I/O O (unused) 0 0 0 5 FB8_3 (b) (unused) 0 0 0 5 FB8_4 (b) (unused) 0 0 0 5 FB8_5 64 I/O I (unused) 0 0 0 5 FB8_6 65 I/O I (unused) 0 0 0 5 FB8_7 (b) PORT0_DO<1> 3 0 0 2 FB8_8 66 I/O O (unused) 0 0 0 5 FB8_9 67 I/O I (unused) 0 0 0 5 FB8_10 (b) PORT0_DO<4> 3 0 0 2 FB8_11 68 I/O O (unused) 0 0 0 5 FB8_12 70 I/O I (unused) 0 0 0 5 FB8_13 (b) (unused) 0 0 0 5 FB8_14 71 I/O I PORT0_DO<5> 3 0 0 2 FB8_15 72 I/O O (unused) 0 0 0 5 FB8_16 (b) (unused) 0 0 0 5 FB8_17 73 I/O I (unused) 0 0 0 5 FB8_18 (b) Signals Used by Logic in Function Block 1: PORT0_DI<7> 8: PORT1_DI<7> 14: RAM_DO<7> 2: PORT0_DO<1> 9: PORT1_MODUS<0> 15: SM1_FFd1 3: PORT0_DO<4> 10: PORT1_WR_S 16: SM1_FFd2 4: PORT0_DO<5> 11: RAM_DI<1> 17: SM1_FFd3 5: PORT0_MODUS<0> 12: RAM_DI<4> 18: SM1_FFd4 6: PORT0_RD_S 13: RAM_DI<5> 19: SM2<0> 7: PORT0_WR_S Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs RAM_DO<7> X...X.XXXX...XXXXX...................... 11 PORT0_DO<1> .X..XX....X...XXXXX..................... 9 PORT0_DO<4> ..X.XX.....X..XXXXX..................... 9 PORT0_DO<5> ...XXX......X.XXXXX..................... 9 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** FTCPE_PORT0_DO0: FTCPE port map (PORT0_DO(0),PORT0_DO_T(0),CLK,NOT RESET,'0'); PORT0_DO_T(0) <= ((PORT0_DO(0) AND SM2(0)) OR (NOT PORT0_MODUS(0) AND PORT0_DO(0) AND NOT RAM_DI(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_RD_S) OR (NOT PORT0_MODUS(0) AND NOT PORT0_DO(0) AND RAM_DI(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND SM1_FFd2 AND NOT SM1_FFd1 AND NOT SM2(0) AND NOT PORT0_RD_S)); FTCPE_PORT0_DO1: FTCPE port map (PORT0_DO(1),PORT0_DO_T(1),CLK,NOT RESET,'0'); PORT0_DO_T(1) <= ((PORT0_DO(1) AND SM2(0)) OR (NOT PORT0_MODUS(0) AND PORT0_DO(1) AND NOT RAM_DI(1) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_RD_S) OR (NOT PORT0_MODUS(0) AND NOT PORT0_DO(1) AND RAM_DI(1) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND SM1_FFd2 AND NOT SM1_FFd1 AND NOT SM2(0) AND NOT PORT0_RD_S)); FTCPE_PORT0_DO2: FTCPE port map (PORT0_DO(2),PORT0_DO_T(2),CLK,NOT RESET,'0'); PORT0_DO_T(2) <= ((PORT0_DO(2) AND SM2(0)) OR (NOT PORT0_MODUS(0) AND PORT0_DO(2) AND NOT RAM_DI(2) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_RD_S) OR (NOT PORT0_MODUS(0) AND NOT PORT0_DO(2) AND RAM_DI(2) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND SM1_FFd2 AND NOT SM1_FFd1 AND NOT SM2(0) AND NOT PORT0_RD_S)); FTCPE_PORT0_DO3: FTCPE port map (PORT0_DO(3),PORT0_DO_T(3),CLK,NOT RESET,'0'); PORT0_DO_T(3) <= ((PORT0_DO(3) AND SM2(0)) OR (NOT PORT0_MODUS(0) AND PORT0_DO(3) AND NOT RAM_DI(3) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_RD_S) OR (NOT PORT0_MODUS(0) AND NOT PORT0_DO(3) AND RAM_DI(3) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND SM1_FFd2 AND NOT SM1_FFd1 AND NOT SM2(0) AND NOT PORT0_RD_S)); FTCPE_PORT0_DO4: FTCPE port map (PORT0_DO(4),PORT0_DO_T(4),CLK,NOT RESET,'0'); PORT0_DO_T(4) <= ((PORT0_DO(4) AND SM2(0)) OR (NOT PORT0_MODUS(0) AND PORT0_DO(4) AND NOT RAM_DI(4) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_RD_S) OR (NOT PORT0_MODUS(0) AND NOT PORT0_DO(4) AND RAM_DI(4) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND SM1_FFd2 AND NOT SM1_FFd1 AND NOT SM2(0) AND NOT PORT0_RD_S)); FTCPE_PORT0_DO5: FTCPE port map (PORT0_DO(5),PORT0_DO_T(5),CLK,NOT RESET,'0'); PORT0_DO_T(5) <= ((PORT0_DO(5) AND SM2(0)) OR (NOT PORT0_MODUS(0) AND PORT0_DO(5) AND NOT RAM_DI(5) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_RD_S) OR (NOT PORT0_MODUS(0) AND NOT PORT0_DO(5) AND RAM_DI(5) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND SM1_FFd2 AND NOT SM1_FFd1 AND NOT SM2(0) AND NOT PORT0_RD_S)); FTCPE_PORT0_DO6: FTCPE port map (PORT0_DO(6),PORT0_DO_T(6),CLK,NOT RESET,'0'); PORT0_DO_T(6) <= ((PORT0_DO(6) AND SM2(0)) OR (NOT PORT0_MODUS(0) AND PORT0_DO(6) AND NOT RAM_DI(6) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_RD_S) OR (NOT PORT0_MODUS(0) AND NOT PORT0_DO(6) AND RAM_DI(6) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND SM1_FFd2 AND NOT SM1_FFd1 AND NOT SM2(0) AND NOT PORT0_RD_S)); FTCPE_PORT0_DO7: FTCPE port map (PORT0_DO(7),PORT0_DO_T(7),CLK,NOT RESET,'0'); PORT0_DO_T(7) <= ((PORT0_DO(7) AND SM2(0)) OR (NOT PORT0_MODUS(0) AND PORT0_DO(7) AND NOT RAM_DI(7) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_RD_S) OR (NOT PORT0_MODUS(0) AND NOT PORT0_DO(7) AND RAM_DI(7) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND SM1_FFd2 AND NOT SM1_FFd1 AND NOT SM2(0) AND NOT PORT0_RD_S)); FDCPE_PORT0_E: FDCPE port map (PORT0_E,PORT0_E_D,CLK,NOT RESET,'0'); PORT0_E_D <= ((PORT0_E AND NOT SM2(0)) OR (NOT PORT0_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND SM1_FFd2 AND NOT SM1_FFd1 AND NOT SM2(0) AND NOT PORT0_RD_S)); FTCPE_PORT0_MODUS0: FTCPE port map (PORT0_MODUS(0),PORT0_MODUS_T(0),CLK,NOT RESET,'0'); PORT0_MODUS_T(0) <= ((NOT PORT0_MODUS(0) AND NOT SM2(0) AND PORT0_WR_S AND PORT0_RD_S) OR (PORT0_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_WR_S) OR (PORT0_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_RD_S)); FDCPE_PORT0_RD_S: FDCPE port map (PORT0_RD_S,PORT0_RD,CLK,'0','0'); FDCPE_PORT0_WR_S: FDCPE port map (PORT0_WR_S,PORT0_WR,CLK,'0','0'); FDCPE_PORT1_DO0: FDCPE port map (PORT1_DO(0),RAM_DI(0),CLK,NOT RESET,'0',PORT1_DO_CE(0)); PORT1_DO_CE(0) <= (NOT PORT1_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND SM1_FFd1 AND NOT PORT1_RD_S); FDCPE_PORT1_DO1: FDCPE port map (PORT1_DO(1),RAM_DI(1),CLK,NOT RESET,'0',PORT1_DO_CE(1)); PORT1_DO_CE(1) <= (NOT PORT1_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND SM1_FFd1 AND NOT PORT1_RD_S); FDCPE_PORT1_DO2: FDCPE port map (PORT1_DO(2),RAM_DI(2),CLK,NOT RESET,'0',PORT1_DO_CE(2)); PORT1_DO_CE(2) <= (NOT PORT1_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND SM1_FFd1 AND NOT PORT1_RD_S); FDCPE_PORT1_DO3: FDCPE port map (PORT1_DO(3),RAM_DI(3),CLK,NOT RESET,'0',PORT1_DO_CE(3)); PORT1_DO_CE(3) <= (NOT PORT1_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND SM1_FFd1 AND NOT PORT1_RD_S); FDCPE_PORT1_DO4: FDCPE port map (PORT1_DO(4),RAM_DI(4),CLK,NOT RESET,'0',PORT1_DO_CE(4)); PORT1_DO_CE(4) <= (NOT PORT1_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND SM1_FFd1 AND NOT PORT1_RD_S); FDCPE_PORT1_DO5: FDCPE port map (PORT1_DO(5),RAM_DI(5),CLK,NOT RESET,'0',PORT1_DO_CE(5)); PORT1_DO_CE(5) <= (NOT PORT1_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND SM1_FFd1 AND NOT PORT1_RD_S); FDCPE_PORT1_DO6: FDCPE port map (PORT1_DO(6),RAM_DI(6),CLK,NOT RESET,'0',PORT1_DO_CE(6)); PORT1_DO_CE(6) <= (NOT PORT1_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND SM1_FFd1 AND NOT PORT1_RD_S); FDCPE_PORT1_DO7: FDCPE port map (PORT1_DO(7),RAM_DI(7),CLK,NOT RESET,'0',PORT1_DO_CE(7)); PORT1_DO_CE(7) <= (NOT PORT1_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND SM1_FFd1 AND NOT PORT1_RD_S); FDCPE_PORT1_E: FDCPE port map (PORT1_E,'1',CLK,NOT RESET,'0',PORT1_E_CE); PORT1_E_CE <= (NOT PORT1_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND SM1_FFd1 AND NOT PORT1_RD_S); FTCPE_PORT1_MODUS0: FTCPE port map (PORT1_MODUS(0),PORT1_MODUS_T(0),CLK,NOT RESET,'0'); PORT1_MODUS_T(0) <= ((NOT PORT1_MODUS(0) AND PORT1_WR_S AND PORT1_RD_S) OR (PORT1_MODUS(0) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT1_WR_S) OR (PORT1_MODUS(0) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT1_RD_S)); FDCPE_PORT1_RD_S: FDCPE port map (PORT1_RD_S,PORT1_RD,CLK,'0','0'); FDCPE_PORT1_WR_S: FDCPE port map (PORT1_WR_S,PORT1_WR,CLK,'0','0'); FTCPE_RAM_A0: FTCPE port map (RAM_A(0),RAM_A_T(0),CLK,NOT RESET,'0'); RAM_A_T(0) <= ((EXP14_.EXP) OR (EXP15_.EXP) OR (PORT1_MODUS(0) AND RAM_A(0) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_WR_S AND NOT PORT1_A(0)) OR (PORT1_MODUS(0) AND RAM_A(0) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_RD_S AND NOT PORT1_A(0)) OR (PORT1_MODUS(0) AND NOT RAM_A(0) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_WR_S AND PORT1_A(0)) OR (PORT1_MODUS(0) AND NOT RAM_A(0) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_RD_S AND PORT1_A(0)) OR (PORT0_MODUS(0) AND RAM_A(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_WR_S AND NOT PORT0_A(0))); FTCPE_RAM_A1: FTCPE port map (RAM_A(1),RAM_A_T(1),CLK,NOT RESET,'0'); RAM_A_T(1) <= ((EXP12_.EXP) OR (EXP13_.EXP) OR (PORT1_MODUS(0) AND RAM_A(1) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_WR_S AND NOT PORT1_A(1)) OR (PORT1_MODUS(0) AND RAM_A(1) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_RD_S AND NOT PORT1_A(1)) OR (PORT1_MODUS(0) AND NOT RAM_A(1) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_WR_S AND PORT1_A(1)) OR (PORT1_MODUS(0) AND NOT RAM_A(1) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_RD_S AND PORT1_A(1)) OR (PORT0_MODUS(0) AND RAM_A(1) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_WR_S AND NOT PORT0_A(1))); FTCPE_RAM_A2: FTCPE port map (RAM_A(2),RAM_A_T(2),CLK,NOT RESET,'0'); RAM_A_T(2) <= ((EXP10_.EXP) OR (EXP11_.EXP) OR (PORT1_MODUS(0) AND RAM_A(2) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_WR_S AND NOT PORT1_A(2)) OR (PORT1_MODUS(0) AND RAM_A(2) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_RD_S AND NOT PORT1_A(2)) OR (PORT1_MODUS(0) AND NOT RAM_A(2) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_WR_S AND PORT1_A(2)) OR (PORT1_MODUS(0) AND NOT RAM_A(2) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_RD_S AND PORT1_A(2)) OR (PORT0_MODUS(0) AND RAM_A(2) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_WR_S AND NOT PORT0_A(2))); FTCPE_RAM_A3: FTCPE port map (RAM_A(3),RAM_A_T(3),CLK,NOT RESET,'0'); RAM_A_T(3) <= ((EXP16_.EXP) OR (EXP17_.EXP) OR (PORT1_MODUS(0) AND RAM_A(3) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_WR_S AND NOT PORT1_A(3)) OR (PORT1_MODUS(0) AND RAM_A(3) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_RD_S AND NOT PORT1_A(3)) OR (PORT1_MODUS(0) AND NOT RAM_A(3) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_WR_S AND PORT1_A(3)) OR (PORT1_MODUS(0) AND NOT RAM_A(3) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_RD_S AND PORT1_A(3)) OR (PORT0_MODUS(0) AND RAM_A(3) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_WR_S AND NOT PORT0_A(3))); FDCPE_RAM_DO0: FDCPE port map (RAM_DO(0),RAM_DO_D(0),CLK,NOT RESET,'0'); RAM_DO_D(0) <= ((RAM_DO(0) AND SM1_FFd4) OR (RAM_DO(0) AND SM1_FFd2) OR (RAM_DO(0) AND NOT SM1_FFd3 AND SM1_FFd1) OR (PORT1_MODUS(0) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_WR_S AND PORT1_DI(0)) OR (PORT0_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_WR_S AND PORT0_DI(0))); FDCPE_RAM_DO1: FDCPE port map (RAM_DO(1),RAM_DO_D(1),CLK,NOT RESET,'0'); RAM_DO_D(1) <= ((RAM_DO(1) AND SM1_FFd4) OR (RAM_DO(1) AND SM1_FFd2) OR (RAM_DO(1) AND NOT SM1_FFd3 AND SM1_FFd1) OR (PORT1_MODUS(0) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_WR_S AND PORT1_DI(1)) OR (PORT0_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_WR_S AND PORT0_DI(1))); FDCPE_RAM_DO2: FDCPE port map (RAM_DO(2),RAM_DO_D(2),CLK,NOT RESET,'0'); RAM_DO_D(2) <= ((RAM_DO(2) AND SM1_FFd4) OR (RAM_DO(2) AND SM1_FFd2) OR (RAM_DO(2) AND NOT SM1_FFd3 AND SM1_FFd1) OR (PORT1_MODUS(0) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_WR_S AND PORT1_DI(2)) OR (PORT0_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_WR_S AND PORT0_DI(2))); FDCPE_RAM_DO3: FDCPE port map (RAM_DO(3),RAM_DO_D(3),CLK,NOT RESET,'0'); RAM_DO_D(3) <= ((RAM_DO(3) AND SM1_FFd4) OR (RAM_DO(3) AND SM1_FFd2) OR (RAM_DO(3) AND NOT SM1_FFd3 AND SM1_FFd1) OR (PORT1_MODUS(0) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_WR_S AND PORT1_DI(3)) OR (PORT0_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_WR_S AND PORT0_DI(3))); FDCPE_RAM_DO4: FDCPE port map (RAM_DO(4),RAM_DO_D(4),CLK,NOT RESET,'0'); RAM_DO_D(4) <= ((RAM_DO(4) AND SM1_FFd4) OR (RAM_DO(4) AND SM1_FFd2) OR (RAM_DO(4) AND NOT SM1_FFd3 AND SM1_FFd1) OR (PORT1_MODUS(0) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_WR_S AND PORT1_DI(4)) OR (PORT0_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_WR_S AND PORT0_DI(4))); FDCPE_RAM_DO5: FDCPE port map (RAM_DO(5),RAM_DO_D(5),CLK,NOT RESET,'0'); RAM_DO_D(5) <= ((RAM_DO(5) AND SM1_FFd4) OR (RAM_DO(5) AND SM1_FFd2) OR (RAM_DO(5) AND NOT SM1_FFd3 AND SM1_FFd1) OR (PORT1_MODUS(0) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_WR_S AND PORT1_DI(5)) OR (PORT0_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_WR_S AND PORT0_DI(5))); FDCPE_RAM_DO6: FDCPE port map (RAM_DO(6),RAM_DO_D(6),CLK,NOT RESET,'0'); RAM_DO_D(6) <= ((RAM_DO(6) AND SM1_FFd4) OR (RAM_DO(6) AND SM1_FFd2) OR (RAM_DO(6) AND NOT SM1_FFd3 AND SM1_FFd1) OR (PORT1_MODUS(0) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_WR_S AND PORT1_DI(6)) OR (PORT0_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_WR_S AND PORT0_DI(6))); FDCPE_RAM_DO7: FDCPE port map (RAM_DO(7),RAM_DO_D(7),CLK,NOT RESET,'0'); RAM_DO_D(7) <= ((RAM_DO(7) AND SM1_FFd4) OR (RAM_DO(7) AND SM1_FFd2) OR (RAM_DO(7) AND NOT SM1_FFd3 AND SM1_FFd1) OR (PORT1_MODUS(0) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_WR_S AND PORT1_DI(7)) OR (PORT0_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_WR_S AND PORT0_DI(7))); FDCPE_RAM_E: FDCPE port map (RAM_E,RAM_E_D,CLK,NOT RESET,'0'); RAM_E_D <= ((RAM_E AND SM1_FFd4) OR (RAM_E AND SM1_FFd2) OR (RAM_E AND NOT SM1_FFd3 AND SM1_FFd1) OR (PORT1_MODUS(0) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_WR_S) OR (PORT0_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_WR_S)); FDCPE_RAM_RD: FDCPE port map (RAM_RD,RAM_RD_D,CLK,'0',NOT RESET); RAM_RD_D <= ((NOT RAM_RD AND NOT SM1_FFd3 AND NOT SM1_FFd4) OR (NOT RAM_RD AND NOT SM1_FFd4 AND NOT SM1_FFd2) OR (NOT RAM_RD AND SM1_FFd3 AND SM1_FFd4 AND NOT SM1_FFd1) OR (SM1_FFd3 AND NOT SM1_FFd4 AND SM1_FFd2 AND NOT PORT1_RD_S) OR (NOT SM1_FFd3 AND SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_RD_S)); FDCPE_RAM_WR: FDCPE port map (RAM_WR,RAM_WR_D,CLK,'0',NOT RESET); RAM_WR_D <= ((NOT RAM_WR AND NOT SM1_FFd3 AND NOT SM1_FFd4) OR (NOT RAM_WR AND NOT SM1_FFd4 AND NOT SM1_FFd2) OR (NOT RAM_WR AND SM1_FFd3 AND SM1_FFd4 AND NOT SM1_FFd1) OR (SM1_FFd3 AND NOT SM1_FFd4 AND SM1_FFd2 AND NOT PORT1_WR_S) OR (NOT SM1_FFd3 AND SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_WR_S)); FDCPE_SM1_FFd1: FDCPE port map (SM1_FFd1,SM1_FFd1_D,CLK,NOT RESET,'0'); SM1_FFd1_D <= ((NOT SM1_FFd4 AND SM1_FFd1) OR (SM1_FFd3 AND SM1_FFd4 AND SM1_FFd2)); FDCPE_SM1_FFd2: FDCPE port map (SM1_FFd2,SM1_FFd2_D,CLK,NOT RESET,'0'); SM1_FFd2_D <= ((NOT SM1_FFd4 AND SM1_FFd2) OR (SM1_FFd3 AND SM1_FFd4 AND NOT SM1_FFd2) OR (PORT1_MODUS(0) AND SM1_FFd3 AND NOT SM1_FFd2 AND NOT PORT1_WR_S) OR (PORT1_MODUS(0) AND SM1_FFd3 AND NOT SM1_FFd2 AND NOT PORT1_RD_S)); FTCPE_SM1_FFd3: FTCPE port map (SM1_FFd3,SM1_FFd3_T,CLK,NOT RESET,'0'); SM1_FFd3_T <= ((SM1_FFd2.EXP) OR (NOT SM1_FFd4 AND SM1_FFd2) OR (NOT SM1_FFd3 AND NOT SM1_FFd2 AND SM1_FFd1) OR (PORT0_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT PORT0_WR_S) OR (PORT0_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT PORT0_RD_S) OR (PORT1_MODUS(0) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT PORT1_WR_S)); FTCPE_SM1_FFd4: FTCPE port map (SM1_FFd4,SM1_FFd4_T,CLK,NOT RESET,'0'); SM1_FFd4_T <= ((NOT PORT0_MODUS(0) AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1) OR (SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1) OR (NOT SM1_FFd3 AND SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1) OR (NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1 AND PORT0_WR_S AND PORT0_RD_S)); FDCPE_SM20: FDCPE port map (SM2(0),SM2_D(0),CLK,NOT RESET,'0'); SM2_D(0) <= ((PORT1_WR_S AND PORT1_RD_S) OR (NOT SM2(0) AND PORT0_WR_S AND PORT0_RD_S)); Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC95144XL-10-TQ100 -------------------------------------------------- /100 98 96 94 92 90 88 86 84 82 80 78 76 \ | 99 97 95 93 91 89 87 85 83 81 79 77 | | 1 75 | | 2 74 | | 3 73 | | 4 72 | | 5 71 | | 6 70 | | 7 69 | | 8 68 | | 9 67 | | 10 66 | | 11 65 | | 12 64 | | 13 XC95144XL-10-TQ100 63 | | 14 62 | | 15 61 | | 16 60 | | 17 59 | | 18 58 | | 19 57 | | 20 56 | | 21 55 | | 22 54 | | 23 53 | | 24 52 | | 25 51 | | 27 29 31 33 35 37 39 41 43 45 47 49 | \26 28 30 32 34 36 38 40 42 44 46 48 50 / -------------------------------------------------- Pin Signal Pin Signal No. Name No. Name 1 RAM_DI<6> 51 VCC 2 KPR 52 PORT1_A<1> 3 PORT0_DI<2> 53 RAM_RD 4 PORT0_DI<0> 54 PORT1_RD 5 VCC 55 PORT0_DO<3> 6 RAM_A<0> 56 KPR 7 RAM_DI<1> 57 VCC 8 PORT0_DI<1> 58 PORT0_DO<6> 9 RAM_DO<0> 59 RAM_DI<0> 10 RAM_DO<1> 60 KPR 11 RAM_A<2> 61 RAM_A<3> 12 PORT1_A<2> 62 GND 13 KPR 63 RAM_DO<7> 14 RAM_A<1> 64 PORT0_DI<3> 15 KPR 65 RAM_DI<7> 16 PORT1_DI<2> 66 PORT0_DO<1> 17 RAM_E 67 PORT1_DI<0> 18 PORT1_DI<1> 68 PORT0_DO<4> 19 RAM_DI<4> 69 GND 20 PORT1_E 70 RAM_DI<3> 21 GND 71 PORT1_DI<5> 22 CLK 72 PORT0_DO<5> 23 PORT0_DI<6> 73 PORT0_WR 24 RAM_DO<6> 74 RAM_DO<2> 25 PORT1_A<3> 75 GND 26 VCC 76 KPR 27 PORT1_DI<3> 77 PORT1_A<0> 28 RAM_WR 78 RAM_DO<3> 29 PORT0_DI<5> 79 KPR 30 PORT1_DI<4> 80 PORT0_RD 31 GND 81 RAM_DO<4> 32 PORT0_E 82 KPR 33 RAM_DI<5> 83 TDO 34 PORT0_DO<0> 84 GND 35 PORT0_DO<2> 85 PORT1_DI<6> 36 RAM_DI<2> 86 RAM_DO<5> 37 PORT0_DO<7> 87 PORT1_DO<0> 38 VCC 88 VCC 39 KPR 89 PORT0_DI<4> 40 PORT1_DO<2> 90 PORT1_DO<1> 41 PORT1_DI<7> 91 PORT0_A<2> 42 PORT1_DO<3> 92 PORT1_DO<4> 43 PORT1_WR 93 PORT0_A<0> 44 GND 94 PORT1_DO<5> 45 TDI 95 PORT0_A<3> 46 PORT1_DO<7> 96 PORT1_DO<6> 47 TMS 97 PORT0_DI<7> 48 TCK 98 VCC 49 KPR 99 RESET 50 PORT0_A<1> 100 GND Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal KPR = Unused I/O with weak keeper (leave unconnected) VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc95144xl-10-TQ100 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Ground on Unused IOs : OFF Set I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 54 Pterm Limit : 25