Timing Report

Need help reading this report?

Design Name CONTROLLER
Device, Speed (SpeedFile Version) XC95144XL, -10 (3.0)
Date Created Wed Feb 15 19:13:16 2006
Created By Timing Report Generator: version I.26
Copyright Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.

Performance Summary
Min. Clock Period 11.000 ns.
Max. Clock Frequency (fSYSTEM) 90.909 MHz.
Limited by Cycle Time for CLK
Clock to Setup (tCYC) 11.000 ns.
Setup to Clock at the Pad (tSU) 7.500 ns.
Clock Pad to Output Pad Delay (tCO) 5.800 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
AUTO_TS_F2F 0.0 11.0 312 312
AUTO_TS_P2P 0.0 5.8 33 33
AUTO_TS_P2F 0.0 9.3 45 45
AUTO_TS_F2P 0.0 4.0 33 33


Constraint: TS1000

Description: PERIOD:PERIOD_CLK:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
PORT0_MODUS<0>.Q to RAM_A<0>.D 0.000 11.000 -11.000
PORT0_MODUS<0>.Q to RAM_A<1>.D 0.000 11.000 -11.000
PORT0_MODUS<0>.Q to RAM_A<2>.D 0.000 11.000 -11.000


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
CLK to PORT0_DO<0> 0.000 5.800 -5.800
CLK to PORT0_DO<1> 0.000 5.800 -5.800
CLK to PORT0_DO<2> 0.000 5.800 -5.800


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
PORT0_A<0> to RAM_A<0>.D 0.000 9.300 -9.300
PORT0_A<1> to RAM_A<1>.D 0.000 9.300 -9.300
PORT0_A<2> to RAM_A<2>.D 0.000 9.300 -9.300


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
PORT0_DO<0>.Q to PORT0_DO<0> 0.000 4.000 -4.000
PORT0_DO<1>.Q to PORT0_DO<1> 0.000 4.000 -4.000
PORT0_DO<2>.Q to PORT0_DO<2> 0.000 4.000 -4.000



Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
CLK 90.909 Limited by Cycle Time for CLK

Setup/Hold Times for Clocks

Setup/Hold Times for Clock CLK
Source Pad Setup to clk (edge) Hold to clk (edge)
PORT0_A<0> 7.500 0.000
PORT0_A<1> 7.500 0.000
PORT0_A<2> 7.500 0.000
PORT0_A<3> 7.500 0.000
PORT0_DI<0> 6.500 0.000
PORT0_DI<1> 6.500 0.000
PORT0_DI<2> 6.500 0.000
PORT0_DI<3> 6.500 0.000
PORT0_DI<4> 6.500 0.000
PORT0_DI<5> 6.500 0.000
PORT0_DI<6> 6.500 0.000
PORT0_DI<7> 6.500 0.000
PORT0_RD 6.500 0.000
PORT0_WR 6.500 0.000
PORT1_A<0> 6.500 0.000
PORT1_A<1> 6.500 0.000
PORT1_A<2> 6.500 0.000
PORT1_A<3> 6.500 0.000
PORT1_DI<0> 6.500 0.000
PORT1_DI<1> 6.500 0.000
PORT1_DI<2> 6.500 0.000
PORT1_DI<3> 6.500 0.000
PORT1_DI<4> 6.500 0.000
PORT1_DI<5> 6.500 0.000
PORT1_DI<6> 6.500 0.000
PORT1_DI<7> 6.500 0.000
PORT1_RD 6.500 0.000
PORT1_WR 6.500 0.000
RAM_DI<0> 6.500 0.000
RAM_DI<1> 6.500 0.000
RAM_DI<2> 6.500 0.000
RAM_DI<3> 6.500 0.000
RAM_DI<4> 6.500 0.000
RAM_DI<5> 6.500 0.000
RAM_DI<6> 6.500 0.000
RAM_DI<7> 6.500 0.000


Clock to Pad Timing

Clock CLK to Pad
Destination Pad Clock (edge) to Pad
PORT0_DO<0> 5.800
PORT0_DO<1> 5.800
PORT0_DO<2> 5.800
PORT0_DO<3> 5.800
PORT0_DO<4> 5.800
PORT0_DO<5> 5.800
PORT0_DO<6> 5.800
PORT0_DO<7> 5.800
PORT0_E 5.800
PORT1_DO<0> 5.800
PORT1_DO<1> 5.800
PORT1_DO<2> 5.800
PORT1_DO<3> 5.800
PORT1_DO<4> 5.800
PORT1_DO<5> 5.800
PORT1_DO<6> 5.800
PORT1_DO<7> 5.800
PORT1_E 5.800
RAM_A<0> 5.800
RAM_A<1> 5.800
RAM_A<2> 5.800
RAM_A<3> 5.800
RAM_DO<0> 5.800
RAM_DO<1> 5.800
RAM_DO<2> 5.800
RAM_DO<3> 5.800
RAM_DO<4> 5.800
RAM_DO<5> 5.800
RAM_DO<6> 5.800
RAM_DO<7> 5.800
RAM_E 5.800
RAM_RD 5.800
RAM_WR 5.800


Clock to Setup Times for Clocks

Clock to Setup for clock CLK
Source Destination Delay
PORT0_MODUS<0>.Q RAM_A<0>.D 11.000
PORT0_MODUS<0>.Q RAM_A<1>.D 11.000
PORT0_MODUS<0>.Q RAM_A<2>.D 11.000
PORT0_MODUS<0>.Q RAM_A<3>.D 11.000
PORT0_RD_S.Q RAM_A<0>.D 11.000
PORT0_RD_S.Q RAM_A<1>.D 11.000
PORT0_RD_S.Q RAM_A<2>.D 11.000
PORT0_RD_S.Q RAM_A<3>.D 11.000
PORT0_WR_S.Q RAM_A<0>.D 11.000
PORT0_WR_S.Q RAM_A<1>.D 11.000
PORT0_WR_S.Q RAM_A<2>.D 11.000
PORT0_WR_S.Q RAM_A<3>.D 11.000
PORT1_MODUS<0>.Q SM1_FFd3.D 11.000
PORT1_RD_S.Q SM1_FFd3.D 11.000
RAM_A<0>.Q RAM_A<0>.D 11.000
RAM_A<1>.Q RAM_A<1>.D 11.000
RAM_A<2>.Q RAM_A<2>.D 11.000
RAM_A<3>.Q RAM_A<3>.D 11.000
SM1_FFd1.Q RAM_A<0>.D 11.000
SM1_FFd1.Q RAM_A<1>.D 11.000
SM1_FFd1.Q RAM_A<2>.D 11.000
SM1_FFd1.Q RAM_A<3>.D 11.000
SM1_FFd2.Q RAM_A<0>.D 11.000
SM1_FFd2.Q RAM_A<1>.D 11.000
SM1_FFd2.Q RAM_A<2>.D 11.000
SM1_FFd2.Q RAM_A<3>.D 11.000
SM1_FFd3.Q RAM_A<0>.D 11.000
SM1_FFd3.Q RAM_A<1>.D 11.000
SM1_FFd3.Q RAM_A<2>.D 11.000
SM1_FFd3.Q RAM_A<3>.D 11.000
SM1_FFd3.Q SM1_FFd3.D 11.000
SM1_FFd4.Q RAM_A<0>.D 11.000
SM1_FFd4.Q RAM_A<1>.D 11.000
SM1_FFd4.Q RAM_A<2>.D 11.000
SM1_FFd4.Q RAM_A<3>.D 11.000
SM1_FFd4.Q SM1_FFd3.D 11.000
PORT0_DO<0>.Q PORT0_DO<0>.D 10.000
PORT0_DO<1>.Q PORT0_DO<1>.D 10.000
PORT0_DO<2>.Q PORT0_DO<2>.D 10.000
PORT0_DO<3>.Q PORT0_DO<3>.D 10.000
PORT0_DO<4>.Q PORT0_DO<4>.D 10.000
PORT0_DO<5>.Q PORT0_DO<5>.D 10.000
PORT0_DO<6>.Q PORT0_DO<6>.D 10.000
PORT0_DO<7>.Q PORT0_DO<7>.D 10.000
PORT0_E.Q PORT0_E.D 10.000
PORT0_MODUS<0>.Q PORT0_DO<0>.D 10.000
PORT0_MODUS<0>.Q PORT0_DO<1>.D 10.000
PORT0_MODUS<0>.Q PORT0_DO<2>.D 10.000
PORT0_MODUS<0>.Q PORT0_DO<3>.D 10.000
PORT0_MODUS<0>.Q PORT0_DO<4>.D 10.000
PORT0_MODUS<0>.Q PORT0_DO<5>.D 10.000
PORT0_MODUS<0>.Q PORT0_DO<6>.D 10.000
PORT0_MODUS<0>.Q PORT0_DO<7>.D 10.000
PORT0_MODUS<0>.Q PORT0_E.D 10.000
PORT0_MODUS<0>.Q PORT0_MODUS<0>.D 10.000
PORT0_MODUS<0>.Q RAM_DO<0>.D 10.000
PORT0_MODUS<0>.Q RAM_DO<1>.D 10.000
PORT0_MODUS<0>.Q RAM_DO<2>.D 10.000
PORT0_MODUS<0>.Q RAM_DO<3>.D 10.000
PORT0_MODUS<0>.Q RAM_DO<4>.D 10.000
PORT0_MODUS<0>.Q RAM_DO<5>.D 10.000
PORT0_MODUS<0>.Q RAM_DO<6>.D 10.000
PORT0_MODUS<0>.Q RAM_DO<7>.D 10.000
PORT0_MODUS<0>.Q RAM_E.D 10.000
PORT0_MODUS<0>.Q SM1_FFd3.D 10.000
PORT0_MODUS<0>.Q SM1_FFd4.D 10.000
PORT0_RD_S.Q PORT0_DO<0>.D 10.000
PORT0_RD_S.Q PORT0_DO<1>.D 10.000
PORT0_RD_S.Q PORT0_DO<2>.D 10.000
PORT0_RD_S.Q PORT0_DO<3>.D 10.000
PORT0_RD_S.Q PORT0_DO<4>.D 10.000
PORT0_RD_S.Q PORT0_DO<5>.D 10.000
PORT0_RD_S.Q PORT0_DO<6>.D 10.000
PORT0_RD_S.Q PORT0_DO<7>.D 10.000
PORT0_RD_S.Q PORT0_E.D 10.000
PORT0_RD_S.Q PORT0_MODUS<0>.D 10.000
PORT0_RD_S.Q RAM_RD.D 10.000
PORT0_RD_S.Q SM1_FFd3.D 10.000
PORT0_RD_S.Q SM1_FFd4.D 10.000
PORT0_RD_S.Q SM2<0>.D 10.000
PORT0_WR_S.Q PORT0_MODUS<0>.D 10.000
PORT0_WR_S.Q RAM_DO<0>.D 10.000
PORT0_WR_S.Q RAM_DO<1>.D 10.000
PORT0_WR_S.Q RAM_DO<2>.D 10.000
PORT0_WR_S.Q RAM_DO<3>.D 10.000
PORT0_WR_S.Q RAM_DO<4>.D 10.000
PORT0_WR_S.Q RAM_DO<5>.D 10.000
PORT0_WR_S.Q RAM_DO<6>.D 10.000
PORT0_WR_S.Q RAM_DO<7>.D 10.000
PORT0_WR_S.Q RAM_E.D 10.000
PORT0_WR_S.Q RAM_WR.D 10.000
PORT0_WR_S.Q SM1_FFd3.D 10.000
PORT0_WR_S.Q SM1_FFd4.D 10.000
PORT0_WR_S.Q SM2<0>.D 10.000
PORT1_MODUS<0>.Q PORT1_DO<0>.CE 10.000
PORT1_MODUS<0>.Q PORT1_DO<1>.CE 10.000
PORT1_MODUS<0>.Q PORT1_DO<2>.CE 10.000
PORT1_MODUS<0>.Q PORT1_DO<3>.CE 10.000
PORT1_MODUS<0>.Q PORT1_DO<4>.CE 10.000
PORT1_MODUS<0>.Q PORT1_DO<5>.CE 10.000
PORT1_MODUS<0>.Q PORT1_DO<6>.CE 10.000
PORT1_MODUS<0>.Q PORT1_DO<7>.CE 10.000
PORT1_MODUS<0>.Q PORT1_E.CE 10.000
PORT1_MODUS<0>.Q PORT1_MODUS<0>.D 10.000
PORT1_MODUS<0>.Q RAM_A<0>.D 10.000
PORT1_MODUS<0>.Q RAM_A<1>.D 10.000
PORT1_MODUS<0>.Q RAM_A<2>.D 10.000
PORT1_MODUS<0>.Q RAM_A<3>.D 10.000
PORT1_MODUS<0>.Q RAM_DO<0>.D 10.000
PORT1_MODUS<0>.Q RAM_DO<1>.D 10.000
PORT1_MODUS<0>.Q RAM_DO<2>.D 10.000
PORT1_MODUS<0>.Q RAM_DO<3>.D 10.000
PORT1_MODUS<0>.Q RAM_DO<4>.D 10.000
PORT1_MODUS<0>.Q RAM_DO<5>.D 10.000
PORT1_MODUS<0>.Q RAM_DO<6>.D 10.000
PORT1_MODUS<0>.Q RAM_DO<7>.D 10.000
PORT1_MODUS<0>.Q RAM_E.D 10.000
PORT1_MODUS<0>.Q SM1_FFd2.D 10.000
PORT1_RD_S.Q PORT1_DO<0>.CE 10.000
PORT1_RD_S.Q PORT1_DO<1>.CE 10.000
PORT1_RD_S.Q PORT1_DO<2>.CE 10.000
PORT1_RD_S.Q PORT1_DO<3>.CE 10.000
PORT1_RD_S.Q PORT1_DO<4>.CE 10.000
PORT1_RD_S.Q PORT1_DO<5>.CE 10.000
PORT1_RD_S.Q PORT1_DO<6>.CE 10.000
PORT1_RD_S.Q PORT1_DO<7>.CE 10.000
PORT1_RD_S.Q PORT1_E.CE 10.000
PORT1_RD_S.Q PORT1_MODUS<0>.D 10.000
PORT1_RD_S.Q RAM_A<0>.D 10.000
PORT1_RD_S.Q RAM_A<1>.D 10.000
PORT1_RD_S.Q RAM_A<2>.D 10.000
PORT1_RD_S.Q RAM_A<3>.D 10.000
PORT1_RD_S.Q RAM_RD.D 10.000
PORT1_RD_S.Q SM1_FFd2.D 10.000
PORT1_RD_S.Q SM2<0>.D 10.000
PORT1_WR_S.Q PORT1_MODUS<0>.D 10.000
PORT1_WR_S.Q RAM_A<0>.D 10.000
PORT1_WR_S.Q RAM_A<1>.D 10.000
PORT1_WR_S.Q RAM_A<2>.D 10.000
PORT1_WR_S.Q RAM_A<3>.D 10.000
PORT1_WR_S.Q RAM_DO<0>.D 10.000
PORT1_WR_S.Q RAM_DO<1>.D 10.000
PORT1_WR_S.Q RAM_DO<2>.D 10.000
PORT1_WR_S.Q RAM_DO<3>.D 10.000
PORT1_WR_S.Q RAM_DO<4>.D 10.000
PORT1_WR_S.Q RAM_DO<5>.D 10.000
PORT1_WR_S.Q RAM_DO<6>.D 10.000
PORT1_WR_S.Q RAM_DO<7>.D 10.000
PORT1_WR_S.Q RAM_E.D 10.000
PORT1_WR_S.Q RAM_WR.D 10.000
PORT1_WR_S.Q SM1_FFd2.D 10.000
PORT1_WR_S.Q SM1_FFd3.D 10.000
PORT1_WR_S.Q SM2<0>.D 10.000
RAM_DO<0>.Q RAM_DO<0>.D 10.000
RAM_DO<1>.Q RAM_DO<1>.D 10.000
RAM_DO<2>.Q RAM_DO<2>.D 10.000
RAM_DO<3>.Q RAM_DO<3>.D 10.000
RAM_DO<4>.Q RAM_DO<4>.D 10.000
RAM_DO<5>.Q RAM_DO<5>.D 10.000
RAM_DO<6>.Q RAM_DO<6>.D 10.000
RAM_DO<7>.Q RAM_DO<7>.D 10.000
RAM_E.Q RAM_E.D 10.000
RAM_RD.Q RAM_RD.D 10.000
RAM_WR.Q RAM_WR.D 10.000
SM1_FFd1.Q PORT0_DO<0>.D 10.000
SM1_FFd1.Q PORT0_DO<1>.D 10.000
SM1_FFd1.Q PORT0_DO<2>.D 10.000
SM1_FFd1.Q PORT0_DO<3>.D 10.000
SM1_FFd1.Q PORT0_DO<4>.D 10.000
SM1_FFd1.Q PORT0_DO<5>.D 10.000
SM1_FFd1.Q PORT0_DO<6>.D 10.000
SM1_FFd1.Q PORT0_DO<7>.D 10.000
SM1_FFd1.Q PORT0_E.D 10.000
SM1_FFd1.Q PORT0_MODUS<0>.D 10.000
SM1_FFd1.Q PORT1_DO<0>.CE 10.000
SM1_FFd1.Q PORT1_DO<1>.CE 10.000
SM1_FFd1.Q PORT1_DO<2>.CE 10.000
SM1_FFd1.Q PORT1_DO<3>.CE 10.000
SM1_FFd1.Q PORT1_DO<4>.CE 10.000
SM1_FFd1.Q PORT1_DO<5>.CE 10.000
SM1_FFd1.Q PORT1_DO<6>.CE 10.000
SM1_FFd1.Q PORT1_DO<7>.CE 10.000
SM1_FFd1.Q PORT1_E.CE 10.000
SM1_FFd1.Q PORT1_MODUS<0>.D 10.000
SM1_FFd1.Q RAM_DO<0>.D 10.000
SM1_FFd1.Q RAM_DO<1>.D 10.000
SM1_FFd1.Q RAM_DO<2>.D 10.000
SM1_FFd1.Q RAM_DO<3>.D 10.000
SM1_FFd1.Q RAM_DO<4>.D 10.000
SM1_FFd1.Q RAM_DO<5>.D 10.000
SM1_FFd1.Q RAM_DO<6>.D 10.000
SM1_FFd1.Q RAM_DO<7>.D 10.000
SM1_FFd1.Q RAM_E.D 10.000
SM1_FFd1.Q RAM_RD.D 10.000
SM1_FFd1.Q RAM_WR.D 10.000
SM1_FFd1.Q SM1_FFd1.D 10.000
SM1_FFd1.Q SM1_FFd3.D 10.000
SM1_FFd1.Q SM1_FFd4.D 10.000
SM1_FFd2.Q PORT0_DO<0>.D 10.000
SM1_FFd2.Q PORT0_DO<1>.D 10.000
SM1_FFd2.Q PORT0_DO<2>.D 10.000
SM1_FFd2.Q PORT0_DO<3>.D 10.000
SM1_FFd2.Q PORT0_DO<4>.D 10.000
SM1_FFd2.Q PORT0_DO<5>.D 10.000
SM1_FFd2.Q PORT0_DO<6>.D 10.000
SM1_FFd2.Q PORT0_DO<7>.D 10.000
SM1_FFd2.Q PORT0_E.D 10.000
SM1_FFd2.Q PORT0_MODUS<0>.D 10.000
SM1_FFd2.Q PORT1_DO<0>.CE 10.000
SM1_FFd2.Q PORT1_DO<1>.CE 10.000
SM1_FFd2.Q PORT1_DO<2>.CE 10.000
SM1_FFd2.Q PORT1_DO<3>.CE 10.000
SM1_FFd2.Q PORT1_DO<4>.CE 10.000
SM1_FFd2.Q PORT1_DO<5>.CE 10.000
SM1_FFd2.Q PORT1_DO<6>.CE 10.000
SM1_FFd2.Q PORT1_DO<7>.CE 10.000
SM1_FFd2.Q PORT1_E.CE 10.000
SM1_FFd2.Q PORT1_MODUS<0>.D 10.000
SM1_FFd2.Q RAM_DO<0>.D 10.000
SM1_FFd2.Q RAM_DO<1>.D 10.000
SM1_FFd2.Q RAM_DO<2>.D 10.000
SM1_FFd2.Q RAM_DO<3>.D 10.000
SM1_FFd2.Q RAM_DO<4>.D 10.000
SM1_FFd2.Q RAM_DO<5>.D 10.000
SM1_FFd2.Q RAM_DO<6>.D 10.000
SM1_FFd2.Q RAM_DO<7>.D 10.000
SM1_FFd2.Q RAM_E.D 10.000
SM1_FFd2.Q RAM_RD.D 10.000
SM1_FFd2.Q RAM_WR.D 10.000
SM1_FFd2.Q SM1_FFd1.D 10.000
SM1_FFd2.Q SM1_FFd2.D 10.000
SM1_FFd2.Q SM1_FFd3.D 10.000
SM1_FFd2.Q SM1_FFd4.D 10.000
SM1_FFd3.Q PORT0_DO<0>.D 10.000
SM1_FFd3.Q PORT0_DO<1>.D 10.000
SM1_FFd3.Q PORT0_DO<2>.D 10.000
SM1_FFd3.Q PORT0_DO<3>.D 10.000
SM1_FFd3.Q PORT0_DO<4>.D 10.000
SM1_FFd3.Q PORT0_DO<5>.D 10.000
SM1_FFd3.Q PORT0_DO<6>.D 10.000
SM1_FFd3.Q PORT0_DO<7>.D 10.000
SM1_FFd3.Q PORT0_E.D 10.000
SM1_FFd3.Q PORT0_MODUS<0>.D 10.000
SM1_FFd3.Q PORT1_DO<0>.CE 10.000
SM1_FFd3.Q PORT1_DO<1>.CE 10.000
SM1_FFd3.Q PORT1_DO<2>.CE 10.000
SM1_FFd3.Q PORT1_DO<3>.CE 10.000
SM1_FFd3.Q PORT1_DO<4>.CE 10.000
SM1_FFd3.Q PORT1_DO<5>.CE 10.000
SM1_FFd3.Q PORT1_DO<6>.CE 10.000
SM1_FFd3.Q PORT1_DO<7>.CE 10.000
SM1_FFd3.Q PORT1_E.CE 10.000
SM1_FFd3.Q PORT1_MODUS<0>.D 10.000
SM1_FFd3.Q RAM_DO<0>.D 10.000
SM1_FFd3.Q RAM_DO<1>.D 10.000
SM1_FFd3.Q RAM_DO<2>.D 10.000
SM1_FFd3.Q RAM_DO<3>.D 10.000
SM1_FFd3.Q RAM_DO<4>.D 10.000
SM1_FFd3.Q RAM_DO<5>.D 10.000
SM1_FFd3.Q RAM_DO<6>.D 10.000
SM1_FFd3.Q RAM_DO<7>.D 10.000
SM1_FFd3.Q RAM_E.D 10.000
SM1_FFd3.Q RAM_RD.D 10.000
SM1_FFd3.Q RAM_WR.D 10.000
SM1_FFd3.Q SM1_FFd1.D 10.000
SM1_FFd3.Q SM1_FFd2.D 10.000
SM1_FFd3.Q SM1_FFd4.D 10.000
SM1_FFd4.Q PORT0_DO<0>.D 10.000
SM1_FFd4.Q PORT0_DO<1>.D 10.000
SM1_FFd4.Q PORT0_DO<2>.D 10.000
SM1_FFd4.Q PORT0_DO<3>.D 10.000
SM1_FFd4.Q PORT0_DO<4>.D 10.000
SM1_FFd4.Q PORT0_DO<5>.D 10.000
SM1_FFd4.Q PORT0_DO<6>.D 10.000
SM1_FFd4.Q PORT0_DO<7>.D 10.000
SM1_FFd4.Q PORT0_E.D 10.000
SM1_FFd4.Q PORT0_MODUS<0>.D 10.000
SM1_FFd4.Q PORT1_DO<0>.CE 10.000
SM1_FFd4.Q PORT1_DO<1>.CE 10.000
SM1_FFd4.Q PORT1_DO<2>.CE 10.000
SM1_FFd4.Q PORT1_DO<3>.CE 10.000
SM1_FFd4.Q PORT1_DO<4>.CE 10.000
SM1_FFd4.Q PORT1_DO<5>.CE 10.000
SM1_FFd4.Q PORT1_DO<6>.CE 10.000
SM1_FFd4.Q PORT1_DO<7>.CE 10.000
SM1_FFd4.Q PORT1_E.CE 10.000
SM1_FFd4.Q PORT1_MODUS<0>.D 10.000
SM1_FFd4.Q RAM_DO<0>.D 10.000
SM1_FFd4.Q RAM_DO<1>.D 10.000
SM1_FFd4.Q RAM_DO<2>.D 10.000
SM1_FFd4.Q RAM_DO<3>.D 10.000
SM1_FFd4.Q RAM_DO<4>.D 10.000
SM1_FFd4.Q RAM_DO<5>.D 10.000
SM1_FFd4.Q RAM_DO<6>.D 10.000
SM1_FFd4.Q RAM_DO<7>.D 10.000
SM1_FFd4.Q RAM_E.D 10.000
SM1_FFd4.Q RAM_RD.D 10.000
SM1_FFd4.Q RAM_WR.D 10.000
SM1_FFd4.Q SM1_FFd1.D 10.000
SM1_FFd4.Q SM1_FFd2.D 10.000
SM1_FFd4.Q SM1_FFd4.D 10.000
SM2<0>.Q PORT0_DO<0>.D 10.000
SM2<0>.Q PORT0_DO<1>.D 10.000
SM2<0>.Q PORT0_DO<2>.D 10.000
SM2<0>.Q PORT0_DO<3>.D 10.000
SM2<0>.Q PORT0_DO<4>.D 10.000
SM2<0>.Q PORT0_DO<5>.D 10.000
SM2<0>.Q PORT0_DO<6>.D 10.000
SM2<0>.Q PORT0_DO<7>.D 10.000
SM2<0>.Q PORT0_E.D 10.000
SM2<0>.Q PORT0_MODUS<0>.D 10.000
SM2<0>.Q SM2<0>.D 10.000


Pad to Pad List

Source Pad Destination Pad Delay



Number of paths analyzed: 423
Number of Timing errors: 423
Analysis Completed: Wed Feb 15 19:13:16 2006