Signal Name | Total Pterms | Total Inputs | Function Block | Macrocell | Power Mode | Slew Rate | Pin Number | Pin Type | Pin Use | Reg Init State | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RAM_A<0> | 8 | 13 | FB2 | MC11 | STD | FAST | 6 | I/O | O | RESET | |||
RAM_DO<0> | 5 | 11 | FB2 | MC15 | STD | FAST | 9 | I/O | O | RESET | |||
RAM_DO<1> | 5 | 11 | FB2 | MC17 | STD | FAST | 10 | I/O | O | RESET | |||
RAM_A<2> | 8 | 13 | FB1 | MC2 | STD | FAST | 11 | I/O | O | RESET | |||
RAM_A<1> | 8 | 13 | FB1 | MC6 | STD | FAST | 14 | I/O | O | RESET | |||
RAM_E | 5 | 9 | FB1 | MC11 | STD | FAST | 17 | I/O | O | RESET | |||
SM1_FFd1 | 2 | 4 | FB1 | MC12 | STD | 18 | I/O | I | RESET | ||||
PORT0_MODUS<0> | 3 | 8 | FB1 | MC14 | STD | 19 | I/O | I | RESET | ||||
PORT1_E | 1 | 6 | FB1 | MC15 | STD | FAST | 20 | I/O | O | RESET | |||
SM1_FFd2 | 4 | 6 | FB1 | MC17 | STD | 22 | I/O/GCK1 | GCK | RESET | ||||
RAM_DO<6> | 5 | 11 | FB3 | MC5 | STD | FAST | 24 | I/O | O | RESET | |||
RAM_WR | 5 | 7 | FB3 | MC9 | STD | FAST | 28 | I/O | O | SET | |||
PORT0_E | 2 | 8 | FB3 | MC14 | STD | FAST | 32 | I/O | O | RESET | |||
PORT0_DO<0> | 3 | 9 | FB3 | MC17 | STD | FAST | 34 | I/O | O | RESET | |||
PORT0_DO<2> | 3 | 9 | FB5 | MC2 | STD | FAST | 35 | I/O | O | RESET | |||
PORT0_DO<7> | 3 | 9 | FB5 | MC6 | STD | FAST | 37 | I/O | O | RESET | |||
PORT1_DO<2> | 2 | 7 | FB5 | MC9 | STD | FAST | 40 | I/O | O | RESET | |||
PORT1_DO<3> | 2 | 7 | FB5 | MC12 | STD | FAST | 42 | I/O | O | RESET | |||
PORT1_DO<7> | 2 | 7 | FB5 | MC15 | STD | FAST | 46 | I/O | O | RESET | |||
PORT1_RD_S | 1 | 1 | FB5 | MC17 | STD | 49 | I/O | (b) | RESET | ||||
RAM_RD | 5 | 7 | FB7 | MC6 | STD | FAST | 53 | I/O | O | SET | |||
PORT0_DO<3> | 3 | 9 | FB7 | MC9 | STD | FAST | 55 | I/O | O | RESET | |||
PORT0_DO<6> | 3 | 9 | FB7 | MC12 | STD | FAST | 58 | I/O | O | RESET | |||
RAM_A<3> | 8 | 13 | FB7 | MC17 | STD | FAST | 61 | I/O | O | RESET | |||
RAM_DO<7> | 5 | 11 | FB8 | MC2 | STD | FAST | 63 | I/O | O | RESET | |||
PORT0_DO<1> | 3 | 9 | FB8 | MC8 | STD | FAST | 66 | I/O | O | RESET | |||
PORT0_DO<4> | 3 | 9 | FB8 | MC11 | STD | FAST | 68 | I/O | O | RESET | |||
PORT0_DO<5> | 3 | 9 | FB8 | MC15 | STD | FAST | 72 | I/O | O | RESET | |||
RAM_DO<2> | 5 | 11 | FB6 | MC2 | STD | FAST | 74 | I/O | O | RESET | |||
RAM_DO<3> | 5 | 11 | FB6 | MC8 | STD | FAST | 78 | I/O | O | RESET | |||
RAM_DO<4> | 5 | 11 | FB6 | MC12 | STD | FAST | 81 | I/O | O | RESET | |||
RAM_DO<5> | 5 | 11 | FB6 | MC17 | STD | FAST | 86 | I/O | O | RESET | |||
PORT1_DO<0> | 2 | 7 | FB4 | MC2 | STD | FAST | 87 | I/O | O | RESET | |||
PORT1_DO<1> | 2 | 7 | FB4 | MC6 | STD | FAST | 90 | I/O | O | RESET | |||
PORT1_DO<4> | 2 | 7 | FB4 | MC9 | STD | FAST | 92 | I/O | O | RESET | |||
PORT1_DO<5> | 2 | 7 | FB4 | MC12 | STD | FAST | 94 | I/O | O | RESET | |||
PORT1_DO<6> | 2 | 7 | FB4 | MC15 | STD | FAST | 96 | I/O | O | RESET | |||
SM2<0> | 2 | 5 | FB1 | MC10 | STD | (b) | (b) | D | RESET | ||||
PORT1_MODUS<0> | 3 | 7 | FB1 | MC13 | STD | (b) | (b) | T | RESET | ||||
SM1_FFd4 | 4 | 7 | FB1 | MC16 | STD | (b) | (b) | T | RESET | ||||
SM1_FFd3 | 6 | 10 | FB1 | MC18 | STD | (b) | (b) | T | RESET | ||||
PORT0_RD_S | 1 | 1 | FB3 | MC18 | STD | (b) | (b) | D | RESET | ||||
PORT1_WR_S | 1 | 1 | FB5 | MC16 | STD | (b) | (b) | D | RESET | ||||
PORT0_WR_S | 1 | 1 | FB5 | MC18 | STD | (b) | (b) | D | RESET |