********** Mapped Logic ********** |
FTCPE_PORT0_DO0: FTCPE port map (PORT0_DO(0),PORT0_DO_T(0),CLK,NOT RESET,'0');
PORT0_DO_T(0) <= ((PORT0_DO(0) AND SM2(0)) OR (NOT PORT0_MODUS(0) AND PORT0_DO(0) AND NOT RAM_DI(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_RD_S) OR (NOT PORT0_MODUS(0) AND NOT PORT0_DO(0) AND RAM_DI(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND SM1_FFd2 AND NOT SM1_FFd1 AND NOT SM2(0) AND NOT PORT0_RD_S)); |
FTCPE_PORT0_DO1: FTCPE port map (PORT0_DO(1),PORT0_DO_T(1),CLK,NOT RESET,'0');
PORT0_DO_T(1) <= ((PORT0_DO(1) AND SM2(0)) OR (NOT PORT0_MODUS(0) AND PORT0_DO(1) AND NOT RAM_DI(1) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_RD_S) OR (NOT PORT0_MODUS(0) AND NOT PORT0_DO(1) AND RAM_DI(1) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND SM1_FFd2 AND NOT SM1_FFd1 AND NOT SM2(0) AND NOT PORT0_RD_S)); |
FTCPE_PORT0_DO2: FTCPE port map (PORT0_DO(2),PORT0_DO_T(2),CLK,NOT RESET,'0');
PORT0_DO_T(2) <= ((PORT0_DO(2) AND SM2(0)) OR (NOT PORT0_MODUS(0) AND PORT0_DO(2) AND NOT RAM_DI(2) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_RD_S) OR (NOT PORT0_MODUS(0) AND NOT PORT0_DO(2) AND RAM_DI(2) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND SM1_FFd2 AND NOT SM1_FFd1 AND NOT SM2(0) AND NOT PORT0_RD_S)); |
FTCPE_PORT0_DO3: FTCPE port map (PORT0_DO(3),PORT0_DO_T(3),CLK,NOT RESET,'0');
PORT0_DO_T(3) <= ((PORT0_DO(3) AND SM2(0)) OR (NOT PORT0_MODUS(0) AND PORT0_DO(3) AND NOT RAM_DI(3) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_RD_S) OR (NOT PORT0_MODUS(0) AND NOT PORT0_DO(3) AND RAM_DI(3) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND SM1_FFd2 AND NOT SM1_FFd1 AND NOT SM2(0) AND NOT PORT0_RD_S)); |
FTCPE_PORT0_DO4: FTCPE port map (PORT0_DO(4),PORT0_DO_T(4),CLK,NOT RESET,'0');
PORT0_DO_T(4) <= ((PORT0_DO(4) AND SM2(0)) OR (NOT PORT0_MODUS(0) AND PORT0_DO(4) AND NOT RAM_DI(4) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_RD_S) OR (NOT PORT0_MODUS(0) AND NOT PORT0_DO(4) AND RAM_DI(4) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND SM1_FFd2 AND NOT SM1_FFd1 AND NOT SM2(0) AND NOT PORT0_RD_S)); |
FTCPE_PORT0_DO5: FTCPE port map (PORT0_DO(5),PORT0_DO_T(5),CLK,NOT RESET,'0');
PORT0_DO_T(5) <= ((PORT0_DO(5) AND SM2(0)) OR (NOT PORT0_MODUS(0) AND PORT0_DO(5) AND NOT RAM_DI(5) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_RD_S) OR (NOT PORT0_MODUS(0) AND NOT PORT0_DO(5) AND RAM_DI(5) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND SM1_FFd2 AND NOT SM1_FFd1 AND NOT SM2(0) AND NOT PORT0_RD_S)); |
FTCPE_PORT0_DO6: FTCPE port map (PORT0_DO(6),PORT0_DO_T(6),CLK,NOT RESET,'0');
PORT0_DO_T(6) <= ((PORT0_DO(6) AND SM2(0)) OR (NOT PORT0_MODUS(0) AND PORT0_DO(6) AND NOT RAM_DI(6) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_RD_S) OR (NOT PORT0_MODUS(0) AND NOT PORT0_DO(6) AND RAM_DI(6) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND SM1_FFd2 AND NOT SM1_FFd1 AND NOT SM2(0) AND NOT PORT0_RD_S)); |
FTCPE_PORT0_DO7: FTCPE port map (PORT0_DO(7),PORT0_DO_T(7),CLK,NOT RESET,'0');
PORT0_DO_T(7) <= ((PORT0_DO(7) AND SM2(0)) OR (NOT PORT0_MODUS(0) AND PORT0_DO(7) AND NOT RAM_DI(7) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_RD_S) OR (NOT PORT0_MODUS(0) AND NOT PORT0_DO(7) AND RAM_DI(7) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND SM1_FFd2 AND NOT SM1_FFd1 AND NOT SM2(0) AND NOT PORT0_RD_S)); |
FDCPE_PORT0_E: FDCPE port map (PORT0_E,PORT0_E_D,CLK,NOT RESET,'0');
PORT0_E_D <= ((PORT0_E AND NOT SM2(0)) OR (NOT PORT0_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND SM1_FFd2 AND NOT SM1_FFd1 AND NOT SM2(0) AND NOT PORT0_RD_S)); |
FTCPE_PORT0_MODUS0: FTCPE port map (PORT0_MODUS(0),PORT0_MODUS_T(0),CLK,NOT RESET,'0');
PORT0_MODUS_T(0) <= ((NOT PORT0_MODUS(0) AND NOT SM2(0) AND PORT0_WR_S AND PORT0_RD_S) OR (PORT0_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_WR_S) OR (PORT0_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_RD_S)); |
FDCPE_PORT0_RD_S: FDCPE port map (PORT0_RD_S,PORT0_RD,CLK,'0','0'); |
FDCPE_PORT0_WR_S: FDCPE port map (PORT0_WR_S,PORT0_WR,CLK,'0','0'); |
FDCPE_PORT1_DO0: FDCPE port map (PORT1_DO(0),RAM_DI(0),CLK,NOT RESET,'0',PORT1_DO_CE(0));
PORT1_DO_CE(0) <= (NOT PORT1_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND SM1_FFd1 AND NOT PORT1_RD_S); |
FDCPE_PORT1_DO1: FDCPE port map (PORT1_DO(1),RAM_DI(1),CLK,NOT RESET,'0',PORT1_DO_CE(1));
PORT1_DO_CE(1) <= (NOT PORT1_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND SM1_FFd1 AND NOT PORT1_RD_S); |
FDCPE_PORT1_DO2: FDCPE port map (PORT1_DO(2),RAM_DI(2),CLK,NOT RESET,'0',PORT1_DO_CE(2));
PORT1_DO_CE(2) <= (NOT PORT1_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND SM1_FFd1 AND NOT PORT1_RD_S); |
FDCPE_PORT1_DO3: FDCPE port map (PORT1_DO(3),RAM_DI(3),CLK,NOT RESET,'0',PORT1_DO_CE(3));
PORT1_DO_CE(3) <= (NOT PORT1_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND SM1_FFd1 AND NOT PORT1_RD_S); |
FDCPE_PORT1_DO4: FDCPE port map (PORT1_DO(4),RAM_DI(4),CLK,NOT RESET,'0',PORT1_DO_CE(4));
PORT1_DO_CE(4) <= (NOT PORT1_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND SM1_FFd1 AND NOT PORT1_RD_S); |
FDCPE_PORT1_DO5: FDCPE port map (PORT1_DO(5),RAM_DI(5),CLK,NOT RESET,'0',PORT1_DO_CE(5));
PORT1_DO_CE(5) <= (NOT PORT1_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND SM1_FFd1 AND NOT PORT1_RD_S); |
FDCPE_PORT1_DO6: FDCPE port map (PORT1_DO(6),RAM_DI(6),CLK,NOT RESET,'0',PORT1_DO_CE(6));
PORT1_DO_CE(6) <= (NOT PORT1_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND SM1_FFd1 AND NOT PORT1_RD_S); |
FDCPE_PORT1_DO7: FDCPE port map (PORT1_DO(7),RAM_DI(7),CLK,NOT RESET,'0',PORT1_DO_CE(7));
PORT1_DO_CE(7) <= (NOT PORT1_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND SM1_FFd1 AND NOT PORT1_RD_S); |
FDCPE_PORT1_E: FDCPE port map (PORT1_E,'1',CLK,NOT RESET,'0',PORT1_E_CE);
PORT1_E_CE <= (NOT PORT1_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND SM1_FFd1 AND NOT PORT1_RD_S); |
FTCPE_PORT1_MODUS0: FTCPE port map (PORT1_MODUS(0),PORT1_MODUS_T(0),CLK,NOT RESET,'0');
PORT1_MODUS_T(0) <= ((NOT PORT1_MODUS(0) AND PORT1_WR_S AND PORT1_RD_S) OR (PORT1_MODUS(0) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT1_WR_S) OR (PORT1_MODUS(0) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT1_RD_S)); |
FDCPE_PORT1_RD_S: FDCPE port map (PORT1_RD_S,PORT1_RD,CLK,'0','0'); |
FDCPE_PORT1_WR_S: FDCPE port map (PORT1_WR_S,PORT1_WR,CLK,'0','0'); |
FTCPE_RAM_A0: FTCPE port map (RAM_A(0),RAM_A_T(0),CLK,NOT RESET,'0');
RAM_A_T(0) <= ((EXP14_.EXP) OR (EXP15_.EXP) OR (PORT1_MODUS(0) AND RAM_A(0) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_WR_S AND NOT PORT1_A(0)) OR (PORT1_MODUS(0) AND RAM_A(0) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_RD_S AND NOT PORT1_A(0)) OR (PORT1_MODUS(0) AND NOT RAM_A(0) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_WR_S AND PORT1_A(0)) OR (PORT1_MODUS(0) AND NOT RAM_A(0) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_RD_S AND PORT1_A(0)) OR (PORT0_MODUS(0) AND RAM_A(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_WR_S AND NOT PORT0_A(0))); |
FTCPE_RAM_A1: FTCPE port map (RAM_A(1),RAM_A_T(1),CLK,NOT RESET,'0');
RAM_A_T(1) <= ((EXP12_.EXP) OR (EXP13_.EXP) OR (PORT1_MODUS(0) AND RAM_A(1) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_WR_S AND NOT PORT1_A(1)) OR (PORT1_MODUS(0) AND RAM_A(1) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_RD_S AND NOT PORT1_A(1)) OR (PORT1_MODUS(0) AND NOT RAM_A(1) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_WR_S AND PORT1_A(1)) OR (PORT1_MODUS(0) AND NOT RAM_A(1) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_RD_S AND PORT1_A(1)) OR (PORT0_MODUS(0) AND RAM_A(1) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_WR_S AND NOT PORT0_A(1))); |
FTCPE_RAM_A2: FTCPE port map (RAM_A(2),RAM_A_T(2),CLK,NOT RESET,'0');
RAM_A_T(2) <= ((EXP10_.EXP) OR (EXP11_.EXP) OR (PORT1_MODUS(0) AND RAM_A(2) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_WR_S AND NOT PORT1_A(2)) OR (PORT1_MODUS(0) AND RAM_A(2) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_RD_S AND NOT PORT1_A(2)) OR (PORT1_MODUS(0) AND NOT RAM_A(2) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_WR_S AND PORT1_A(2)) OR (PORT1_MODUS(0) AND NOT RAM_A(2) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_RD_S AND PORT1_A(2)) OR (PORT0_MODUS(0) AND RAM_A(2) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_WR_S AND NOT PORT0_A(2))); |
FTCPE_RAM_A3: FTCPE port map (RAM_A(3),RAM_A_T(3),CLK,NOT RESET,'0');
RAM_A_T(3) <= ((EXP16_.EXP) OR (EXP17_.EXP) OR (PORT1_MODUS(0) AND RAM_A(3) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_WR_S AND NOT PORT1_A(3)) OR (PORT1_MODUS(0) AND RAM_A(3) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_RD_S AND NOT PORT1_A(3)) OR (PORT1_MODUS(0) AND NOT RAM_A(3) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_WR_S AND PORT1_A(3)) OR (PORT1_MODUS(0) AND NOT RAM_A(3) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_RD_S AND PORT1_A(3)) OR (PORT0_MODUS(0) AND RAM_A(3) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_WR_S AND NOT PORT0_A(3))); |
FDCPE_RAM_DO0: FDCPE port map (RAM_DO(0),RAM_DO_D(0),CLK,NOT RESET,'0');
RAM_DO_D(0) <= ((RAM_DO(0) AND SM1_FFd4) OR (RAM_DO(0) AND SM1_FFd2) OR (RAM_DO(0) AND NOT SM1_FFd3 AND SM1_FFd1) OR (PORT1_MODUS(0) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_WR_S AND PORT1_DI(0)) OR (PORT0_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_WR_S AND PORT0_DI(0))); |
FDCPE_RAM_DO1: FDCPE port map (RAM_DO(1),RAM_DO_D(1),CLK,NOT RESET,'0');
RAM_DO_D(1) <= ((RAM_DO(1) AND SM1_FFd4) OR (RAM_DO(1) AND SM1_FFd2) OR (RAM_DO(1) AND NOT SM1_FFd3 AND SM1_FFd1) OR (PORT1_MODUS(0) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_WR_S AND PORT1_DI(1)) OR (PORT0_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_WR_S AND PORT0_DI(1))); |
FDCPE_RAM_DO2: FDCPE port map (RAM_DO(2),RAM_DO_D(2),CLK,NOT RESET,'0');
RAM_DO_D(2) <= ((RAM_DO(2) AND SM1_FFd4) OR (RAM_DO(2) AND SM1_FFd2) OR (RAM_DO(2) AND NOT SM1_FFd3 AND SM1_FFd1) OR (PORT1_MODUS(0) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_WR_S AND PORT1_DI(2)) OR (PORT0_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_WR_S AND PORT0_DI(2))); |
FDCPE_RAM_DO3: FDCPE port map (RAM_DO(3),RAM_DO_D(3),CLK,NOT RESET,'0');
RAM_DO_D(3) <= ((RAM_DO(3) AND SM1_FFd4) OR (RAM_DO(3) AND SM1_FFd2) OR (RAM_DO(3) AND NOT SM1_FFd3 AND SM1_FFd1) OR (PORT1_MODUS(0) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_WR_S AND PORT1_DI(3)) OR (PORT0_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_WR_S AND PORT0_DI(3))); |
FDCPE_RAM_DO4: FDCPE port map (RAM_DO(4),RAM_DO_D(4),CLK,NOT RESET,'0');
RAM_DO_D(4) <= ((RAM_DO(4) AND SM1_FFd4) OR (RAM_DO(4) AND SM1_FFd2) OR (RAM_DO(4) AND NOT SM1_FFd3 AND SM1_FFd1) OR (PORT1_MODUS(0) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_WR_S AND PORT1_DI(4)) OR (PORT0_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_WR_S AND PORT0_DI(4))); |
FDCPE_RAM_DO5: FDCPE port map (RAM_DO(5),RAM_DO_D(5),CLK,NOT RESET,'0');
RAM_DO_D(5) <= ((RAM_DO(5) AND SM1_FFd4) OR (RAM_DO(5) AND SM1_FFd2) OR (RAM_DO(5) AND NOT SM1_FFd3 AND SM1_FFd1) OR (PORT1_MODUS(0) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_WR_S AND PORT1_DI(5)) OR (PORT0_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_WR_S AND PORT0_DI(5))); |
FDCPE_RAM_DO6: FDCPE port map (RAM_DO(6),RAM_DO_D(6),CLK,NOT RESET,'0');
RAM_DO_D(6) <= ((RAM_DO(6) AND SM1_FFd4) OR (RAM_DO(6) AND SM1_FFd2) OR (RAM_DO(6) AND NOT SM1_FFd3 AND SM1_FFd1) OR (PORT1_MODUS(0) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_WR_S AND PORT1_DI(6)) OR (PORT0_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_WR_S AND PORT0_DI(6))); |
FDCPE_RAM_DO7: FDCPE port map (RAM_DO(7),RAM_DO_D(7),CLK,NOT RESET,'0');
RAM_DO_D(7) <= ((RAM_DO(7) AND SM1_FFd4) OR (RAM_DO(7) AND SM1_FFd2) OR (RAM_DO(7) AND NOT SM1_FFd3 AND SM1_FFd1) OR (PORT1_MODUS(0) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_WR_S AND PORT1_DI(7)) OR (PORT0_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_WR_S AND PORT0_DI(7))); |
FDCPE_RAM_E: FDCPE port map (RAM_E,RAM_E_D,CLK,NOT RESET,'0');
RAM_E_D <= ((RAM_E AND SM1_FFd4) OR (RAM_E AND SM1_FFd2) OR (RAM_E AND NOT SM1_FFd3 AND SM1_FFd1) OR (PORT1_MODUS(0) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT PORT1_WR_S) OR (PORT0_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_WR_S)); |
FDCPE_RAM_RD: FDCPE port map (RAM_RD,RAM_RD_D,CLK,'0',NOT RESET);
RAM_RD_D <= ((NOT RAM_RD AND NOT SM1_FFd3 AND NOT SM1_FFd4) OR (NOT RAM_RD AND NOT SM1_FFd4 AND NOT SM1_FFd2) OR (NOT RAM_RD AND SM1_FFd3 AND SM1_FFd4 AND NOT SM1_FFd1) OR (SM1_FFd3 AND NOT SM1_FFd4 AND SM1_FFd2 AND NOT PORT1_RD_S) OR (NOT SM1_FFd3 AND SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_RD_S)); |
FDCPE_RAM_WR: FDCPE port map (RAM_WR,RAM_WR_D,CLK,'0',NOT RESET);
RAM_WR_D <= ((NOT RAM_WR AND NOT SM1_FFd3 AND NOT SM1_FFd4) OR (NOT RAM_WR AND NOT SM1_FFd4 AND NOT SM1_FFd2) OR (NOT RAM_WR AND SM1_FFd3 AND SM1_FFd4 AND NOT SM1_FFd1) OR (SM1_FFd3 AND NOT SM1_FFd4 AND SM1_FFd2 AND NOT PORT1_WR_S) OR (NOT SM1_FFd3 AND SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1 AND NOT PORT0_WR_S)); |
FDCPE_SM1_FFd1: FDCPE port map (SM1_FFd1,SM1_FFd1_D,CLK,NOT RESET,'0');
SM1_FFd1_D <= ((NOT SM1_FFd4 AND SM1_FFd1) OR (SM1_FFd3 AND SM1_FFd4 AND SM1_FFd2)); |
FDCPE_SM1_FFd2: FDCPE port map (SM1_FFd2,SM1_FFd2_D,CLK,NOT RESET,'0');
SM1_FFd2_D <= ((NOT SM1_FFd4 AND SM1_FFd2) OR (SM1_FFd3 AND SM1_FFd4 AND NOT SM1_FFd2) OR (PORT1_MODUS(0) AND SM1_FFd3 AND NOT SM1_FFd2 AND NOT PORT1_WR_S) OR (PORT1_MODUS(0) AND SM1_FFd3 AND NOT SM1_FFd2 AND NOT PORT1_RD_S)); |
FTCPE_SM1_FFd3: FTCPE port map (SM1_FFd3,SM1_FFd3_T,CLK,NOT RESET,'0');
SM1_FFd3_T <= ((SM1_FFd2.EXP) OR (NOT SM1_FFd4 AND SM1_FFd2) OR (NOT SM1_FFd3 AND NOT SM1_FFd2 AND SM1_FFd1) OR (PORT0_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT PORT0_WR_S) OR (PORT0_MODUS(0) AND NOT SM1_FFd3 AND NOT SM1_FFd4 AND NOT PORT0_RD_S) OR (PORT1_MODUS(0) AND SM1_FFd3 AND NOT SM1_FFd4 AND NOT PORT1_WR_S)); |
FTCPE_SM1_FFd4: FTCPE port map (SM1_FFd4,SM1_FFd4_T,CLK,NOT RESET,'0');
SM1_FFd4_T <= ((NOT PORT0_MODUS(0) AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1) OR (SM1_FFd3 AND NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1) OR (NOT SM1_FFd3 AND SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1) OR (NOT SM1_FFd4 AND NOT SM1_FFd2 AND NOT SM1_FFd1 AND PORT0_WR_S AND PORT0_RD_S)); |
FDCPE_SM20: FDCPE port map (SM2(0),SM2_D(0),CLK,NOT RESET,'0');
SM2_D(0) <= ((PORT1_WR_S AND PORT1_RD_S) OR (NOT SM2(0) AND PORT0_WR_S AND PORT0_RD_S)); |
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); |