-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 20:06:02 02/17/06 -- Design Name: -- Module Name: CntAnd7Seg - Behavioral -- Project Name: -- Target Device: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity My7Seg is port ( CLOCK, INPUT0, INPUT1, INPUT2 : in std_ulogic; OUTPUT0, OUTPUT1 : out std_ulogic); --SegOUT : out std_logic_vector (7 downto 0)); end My7Seg; architecture Behavioral of My7Seg is component OR3 is port (O : out STD_ULOGIC; I0 : in STD_ULOGIC; I1 : in STD_ULOGIC; I2 : in STD_ULOGIC); end component OR3; signal uhelp : STD_ULOGIC; begin OR3_INSTANCE_NAME : OR3 port map (uhelp, INPUT0, INPUT1,INPUT2); process begin if uhelp = '1' then OUTPUT1 <= '1'; else OUTPUT1 <= '0'; end if; end process; end Behavioral;