-- main.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library APA;

entity function_test is

  port (clock   : in std_logic;
        clk_out : out std_logic;
        TS      : out std_logic_vector(3 downto 0));

end function_test;


architecture behavior of function_test is

  signal clk      : std_logic;
  signal clk_last : std_logic;
  signal count    : integer range 0 to 40000000;

begin

  process (clock,clk) is 
    variable A : std_logic_vector(3 downto 0);
  begin

    if rising_edge(clock) then

      -- slower clock

      if count = 40000000 then
        count  <= 0;
      else
        count  <= count + 1;
      end if;

      if count = 0 then
        clk <= '0';                 
      elsif count = 20000000 then
        clk <= '1';
      end if;


      -- generate TS / A

      clk_last <= clk;

      if clk_last = '0' and clk = '1' then  -- rising clk edge
        A := A + 1;
        if A = 10 then
          A := (others => '0');
        end if;
      end if;

    end if;

    clk_out <= clk;
    TS      <= A;
 
  end process;

end behavior;