... D : inout STD_LOGIC_VECTOR (7 downto 0); -- Tristate Data-Bus WR : in STD_LOGIC; -- WR Signal RD : in STD_LOGIC; -- RD Signal ... ... signal OUT_EN : bit:='0'; signal OUT_DATA : STD_ULOGIC_VECTOR(7 downto 0) := (others => '0'); signal IN_DATA : STD_ULOGIC_VECTOR(7 downto 0) := (others => '0'); signal CFG_DATA : STD_ULOGIC_VECTOR(7 downto 0) := (others => '0'); signal X_DATA : STD_ULOGIC_VECTOR(11 downto 0) := (others => '0'); signal Y_DATA : STD_ULOGIC_VECTOR(11 downto 0) := (others => '0'); ... ... RD_COUNT: process(RD, RESET, X_DATA, Y_DATA) variable RD_CNT: STD_LOGIC_VECTOR(2 downto 0) := (others => '0'); begin if RESET = '1' then RD_CNT := (others => '0'); elsif RD = '0' and RD'event then if RD_CNT < 4 then RD_CNT := RD_CNT + 1; end if; end if; if RD = '0' then OUT_EN <= '1'; elsif RD = '1' then OUT_EN <= '0'; end if; case RD_CNT is when "001" => OUT_DATA <= X_DATA(7 downto 0); when "010" => OUT_DATA <= ("0000" & X_DATA(11 downto 8)); when "011" => OUT_DATA <= Y_DATA(7 downto 0); when "100" => OUT_DATA <= ("0000" & Y_DATA(11 downto 8)); when others => OUT_DATA <= (others => 'Z'); end case; end process RD_COUNT; WRITE_BUS: process(OUT_EN, OUT_DATA) begin if OUT_EN = '1' then D <= To_StdLogicVector(OUT_DATA); else D <= (others => 'Z'); end if; end process WRITE_BUS; READ_BUS: IN_DATA <= To_StdULogicVector(D); SET_CFG_REG: process(WR) begin if WR = '1' and WR'event and not OUT_EN = '1' then CFG_DATA <= IN_DATA; else null; end if; end process SET_CFG_REG; ...