-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 15:45:13 05/20/06 -- Design Name: -- Module Name: LedTests - Behavioral -- Project Name: -- Target Device: XC9536 -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity LedTests is Port ( CLOCK : in std_logic; DIRECTION : in std_logic; LED_ARRAY : out std_logic_vector(7 downto 0)); end LedTests; architecture Behavioral of LedTests is signal sBufClock : std_logic := '0'; signal sCnt : std_logic_vector (7 downto 0):= "00000000"; signal sFreqCnt : std_logic_vector (2 downto 0) := "000"; signal sClkEn : std_logic := '0'; begin BUFG_inst : BUFG port map ( O => sBufClock, -- Clock buffer output I => CLOCK -- Clock buffer input ); Frequenzteiler: process (sBufClock) begin if rising_edge (sBufClock) then if sFreqCnt = 4 then sFreqCnt <= (others => '0'); sClkEn <= '1'; else sClkEn <= '0'; sFreqCnt <= sFreqCnt + 1; end if; end if; end process; process (sBufClock) begin if rising_edge (sBufClock) then if sClkEn = '1' then if DIRECTION ='1' then sCnt <= sCnt + 1; else sCnt <= sCnt - 1; end if; end if; end if; end process; LED_ARRAY <= sCnt; end Behavioral;