//========================================== `define P_NUM_STATE_BITS 6 `define P_IDLE 0 `define P_SEND1 1 `define P_SEND2 2 `define P_READY 3 `define P_NO_SEND 4 `define P_WAIT 5 //========================================== module producer(clk, start, wdata, write, wrack, full, ready, present_state); input clk; input start; input wrack; input full; output [7:0] wdata; output write; output ready; output [`P_NUM_STATE_BITS-1:0] present_state; wire clk; wire wrack; wire full; reg [7:0] wdata; reg write; reg ready; reg [`P_NUM_STATE_BITS-1:0] present_state; reg [7:0] src [15:0]; reg [7:0] i; integer ii; integer j; initial begin // initialize wdata to be sent for (ii=0; ii<16; ii=ii+1) src[ii] = 3*ii; end always begin @(posedge clk) enter_new_state(`P_IDLE); write <= @(posedge clk) 0; i <= @(posedge clk) 0; if (start == 1) begin while (i < 16) begin //while ($random(j)%3 != 0) // @(posedge clk) enter_new_state(`P_NO_SEND); while (wrack == 1) @(posedge clk) enter_new_state(`P_WAIT); while (wrack == 0) //teeeeeescht begin if (full==0) begin @(posedge clk) enter_new_state(`P_SEND1); wdata <= @(posedge clk) src[i]; write <= @(posedge clk) 1; end end //???? @(posedge clk)#1; @(posedge clk) enter_new_state(`P_SEND2); i <= @(posedge clk) i+1; wdata <= @(posedge clk) 8'bx; write <= @(posedge clk) 0; end while (1) begin @(posedge clk) enter_new_state(`P_READY); ready = 1; end end end task enter_new_state; input [`P_NUM_STATE_BITS-1:0] this_state; begin present_state = this_state; #1; ready = 0; end endtask endmodule // do würds jetzt schwindlig: //========================================== `define C_NUM_STATE_BITS 6 `define C_IDLE 0 `define C_SEND1 1 `define C_SEND2 2 `define C_READY 3 `define C_NO_SEND 4 `define C_WAIT 5 //========================================== module consumer(clk, start, rdata, read, rdack, empty, ready, present_state); input clk; input start; input [7:0] rdata; input rdack; input empty; output read; output ready; output [`P_NUM_STATE_BITS-1:0] present_state; wire clk; wire [7:0] rdata; wire rdack; wire empty; reg read; reg ready; reg [`P_NUM_STATE_BITS-1:0] present_state; reg [7:0] src [15:0]; reg [7:0] i; integer ii; integer j; //initial // begin // initialize wdata to be sent //for (ii=0; ii<16; ii=ii+1) // src[ii] = 3*ii; // end always begin @(posedge clk) enter_new_state(`C_IDLE); read <= @(posedge clk) 0; i <= @(posedge clk) 0; if (start == 1) begin while (i < 16) begin while ($random(j)%3 != 0) @(posedge clk) enter_new_state(`C_NO_SEND); while (rdack == 1) @(posedge clk) enter_new_state(`C_WAIT); while (rdack == 0) //teeeeeescht begin if (empty==1) begin @(posedge clk) enter_new_state(`C_SEND1); src[i] <= @(posedge clk) rdata; read <= @(posedge clk) 1; end end @(posedge clk) enter_new_state(`C_SEND2); i <= @(posedge clk) i+1; //rdata <= @(posedge clk) 8'bx; read <= @(posedge clk) 0; end while (1) begin @(posedge clk) enter_new_state(`C_READY); ready = 1; end end end task enter_new_state; input [`P_NUM_STATE_BITS-1:0] this_state; begin present_state = this_state; #1; ready = 0; end endtask endmodule // ### schwidnlig fertig //========================================== `define C_NUM_STATE_BITS 8 `define C_IDLE 0 `define C_WAIT 1 `define C_RECEIVE 2 `define C_wrack0 3 `define C_wrack1 4 `define C_SEND 5 `define C_rdack1 6 `define C_rdack0 7 module fifo(clk, start, wdata, write, wrack, ready, rdack, rdata, read, full, empty, present_state); input clk; input start; input [7:0] wdata; input write; input read; output wrack; output rdack; output ready; output [7:0] rdata; output present_state; output full; output empty; wire clk; wire [7:0] wdata; wire write; wire read; reg wrack; reg rdack; reg ready; reg [7:0] rdata; reg full, empty; reg [`C_NUM_STATE_BITS-1:0] present_state; reg [7:0] dest [16:0]; reg [7:0] i, r; integer ii; initial begin for (ii=0; ii<16; ii=ii+1) dest[ii] = 0; end always begin @(posedge clk) enter_new_state(`C_IDLE); i <= @(posedge clk) 0; r <= @(posedge clk) 0; rdack <= @(posedge clk) 0; wrack <= @(posedge clk) 0; full <= @(posedge clk) 0; empty <= @(posedge clk) 1; while (1) begin if (write == 1) begin @(posedge clk) enter_new_state(`C_RECEIVE); dest[i] <= @(posedge clk) wdata; wrack <= @(posedge clk) 1; //empty <= @(posedge clk) 0; while (write == 1) @(posedge clk) enter_new_state(`C_wrack1); @(posedge clk) enter_new_state(`C_wrack0); wrack <= @(posedge clk) 0; i <= @(posedge clk) i+1; //++++++++++++++++++++++++++++++++++++++ //geändert: empty <= @(posedge clk) 0; //++++++++++++++++++++++++++++++++++++++ @(posedge clk)#1; if (r == i) full <= @(posedge clk) 1; end else if (read == 1) begin @(posedge clk) enter_new_state(`C_SEND); rdata <= @(posedge clk) dest[r]; rdack <= @(posedge clk) 1; //full <= @(posedge clk) 0; while (read == 1) @(posedge clk) enter_new_state(`C_rdack1); @(posedge clk) enter_new_state(`C_rdack0); rdack <= @(posedge clk) 0; r <= @(posedge clk) r+1; //++++++++++++++++++++++++++++++++++++++ //geändert: full <= @(posedge clk) 0; //++++++++++++++++++++++++++++++++++++++ @(posedge clk)#1; if (r == i) //@(posedge clk)#1; empty <= @(posedge clk) 1; end else @(posedge clk) enter_new_state(`C_WAIT); end end task enter_new_state; input [`C_NUM_STATE_BITS-1:0] this_state; begin present_state = this_state; #1; ready = 0; end endtask endmodule //========================================== module top; //####################### eigener mischt reg prod_clk; initial prod_clk = 0; always #117 prod_clk = ~prod_clk; //####################### eigener mischt - ende reg clk; initial clk = 0; always #11 clk = ~clk; //initial #1000000 $finish; reg start; wire [7:0]wdata; wire [7:0]rdata; wire write, read; wire wrack, rdack; wire [`P_NUM_STATE_BITS-1:0] p_state; wire [`C_NUM_STATE_BITS-1:0] c_state; wire p_ready; wire f_ready; wire c_ready; wire full, empty; integer ii; producer prod(clk, start, wdata, write, wrack, full, p_ready, p_state); fifo fif(clk, start, wdata, write, wrack, f_ready, rdack, rdata, read, full, empty, c_state); consumer cons(clk, start, rdata, read, rdack, empty, c_ready, present_state); initial begin start = 0; #3500 start = 1; #2100 start = 0; wait(p_ready); // print contents of src and dest: $write("\n"); for (ii=0; ii<17; ii=ii+1) $write("src[%d]=%d dest[%d]=%d gelesen[%d]=%d \n", ii, prod.src[ii], ii, fif.dest[ii], ii, cons.src[ii]); $write("\n"); $finish; end always @(posedge clk) #1 begin p_print_state_name(prod.present_state); $write("prod.i=%d write=%b wrack=%b wdata=%d fif.i=%d empty:%d full:%d i=%d r=%d " , prod.i, write, wrack, wdata, fif.i, fif.empty, fif.full, fif.i, fif.r); c_print_state_name(fif.present_state); $write("\n"); end task p_print_state_name; input [`P_NUM_STATE_BITS-1:0] state_code; begin case(state_code) `P_IDLE: $write("P_IDLE "); `P_SEND1: $write("P_SEND1 "); `P_SEND2: $write("P_SEND2 "); `P_READY: $write("P_READY "); `P_NO_SEND: $write("P_NO_SEND "); `P_WAIT: $write("P_WAIT "); endcase end endtask task c_print_state_name; input [`C_NUM_STATE_BITS-1:0] state_code; begin case(state_code) `C_IDLE: $write("C_IDLE "); `C_WAIT: $write("C_WAIT "); `C_RECEIVE: $write("C_RECEIVE "); `C_wrack0: $write("C_wrack0 "); `C_wrack1: $write("C_wrack1 "); `C_SEND: $write("C_SEND "); `C_rdack1: $write("C_rdack1 "); `C_rdack0:$write("C_rdack0 "); endcase end endtask endmodule