cpldfit:  version I.27                              Xilinx Inc.
                                  Fitter Report
Design Name: ccd_logic                           Date:  6-14-2006,  0:51AM
Device Used: XC9572-15-PC44
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
38 /72  ( 53%) 82  /360  ( 23%) 69 /144 ( 48%)   31 /72  ( 43%) 7  /34  ( 21%)

** Function Block Resources **

Function    Mcells      FB Inps     Signals     Pterms      IO          
Block       Used/Tot    Used/Tot    Used        Used/Tot    Used/Tot    
FB1           0/18        0/36        0           0/90       0/ 9
FB2          16/18       27/36       27          44/90       2/ 9
FB3           6/18       13/36       13           8/90       1/ 8
FB4          16/18       29/36       29          30/90       3/ 8
             -----       -----                   -----       -----     
             38/72       69/144                  82/360      6/34 

* - Resource is exhausted

** Global Control Resources **

The complement of 'CLK' mapped onto global clock net GCK3.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    0           0    |  I/O              :     6      28
Output        :    6           6    |  GCK/IO           :     1       3
Bidirectional :    0           0    |  GTS/IO           :     0       2
GCK           :    1           1    |  GSR/IO           :     0       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total      7           7

** Power Data **

There are 38 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
**************************  Errors and Warnings  ***************************

WARNING:Cpld:828 - Signal 'INT_EN.SETF' has been minimized to 'GND'.
     The signal is removed.
*************************  Summary of Mapped Logic  ************************

** 6 Outputs **

Signal                      Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                        Pts   Inps          No.  Type    Use     Mode Rate State
CCD_ROG                     1     14    FB2_2   35   I/O     O       STD  SLOW 
CCD_CLK                     2     11    FB2_6   37   I/O     O       STD  SLOW RESET
ADC_RDY                     1     2     FB3_17  22   I/O     O       STD  SLOW 
INT1                        1     2     FB4_2   24   I/O     O       STD  SLOW 
INT0                        2     12    FB4_8   26   I/O     O       STD  SLOW RESET
RESET                       1     2     FB4_11  28   I/O     O       STD  SLOW 

** 32 Buried Nodes **

Signal                      Total Total Loc     Pwr  Reg Init
Name                        Pts   Inps          Mode State
PIX_CNT<10>                 2     11    FB2_4   STD  RESET
PIX_CNT<0>                  2     13    FB2_5   STD  RESET
CLK_CNT<2>                  2     10    FB2_7   STD  RESET
CLK_CNT<1>                  2     10    FB2_8   STD  RESET
$OpTx$INV$79__$INT          2     11    FB2_9   STD  
ROG_EN                      2     10    FB2_10  STD  RESET
RESET_EN                    2     10    FB2_11  STD  RESET
PIX_CNT<5>                  3     13    FB2_12  STD  RESET
PIX_CNT<3>                  3     13    FB2_13  STD  RESET
PIX_CNT<11>                 3     13    FB2_14  STD  RESET
INT_RES                     2     12    FB2_15  STD  RESET
INT_ACT                     3     14    FB2_16  STD  RESET
ADC_EN                      2     10    FB2_17  STD  RESET
ADC_ACT/ADC_ACT_SETF__$INT  11    12    FB2_18  STD  
CLK_CNT<6>                  1     6     FB3_13  STD  RESET
CLK_CNT<0>                  1     10    FB3_14  STD  RESET
INT_EN                      1     1     FB3_15  STD  SET
CLK_CNT<9>                  2     10    FB3_16  STD  RESET
CLK_CNT<8>                  2     10    FB3_18  STD  RESET
PIX_CNT<9>                  2     10    FB4_4   STD  RESET
PIX_CNT<8>                  2     9     FB4_5   STD  RESET
PIX_CNT<7>                  2     8     FB4_6   STD  RESET
PIX_CNT<6>                  2     7     FB4_7   STD  RESET
PIX_CNT<4>                  2     5     FB4_9   STD  RESET
PIX_CNT<2>                  2     3     FB4_10  STD  RESET
PIX_CNT<1>                  2     2     FB4_12  STD  RESET
CLK_CNT<7>                  2     10    FB4_13  STD  RESET
CLK_CNT<5>                  2     10    FB4_14  STD  RESET
CLK_CNT<4>                  2     10    FB4_15  STD  RESET
CLK_CNT<3>                  2     10    FB4_16  STD  RESET
$OpTx$FX_DC$29              2     5     FB4_17  STD  
ADC_ACT                     2     9     FB4_18  STD  RESET

** 1 Inputs **

Signal                      Loc     Pin  Pin     Pin     
Name                                No.  Type    Use     
CLK                         FB1_14  7    GCK/I/O GCK

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@)         - Signal used as input (wire-AND input) to the macrocell logic.
               The number of Signals Used may exceed the number of FB Inputs
               Used due to wire-ANDing in the switch matrix.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               0/36
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB1_1         (b)     
(unused)              0       0     0   5     FB1_2   1     I/O     
(unused)              0       0     0   5     FB1_3         (b)     
(unused)              0       0     0   5     FB1_4         (b)     
(unused)              0       0     0   5     FB1_5   2     I/O     
(unused)              0       0     0   5     FB1_6   3     I/O     
(unused)              0       0     0   5     FB1_7         (b)     
(unused)              0       0     0   5     FB1_8   4     I/O     
(unused)              0       0     0   5     FB1_9   5     GCK/I/O 
(unused)              0       0     0   5     FB1_10        (b)     
(unused)              0       0     0   5     FB1_11  6     GCK/I/O 
(unused)              0       0     0   5     FB1_12        (b)     
(unused)              0       0     0   5     FB1_13        (b)     
(unused)              0       0     0   5     FB1_14  7     GCK/I/O GCK
(unused)              0       0     0   5     FB1_15  8     I/O     
(unused)              0       0     0   5     FB1_16        (b)     
(unused)              0       0     0   5     FB1_17  9     I/O     
(unused)              0       0     0   5     FB1_18        (b)     
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               27/9
Number of signals used by logic mapping into function block:  27
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   /\5   0     FB2_1         (b)     (b)
CCD_ROG               1       0     0   4     FB2_2   35    I/O     O
(unused)              0       0     0   5     FB2_3         (b)     
PIX_CNT<10>           2       0     0   3     FB2_4         (b)     (b)
PIX_CNT<0>            2       0     0   3     FB2_5   36    I/O     (b)
CCD_CLK               2       0     0   3     FB2_6   37    I/O     O
CLK_CNT<2>            2       0     0   3     FB2_7         (b)     (b)
CLK_CNT<1>            2       0     0   3     FB2_8   38    I/O     (b)
$OpTx$INV$79__$INT    2       0     0   3     FB2_9   39    GSR/I/O (b)
ROG_EN                2       0     0   3     FB2_10        (b)     (b)
RESET_EN              2       0     0   3     FB2_11  40    GTS/I/O (b)
PIX_CNT<5>            3       0     0   2     FB2_12        (b)     (b)
PIX_CNT<3>            3       0     0   2     FB2_13        (b)     (b)
PIX_CNT<11>           3       0     0   2     FB2_14  42    GTS/I/O (b)
INT_RES               2       0     0   3     FB2_15  43    I/O     (b)
INT_ACT               3       0     0   2     FB2_16        (b)     (b)
ADC_EN                2       0   \/1   2     FB2_17  44    I/O     (b)
ADC_ACT/ADC_ACT_SETF__$INT
                     11       6<-   0   0     FB2_18        (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$INV$79__$INT.LFBK  10: CLK_CNT<7>        19: PIX_CNT<2> 
  2: ADC_ACT                  11: CLK_CNT<8>        20: PIX_CNT<3>.LFBK 
  3: CLK_CNT<0>               12: CLK_CNT<9>        21: PIX_CNT<4> 
  4: CLK_CNT<1>.LFBK          13: INT_ACT.LFBK      22: PIX_CNT<5>.LFBK 
  5: CLK_CNT<2>.LFBK          14: PIX_CLK.LFBK      23: PIX_CNT<6> 
  6: CLK_CNT<3>               15: PIX_CNT<0>.LFBK   24: PIX_CNT<7> 
  7: CLK_CNT<4>               16: PIX_CNT<10>.LFBK  25: PIX_CNT<8> 
  8: CLK_CNT<5>               17: PIX_CNT<11>.LFBK  26: PIX_CNT<9> 
  9: CLK_CNT<6>               18: PIX_CNT<1>        27: ROG_EN.LFBK 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
CCD_ROG              .............XXXXXXXXXXXXXX............. 14      14
PIX_CNT<10>          .............XX..XXXXXXXXX.............. 11      11
PIX_CNT<0>           .............XXXXXXXXXXXXX.............. 13      13
CCD_CLK              ..XXXXXXXXXX.X.......................... 11      11
CLK_CNT<2>           ..XXXXXXXXXX............................ 10      10
CLK_CNT<1>           ..XXXXXXXXXX............................ 10      10
$OpTx$INV$79__$INT   ..XXXXXXXXXX.X.......................... 11      11
ROG_EN               ..XXXXXXXXXX............................ 10      10
RESET_EN             ..XXXXXXXXXX............................ 10      10
PIX_CNT<5>           .............XXXXXXXXXXXXX.............. 13      13
PIX_CNT<3>           .............XXXXXXXXXXXXX.............. 13      13
PIX_CNT<11>          .............XXXXXXXXXXXXX.............. 13      13
INT_RES              X.XXXXXXXXXX.X.......................... 12      12
INT_ACT              ............XXXXXXXXXXXXXX.............. 14      14
ADC_EN               ..XXXXXXXXXX............................ 10      10
ADC_ACT/ADC_ACT_SETF__$INT 
                     .X.............XXXXXXXXXXX.............. 12      12
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               13/23
Number of signals used by logic mapping into function block:  13
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB3_1         (b)     
(unused)              0       0     0   5     FB3_2   11    I/O     
(unused)              0       0     0   5     FB3_3         (b)     
(unused)              0       0     0   5     FB3_4         (b)     
(unused)              0       0     0   5     FB3_5   12    I/O     
(unused)              0       0     0   5     FB3_6         (b)     
(unused)              0       0     0   5     FB3_7         (b)     
(unused)              0       0     0   5     FB3_8   13    I/O     
(unused)              0       0     0   5     FB3_9   14    I/O     
(unused)              0       0     0   5     FB3_10        (b)     
(unused)              0       0     0   5     FB3_11  18    I/O     
(unused)              0       0     0   5     FB3_12        (b)     
CLK_CNT<6>            1       0     0   4     FB3_13        (b)     (b)
CLK_CNT<0>            1       0     0   4     FB3_14  19    I/O     (b)
INT_EN                1       0     0   4     FB3_15  20    I/O     (b)
CLK_CNT<9>            2       0     0   3     FB3_16        (b)     (b)
ADC_RDY               1       0     0   4     FB3_17  22    I/O     O
CLK_CNT<8>            2       0     0   3     FB3_18        (b)     (b)

Signals Used by Logic in Function Block
  1: ADC_ACT            6: CLK_CNT<3>        10: CLK_CNT<7> 
  2: ADC_EN             7: CLK_CNT<4>        11: CLK_CNT<8>.LFBK 
  3: CLK_CNT<0>.LFBK    8: CLK_CNT<5>        12: CLK_CNT<9>.LFBK 
  4: CLK_CNT<1>         9: CLK_CNT<6>.LFBK   13: INT_RES 
  5: CLK_CNT<2>       

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
CLK_CNT<6>           ..XXXXXX................................ 6       6
CLK_CNT<0>           ..XXXXXXXXXX............................ 10      10
INT_EN               ............X........................... 1       1
CLK_CNT<9>           ..XXXXXXXXXX............................ 10      10
ADC_RDY              XX...................................... 2       2
CLK_CNT<8>           ..XXXXXXXXXX............................ 10      10
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               29/7
Number of signals used by logic mapping into function block:  29
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB4_1         (b)     
INT1                  1       0     0   4     FB4_2   24    I/O     O
(unused)              0       0     0   5     FB4_3         (b)     
PIX_CNT<9>            2       0     0   3     FB4_4         (b)     (b)
PIX_CNT<8>            2       0     0   3     FB4_5   25    I/O     (b)
PIX_CNT<7>            2       0     0   3     FB4_6         (b)     (b)
PIX_CNT<6>            2       0     0   3     FB4_7         (b)     (b)
INT0                  2       0     0   3     FB4_8   26    I/O     O
PIX_CNT<4>            2       0     0   3     FB4_9   27    I/O     (b)
PIX_CNT<2>            2       0     0   3     FB4_10        (b)     (b)
RESET                 1       0     0   4     FB4_11  28    I/O     O
PIX_CNT<1>            2       0     0   3     FB4_12        (b)     (b)
CLK_CNT<7>            2       0     0   3     FB4_13        (b)     (b)
CLK_CNT<5>            2       0     0   3     FB4_14  29    I/O     (b)
CLK_CNT<4>            2       0     0   3     FB4_15  33    I/O     (b)
CLK_CNT<3>            2       0     0   3     FB4_16        (b)     (b)
$OpTx$FX_DC$29        2       0     0   3     FB4_17  34    I/O     (b)
ADC_ACT               2       0     0   3     FB4_18        (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$FX_DC$29.LFBK         11: CLK_CNT<6>        21: PIX_CNT<2>.LFBK 
  2: ADC_ACT.LFBK                12: CLK_CNT<7>.LFBK   22: PIX_CNT<3> 
  3: ADC_ACT/ADC_ACT_SETF__$INT  13: CLK_CNT<8>        23: PIX_CNT<4>.LFBK 
  4: CCD_CLK                     14: CLK_CNT<9>        24: PIX_CNT<5> 
  5: CLK_CNT<0>                  15: INT_ACT           25: PIX_CNT<6>.LFBK 
  6: CLK_CNT<1>                  16: INT_EN            26: PIX_CNT<7>.LFBK 
  7: CLK_CNT<2>                  17: PIX_CNT<0>        27: PIX_CNT<8>.LFBK 
  8: CLK_CNT<3>.LFBK             18: PIX_CNT<10>       28: PIX_CNT<9>.LFBK 
  9: CLK_CNT<4>.LFBK             19: PIX_CNT<11>       29: RESET_EN 
 10: CLK_CNT<5>.LFBK             20: PIX_CNT<1>.LFBK  

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
INT1                 ..............XX........................ 2       2
PIX_CNT<9>           ...X............X..XXXXXXXX............. 10      10
PIX_CNT<8>           ...X............X..XXXXXXX.............. 9       9
PIX_CNT<7>           ...X............X..XXXXXX............... 8       8
PIX_CNT<6>           ...X............X..XXXXX................ 7       7
INT0                 ................XXXXXXXXXXXX............ 12      12
PIX_CNT<4>           ...X............X..XXX.................. 5       5
PIX_CNT<2>           ...X............X..X.................... 3       3
RESET                .X..........................X........... 2       2
PIX_CNT<1>           ...X............X....................... 2       2
CLK_CNT<7>           ....XXXXXXXXXX.......................... 10      10
CLK_CNT<5>           ....XXXXXXXXXX.......................... 10      10
CLK_CNT<4>           ....XXXXXXXXXX.......................... 10      10
CLK_CNT<3>           ....XXXXXXXXXX.......................... 10      10
$OpTx$FX_DC$29       ...................XXXXX................ 5       5
ADC_ACT              XXX..............XX.....XXXX............ 9       9
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********


$OpTx$FX_DC$29 <= ((NOT PIX_CNT(5))
	OR (NOT PIX_CNT(3) AND NOT PIX_CNT(1).LFBK AND NOT PIX_CNT(2).LFBK AND 
	NOT PIX_CNT(4).LFBK));


$OpTx$INV$79__$INT <= ((PIX_CLK.LFBK)
	OR (CLK_CNT(0) AND CLK_CNT(3) AND CLK_CNT(4) AND 
	CLK_CNT(5) AND NOT CLK_CNT(6) AND CLK_CNT(7) AND CLK_CNT(8) AND 
	CLK_CNT(9) AND NOT CLK_CNT(2).LFBK AND NOT CLK_CNT(1).LFBK));

FDCPE_ADC_ACT: FDCPE port map (ADC_ACT,'0','0',ADC_ACT_CLR,NOT ADC_ACT/ADC_ACT_SETF__$INT);
ADC_ACT_CLR <= (NOT PIX_CNT(10) AND NOT PIX_CNT(11) AND NOT PIX_CNT(6).LFBK AND 
	NOT PIX_CNT(7).LFBK AND NOT PIX_CNT(8).LFBK AND NOT PIX_CNT(9).LFBK AND NOT ADC_ACT.LFBK AND 
	$OpTx$FX_DC$29.LFBK);


ADC_ACT/ADC_ACT_SETF__$INT <= ((EXP0_.EXP)
	OR (ADC_EN.EXP)
	OR (PIX_CNT(7) AND PIX_CNT(11).LFBK)
	OR (PIX_CNT(9) AND PIX_CNT(11).LFBK)
	OR (PIX_CNT(6) AND PIX_CNT(11).LFBK)
	OR (PIX_CNT(8) AND PIX_CNT(11).LFBK)
	OR (PIX_CNT(10).LFBK AND PIX_CNT(11).LFBK));

FDCPE_ADC_EN: FDCPE port map (ADC_EN,'0','0',ADC_EN_CLR,ADC_EN_PRE);
ADC_EN_CLR <= (CLK_CNT(0) AND CLK_CNT(3) AND CLK_CNT(4) AND 
	CLK_CNT(5) AND CLK_CNT(6) AND NOT CLK_CNT(7) AND NOT CLK_CNT(8) AND 
	NOT CLK_CNT(9) AND CLK_CNT(2).LFBK AND NOT CLK_CNT(1).LFBK);
ADC_EN_PRE <= (NOT CLK_CNT(0) AND NOT CLK_CNT(3) AND NOT CLK_CNT(4) AND 
	CLK_CNT(5) AND CLK_CNT(6) AND NOT CLK_CNT(7) AND NOT CLK_CNT(8) AND 
	NOT CLK_CNT(9) AND CLK_CNT(2).LFBK AND NOT CLK_CNT(1).LFBK);


ADC_RDY <= (ADC_ACT AND ADC_EN);

FDCPE_CCD_CLK: FDCPE port map (CCD_CLK,'0','0',CCD_CLK_CLR,CCD_CLK_PRE);
CCD_CLK_CLR <= (NOT CLK_CNT(0) AND NOT CLK_CNT(3) AND NOT CLK_CNT(4) AND 
	NOT CLK_CNT(5) AND NOT CLK_CNT(6) AND NOT CLK_CNT(7) AND NOT CLK_CNT(8) AND 
	NOT CLK_CNT(9) AND PIX_CLK.LFBK AND NOT CLK_CNT(2).LFBK AND NOT CLK_CNT(1).LFBK);
CCD_CLK_PRE <= (NOT CLK_CNT(0) AND NOT CLK_CNT(3) AND NOT CLK_CNT(4) AND 
	NOT CLK_CNT(5) AND NOT CLK_CNT(6) AND NOT CLK_CNT(7) AND NOT CLK_CNT(8) AND 
	NOT CLK_CNT(9) AND NOT PIX_CLK.LFBK AND NOT CLK_CNT(2).LFBK AND NOT CLK_CNT(1).LFBK);


CCD_ROG <= NOT ((NOT PIX_CNT(1) AND NOT PIX_CNT(7) AND NOT PIX_CNT(9) AND 
	NOT PIX_CNT(2) AND NOT PIX_CNT(4) AND NOT PIX_CNT(6) AND NOT PIX_CNT(8) AND 
	PIX_CLK.LFBK AND PIX_CNT(0).LFBK AND NOT PIX_CNT(3).LFBK AND 
	NOT PIX_CNT(5).LFBK AND NOT PIX_CNT(10).LFBK AND NOT PIX_CNT(11).LFBK AND 
	ROG_EN.LFBK));

FTCPE_CLK_CNT0: FTCPE port map (CLK_CNT(0),CLK_CNT_T(0),NOT CLK,'0','0');
CLK_CNT_T(0) <= (CLK_CNT(3) AND CLK_CNT(4) AND CLK_CNT(2) AND 
	CLK_CNT(5) AND CLK_CNT(1) AND CLK_CNT(7) AND NOT CLK_CNT(0).LFBK AND 
	NOT CLK_CNT(6).LFBK AND CLK_CNT(8).LFBK AND CLK_CNT(9).LFBK);

FTCPE_CLK_CNT1: FTCPE port map (CLK_CNT(1),CLK_CNT_T(1),NOT CLK,'0','0');
CLK_CNT_T(1) <= ((CLK_CNT(0))
	OR (CLK_CNT(3) AND CLK_CNT(4) AND CLK_CNT(5) AND 
	NOT CLK_CNT(6) AND CLK_CNT(7) AND CLK_CNT(8) AND CLK_CNT(9) AND 
	CLK_CNT(2).LFBK AND CLK_CNT(1).LFBK));

FTCPE_CLK_CNT2: FTCPE port map (CLK_CNT(2),CLK_CNT_T(2),NOT CLK,'0','0');
CLK_CNT_T(2) <= ((CLK_CNT(0) AND CLK_CNT(1).LFBK)
	OR (CLK_CNT(3) AND CLK_CNT(4) AND CLK_CNT(5) AND 
	NOT CLK_CNT(6) AND CLK_CNT(7) AND CLK_CNT(8) AND CLK_CNT(9) AND 
	CLK_CNT(2).LFBK AND CLK_CNT(1).LFBK));

FTCPE_CLK_CNT3: FTCPE port map (CLK_CNT(3),CLK_CNT_T(3),NOT CLK,'0','0');
CLK_CNT_T(3) <= ((CLK_CNT(0) AND CLK_CNT(2) AND CLK_CNT(1))
	OR (CLK_CNT(2) AND CLK_CNT(1) AND NOT CLK_CNT(6) AND 
	CLK_CNT(8) AND CLK_CNT(9) AND CLK_CNT(3).LFBK AND CLK_CNT(4).LFBK AND 
	CLK_CNT(5).LFBK AND CLK_CNT(7).LFBK));

FTCPE_CLK_CNT4: FTCPE port map (CLK_CNT(4),CLK_CNT_T(4),NOT CLK,'0','0');
CLK_CNT_T(4) <= ((CLK_CNT(0) AND CLK_CNT(2) AND CLK_CNT(1) AND 
	CLK_CNT(3).LFBK)
	OR (CLK_CNT(2) AND CLK_CNT(1) AND NOT CLK_CNT(6) AND 
	CLK_CNT(8) AND CLK_CNT(9) AND CLK_CNT(3).LFBK AND CLK_CNT(4).LFBK AND 
	CLK_CNT(5).LFBK AND CLK_CNT(7).LFBK));

FTCPE_CLK_CNT5: FTCPE port map (CLK_CNT(5),CLK_CNT_T(5),NOT CLK,'0','0');
CLK_CNT_T(5) <= ((CLK_CNT(0) AND CLK_CNT(2) AND CLK_CNT(1) AND 
	CLK_CNT(3).LFBK AND CLK_CNT(4).LFBK)
	OR (CLK_CNT(2) AND CLK_CNT(1) AND NOT CLK_CNT(6) AND 
	CLK_CNT(8) AND CLK_CNT(9) AND CLK_CNT(3).LFBK AND CLK_CNT(4).LFBK AND 
	CLK_CNT(5).LFBK AND CLK_CNT(7).LFBK));

FTCPE_CLK_CNT6: FTCPE port map (CLK_CNT(6),CLK_CNT_T(6),NOT CLK,'0','0');
CLK_CNT_T(6) <= (CLK_CNT(3) AND CLK_CNT(4) AND CLK_CNT(2) AND 
	CLK_CNT(5) AND CLK_CNT(1) AND CLK_CNT(0).LFBK);

FTCPE_CLK_CNT7: FTCPE port map (CLK_CNT(7),CLK_CNT_T(7),NOT CLK,'0','0');
CLK_CNT_T(7) <= ((CLK_CNT(0) AND CLK_CNT(2) AND CLK_CNT(1) AND 
	CLK_CNT(6) AND CLK_CNT(3).LFBK AND CLK_CNT(4).LFBK AND 
	CLK_CNT(5).LFBK)
	OR (NOT CLK_CNT(0) AND CLK_CNT(2) AND CLK_CNT(1) AND 
	NOT CLK_CNT(6) AND CLK_CNT(8) AND CLK_CNT(9) AND CLK_CNT(3).LFBK AND 
	CLK_CNT(4).LFBK AND CLK_CNT(5).LFBK AND CLK_CNT(7).LFBK));

FTCPE_CLK_CNT8: FTCPE port map (CLK_CNT(8),CLK_CNT_T(8),NOT CLK,'0','0');
CLK_CNT_T(8) <= ((CLK_CNT(3) AND CLK_CNT(4) AND CLK_CNT(2) AND 
	CLK_CNT(5) AND CLK_CNT(1) AND CLK_CNT(7) AND CLK_CNT(0).LFBK AND 
	CLK_CNT(6).LFBK)
	OR (CLK_CNT(3) AND CLK_CNT(4) AND CLK_CNT(2) AND 
	CLK_CNT(5) AND CLK_CNT(1) AND CLK_CNT(7) AND NOT CLK_CNT(0).LFBK AND 
	NOT CLK_CNT(6).LFBK AND CLK_CNT(8).LFBK AND CLK_CNT(9).LFBK));

FTCPE_CLK_CNT9: FTCPE port map (CLK_CNT(9),CLK_CNT_T(9),NOT CLK,'0','0');
CLK_CNT_T(9) <= ((CLK_CNT(3) AND CLK_CNT(4) AND CLK_CNT(2) AND 
	CLK_CNT(5) AND CLK_CNT(1) AND CLK_CNT(7) AND CLK_CNT(0).LFBK AND 
	CLK_CNT(6).LFBK AND CLK_CNT(8).LFBK)
	OR (CLK_CNT(3) AND CLK_CNT(4) AND CLK_CNT(2) AND 
	CLK_CNT(5) AND CLK_CNT(1) AND CLK_CNT(7) AND NOT CLK_CNT(0).LFBK AND 
	NOT CLK_CNT(6).LFBK AND CLK_CNT(8).LFBK AND CLK_CNT(9).LFBK));



FDCPE_INT0: FDCPE port map (INT0,'0','0',INT0_CLR,INT0_PRE);
INT0_CLR <= (NOT PIX_CNT(3) AND PIX_CNT(5) AND NOT PIX_CNT(0) AND 
	NOT PIX_CNT(10) AND NOT PIX_CNT(11) AND NOT PIX_CNT(1).LFBK AND NOT PIX_CNT(2).LFBK AND 
	NOT PIX_CNT(4).LFBK AND NOT PIX_CNT(6).LFBK AND NOT PIX_CNT(7).LFBK AND 
	NOT PIX_CNT(8).LFBK AND NOT PIX_CNT(9).LFBK);
INT0_PRE <= (NOT PIX_CNT(3) AND NOT PIX_CNT(5) AND PIX_CNT(0) AND 
	NOT PIX_CNT(10) AND NOT PIX_CNT(11) AND NOT PIX_CNT(1).LFBK AND NOT PIX_CNT(2).LFBK AND 
	NOT PIX_CNT(4).LFBK AND NOT PIX_CNT(6).LFBK AND NOT PIX_CNT(7).LFBK AND 
	NOT PIX_CNT(8).LFBK AND NOT PIX_CNT(9).LFBK);


INT1 <= (INT_ACT AND INT_EN);

FTCPE_INT_ACT: FTCPE port map (INT_ACT,INT_ACT_T,PIX_CLK.LFBK,'0','0');
INT_ACT_T <= ((PIX_CNT(1) AND NOT PIX_CNT(7) AND NOT PIX_CNT(9) AND 
	NOT PIX_CNT(2) AND NOT PIX_CNT(4) AND NOT PIX_CNT(6) AND NOT PIX_CNT(8) AND 
	NOT PIX_CNT(0).LFBK AND NOT PIX_CNT(3).LFBK AND PIX_CNT(5).LFBK AND 
	NOT PIX_CNT(10).LFBK AND PIX_CNT(11).LFBK AND INT_ACT.LFBK)
	OR (PIX_CNT(1) AND NOT PIX_CNT(7) AND NOT PIX_CNT(9) AND 
	NOT PIX_CNT(2) AND NOT PIX_CNT(4) AND NOT PIX_CNT(6) AND NOT PIX_CNT(8) AND 
	NOT PIX_CNT(0).LFBK AND NOT PIX_CNT(3).LFBK AND PIX_CNT(5).LFBK AND 
	NOT PIX_CNT(10).LFBK AND NOT PIX_CNT(11).LFBK AND NOT INT_ACT.LFBK));

FDCPE_INT_EN: FDCPE port map (INT_EN,'0','0',INT_RES,'0');

FDCPE_INT_RES: FDCPE port map (INT_RES,'0','0',NOT $OpTx$INV$79__$INT.LFBK,INT_RES_PRE);
INT_RES_PRE <= (CLK_CNT(0) AND CLK_CNT(3) AND CLK_CNT(4) AND 
	CLK_CNT(5) AND NOT CLK_CNT(6) AND CLK_CNT(7) AND CLK_CNT(8) AND 
	CLK_CNT(9) AND NOT PIX_CLK.LFBK AND NOT CLK_CNT(2).LFBK AND NOT CLK_CNT(1).LFBK);

FTCPE_PIX_CNT0: FTCPE port map (PIX_CNT(0),PIX_CNT_T(0),PIX_CLK.LFBK,'0','0');
PIX_CNT_T(0) <= (NOT PIX_CNT(1) AND NOT PIX_CNT(7) AND NOT PIX_CNT(9) AND 
	NOT PIX_CNT(2) AND NOT PIX_CNT(4) AND NOT PIX_CNT(6) AND NOT PIX_CNT(8) AND 
	NOT PIX_CNT(0).LFBK AND PIX_CNT(3).LFBK AND PIX_CNT(5).LFBK AND 
	NOT PIX_CNT(10).LFBK AND PIX_CNT(11).LFBK);

FTCPE_PIX_CNT1: FTCPE port map (PIX_CNT(1),PIX_CNT(0),CCD_CLK,'0','0');

FTCPE_PIX_CNT2: FTCPE port map (PIX_CNT(2),PIX_CNT_T(2),CCD_CLK,'0','0');
PIX_CNT_T(2) <= (PIX_CNT(0) AND PIX_CNT(1).LFBK);

FTCPE_PIX_CNT3: FTCPE port map (PIX_CNT(3),PIX_CNT_T(3),PIX_CLK.LFBK,'0','0');
PIX_CNT_T(3) <= ((PIX_CNT(1) AND PIX_CNT(2) AND PIX_CNT(0).LFBK)
	OR (NOT PIX_CNT(1) AND NOT PIX_CNT(7) AND NOT PIX_CNT(9) AND 
	NOT PIX_CNT(2) AND NOT PIX_CNT(4) AND NOT PIX_CNT(6) AND NOT PIX_CNT(8) AND 
	NOT PIX_CNT(0).LFBK AND PIX_CNT(3).LFBK AND PIX_CNT(5).LFBK AND 
	NOT PIX_CNT(10).LFBK AND PIX_CNT(11).LFBK));

FTCPE_PIX_CNT4: FTCPE port map (PIX_CNT(4),PIX_CNT_T(4),CCD_CLK,'0','0');
PIX_CNT_T(4) <= (PIX_CNT(3) AND PIX_CNT(0) AND PIX_CNT(1).LFBK AND 
	PIX_CNT(2).LFBK);

FTCPE_PIX_CNT5: FTCPE port map (PIX_CNT(5),PIX_CNT_T(5),PIX_CLK.LFBK,'0','0');
PIX_CNT_T(5) <= ((PIX_CNT(1) AND PIX_CNT(2) AND PIX_CNT(4) AND 
	PIX_CNT(0).LFBK AND PIX_CNT(3).LFBK)
	OR (NOT PIX_CNT(1) AND NOT PIX_CNT(7) AND NOT PIX_CNT(9) AND 
	NOT PIX_CNT(2) AND NOT PIX_CNT(4) AND NOT PIX_CNT(6) AND NOT PIX_CNT(8) AND 
	NOT PIX_CNT(0).LFBK AND PIX_CNT(3).LFBK AND PIX_CNT(5).LFBK AND 
	NOT PIX_CNT(10).LFBK AND PIX_CNT(11).LFBK));

FTCPE_PIX_CNT6: FTCPE port map (PIX_CNT(6),PIX_CNT_T(6),CCD_CLK,'0','0');
PIX_CNT_T(6) <= (PIX_CNT(3) AND PIX_CNT(5) AND PIX_CNT(0) AND 
	PIX_CNT(1).LFBK AND PIX_CNT(2).LFBK AND PIX_CNT(4).LFBK);

FTCPE_PIX_CNT7: FTCPE port map (PIX_CNT(7),PIX_CNT_T(7),CCD_CLK,'0','0');
PIX_CNT_T(7) <= (PIX_CNT(3) AND PIX_CNT(5) AND PIX_CNT(0) AND 
	PIX_CNT(1).LFBK AND PIX_CNT(2).LFBK AND PIX_CNT(4).LFBK AND 
	PIX_CNT(6).LFBK);

FTCPE_PIX_CNT8: FTCPE port map (PIX_CNT(8),PIX_CNT_T(8),CCD_CLK,'0','0');
PIX_CNT_T(8) <= (PIX_CNT(3) AND PIX_CNT(5) AND PIX_CNT(0) AND 
	PIX_CNT(1).LFBK AND PIX_CNT(2).LFBK AND PIX_CNT(4).LFBK AND 
	PIX_CNT(6).LFBK AND PIX_CNT(7).LFBK);

FTCPE_PIX_CNT9: FTCPE port map (PIX_CNT(9),PIX_CNT_T(9),CCD_CLK,'0','0');
PIX_CNT_T(9) <= (PIX_CNT(3) AND PIX_CNT(5) AND PIX_CNT(0) AND 
	PIX_CNT(1).LFBK AND PIX_CNT(2).LFBK AND PIX_CNT(4).LFBK AND 
	PIX_CNT(6).LFBK AND PIX_CNT(7).LFBK AND PIX_CNT(8).LFBK);

FTCPE_PIX_CNT10: FTCPE port map (PIX_CNT(10),PIX_CNT_T(10),PIX_CLK.LFBK,'0','0');
PIX_CNT_T(10) <= (PIX_CNT(1) AND PIX_CNT(7) AND PIX_CNT(9) AND 
	PIX_CNT(2) AND PIX_CNT(4) AND PIX_CNT(6) AND PIX_CNT(8) AND 
	PIX_CNT(0).LFBK AND PIX_CNT(3).LFBK AND PIX_CNT(5).LFBK);

FTCPE_PIX_CNT11: FTCPE port map (PIX_CNT(11),PIX_CNT_T(11),PIX_CLK.LFBK,'0','0');
PIX_CNT_T(11) <= ((PIX_CNT(1) AND PIX_CNT(7) AND PIX_CNT(9) AND 
	PIX_CNT(2) AND PIX_CNT(4) AND PIX_CNT(6) AND PIX_CNT(8) AND 
	PIX_CNT(0).LFBK AND PIX_CNT(3).LFBK AND PIX_CNT(5).LFBK AND 
	PIX_CNT(10).LFBK)
	OR (NOT PIX_CNT(1) AND NOT PIX_CNT(7) AND NOT PIX_CNT(9) AND 
	NOT PIX_CNT(2) AND NOT PIX_CNT(4) AND NOT PIX_CNT(6) AND NOT PIX_CNT(8) AND 
	NOT PIX_CNT(0).LFBK AND PIX_CNT(3).LFBK AND PIX_CNT(5).LFBK AND 
	NOT PIX_CNT(10).LFBK AND PIX_CNT(11).LFBK));


RESET <= (RESET_EN AND ADC_ACT.LFBK);

FDCPE_RESET_EN: FDCPE port map (RESET_EN,'0','0',RESET_EN_CLR,RESET_EN_PRE);
RESET_EN_CLR <= (NOT CLK_CNT(0) AND NOT CLK_CNT(3) AND NOT CLK_CNT(4) AND 
	CLK_CNT(5) AND CLK_CNT(6) AND NOT CLK_CNT(7) AND NOT CLK_CNT(8) AND 
	NOT CLK_CNT(9) AND NOT CLK_CNT(2).LFBK AND CLK_CNT(1).LFBK);
RESET_EN_PRE <= (CLK_CNT(0) AND CLK_CNT(3) AND CLK_CNT(4) AND 
	NOT CLK_CNT(5) AND CLK_CNT(6) AND NOT CLK_CNT(7) AND NOT CLK_CNT(8) AND 
	NOT CLK_CNT(9) AND CLK_CNT(2).LFBK AND CLK_CNT(1).LFBK);

FDCPE_ROG_EN: FDCPE port map (ROG_EN,'0','0',ROG_EN_CLR,ROG_EN_PRE);
ROG_EN_CLR <= (NOT CLK_CNT(0) AND NOT CLK_CNT(3) AND CLK_CNT(4) AND 
	NOT CLK_CNT(5) AND NOT CLK_CNT(6) AND CLK_CNT(7) AND CLK_CNT(8) AND 
	CLK_CNT(9) AND CLK_CNT(2).LFBK AND CLK_CNT(1).LFBK);
ROG_EN_PRE <= (CLK_CNT(0) AND CLK_CNT(3) AND NOT CLK_CNT(4) AND 
	CLK_CNT(5) AND NOT CLK_CNT(6) AND NOT CLK_CNT(7) AND NOT CLK_CNT(8) AND 
	NOT CLK_CNT(9) AND NOT CLK_CNT(2).LFBK AND NOT CLK_CNT(1).LFBK);

Register Legend:
 FDCPE (Q,D,C,CLR,PRE); 
 FTCPE (Q,D,C,CLR,PRE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC9572-15-PC44


   --------------------------------  
  /6  5  4  3  2  1  44 43 42 41 40 \
 | 7                             39 | 
 | 8                             38 | 
 | 9                             37 | 
 | 10                            36 | 
 | 11        XC9572-15-PC44      35 | 
 | 12                            34 | 
 | 13                            33 | 
 | 14                            32 | 
 | 15                            31 | 
 | 16                            30 | 
 | 17                            29 | 
 \ 18 19 20 21 22 23 24 25 26 27 28 /
   --------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 TIE                              23 GND                           
  2 TIE                              24 INT1                          
  3 TIE                              25 TIE                           
  4 TIE                              26 INT0                          
  5 TIE                              27 TIE                           
  6 TIE                              28 RESET                         
  7 CLK                              29 TIE                           
  8 TIE                              30 TDO                           
  9 TIE                              31 GND                           
 10 GND                              32 VCC                           
 11 TIE                              33 TIE                           
 12 TIE                              34 TIE                           
 13 TIE                              35 CCD_ROG                       
 14 TIE                              36 TIE                           
 15 TDI                              37 CCD_CLK                       
 16 TMS                              38 TIE                           
 17 TCK                              39 TIE                           
 18 TIE                              40 TIE                           
 19 TIE                              41 VCC                           
 20 TIE                              42 TIE                           
 21 VCC                              43 TIE                           
 22 ADC_RDY                          44 TIE                           


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc9572-15-PC44
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : SLOW
Power Mode                                  : STD
Ground on Unused IOs                        : OFF
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
FASTConnect/UIM optimzation                 : ON
Local Feedback                              : ON
Pin Feedback                                : ON
Input Limit                                 : 36
Pterm Limit                                 : 25