-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 10:00:27 07/22/06 -- Design Name: -- Module Name: counter - Behavioral -- Project Name: -- Target Device: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity counter is port( clk : in std_logic; reset : in std_logic; switches : in std_logic_vector(3 downto 0); enable : in std_logic; q : out std_logic_vector(7 downto 0) ); end counter; architecture Behavioral of counter is signal count : std_logic_vector(31 downto 0); begin process(clk,enable,reset,switches,count) begin case switches is when "0001" => q <= count(7 downto 0); when "0010" => q <= count(15 downto 8); when "0100" => q <= count(23 downto 16); when "1000" => q <= count(31 downto 24); when others => q <= (others => 'Z'); --Tristate end case; if reset = '1' then --Asynchroner Reset q <= (others => '0'); count <= (others => '0'); elsif rising_edge(clk) then if enable = '0' then --Synchroner Zähler mit enable count <= count +1; end if; end if; end process; end Behavioral;