.include "m16def.inc"


; MASTER einstellungen 
.equ TWI_BIT_RATE			= 255	; Bit-Rate	(11...255				
.equ TWI_PRESCALER			= 3		; Vorteiler: 0=1 1=4 2=16 3=64		

; REGISTER				
.def ADRESSE_SLAVE	= R11

.def DATA_SENDEN_1	= R14

.def temp  			= R16
.def temp1 			= R17
.def temp2 			= R18
.def temp3 			= R19

.cseg					

.org 0					;Startadresse=0				
	rjmp RESET      	;Reset Handler                           


RESET:                        
	
;STACK initialisieren
	ldi 	temp,LOW(RAMEND)
    out 	SPL,temp
    ldi 	temp,HIGH(RAMEND)
    out 	SPH,temp
; PORT B + D alles AUSGÄNGE	
	ldi 	temp,0b11111111
	out 	DDRB,temp
	out 	PORTB,temp
	out 	DDRD,temp
	out 	PORTD,temp
; PORT C alles Eingänge
	clr 	temp
	out		DDRC,temp
; TWI-INITILISIERUNG
	rcall 	TWI_INI

; Startwerte		
	
	ldi 	temp,0b11111110			; SLAVE ADRESSE	127 (0=!General CALL)
	mov 	ADRESSE_SLAVE,temp

	rcall 	wait_1s

LOOP:
	ldi		temp,0b11111111		
	mov 	DATA_SENDEN_1,temp	
	rcall 	TWI_MASTER_TRANSMITTER
	rcall 	wait_1s
	rcall 	wait_1s
	rcall 	wait_1s
	rcall 	wait_1s
	rcall 	wait_1s
	rcall 	wait_1s

	ldi		temp,0b00000000	
	mov 	DATA_SENDEN_1,temp
	rcall 	TWI_MASTER_TRANSMITTER
	rcall 	wait_1s
	rcall 	wait_1s
	rcall 	wait_1s
	rcall 	wait_1s
	rcall 	wait_1s
	rcall 	wait_1s			
rjmp LOOP

TWI_MASTER_TRANSMITTER:
												
	ldi		temp,(1<<TWINT)|(1<<TWSTA)|(1<<TWEN)
	out 	TWCR, temp	
						
	rcall 	TWI_TWINT_wait
										
	in 		temp,TWSR		
	andi 	temp,0xF8
	cpi 	temp,0x08	; 0x08
	brne 	ERROR

						
	out 	TWDR, ADRESSE_SLAVE 								
	ldi 	temp, (1<<TWINT) | (1<<TWEN)
	out 	TWCR, temp

						
	rcall 	TWI_TWINT_wait

										
	in 		temp,TWSR
	andi 	temp,0xF8
	cpi 	temp,0x18	; 0x18
	brne 	ERROR
										
	out 	TWDR, DATA_SENDEN_1
								
	ldi 	temp, (1<<TWINT)|(1<<TWEN)
	out 	TWCR, temp
						
	rcall 	TWI_TWINT_wait

	in 		temp,TWSR
	andi 	temp, 0xF8
	cpi 	temp, 0x28	; 0x28
	brne 	ERROR
	out		PORTB,DATA_SENDEN_1
												
	ldi 	temp, (1<<TWINT)|(1<<TWEN)|(1<<TWSTO)
	out 	TWCR, temp

ret


TWI_INI:
	; TWI TWBR 				Bit RATE Register	
	ldi temp, TWI_BIT_RATE
	out TWBR, temp
	; TWI TWSR 				STATUS-Register		
	ldi temp, TWI_PRESCALER
	out TWSR, temp
	; TWI TWCR 				Control-REGISTER	
	ldi temp,(1<<TWINT)|(0<<TWEA)|(1<<TWSTA)|(0<<TWSTO)|(0<<TWWC)|(1<<TWEN)|(0<<TWIE)
	out TWCR,temp
ret

ERROR:
	sbi PORTD,0
; TWI STOP				
	ldi temp, (1<<TWINT)|(1<<TWEN)|(1<<TWSTO)
	out TWCR, temp
; TWI aus				
	ldi temp, (0<<TWEN)
	out TWCR, temp
; TWI INITIALISIERUNG	
 	rcall TWI_INI
	
	rcall wait_1s
	
	cbi PORTD,0
ret
 
TWI_TWINT_wait:
	in temp, TWCR
	sbrs temp, TWINT
	rjmp TWI_TWINT_wait
ret
		
WAIT_1s:
	push temp1           ; temp1 auf dem Stack sichern            
	push temp2           ; temp2 auf dem Stack sichern            
	push temp3           ; temp3 auf dem Stack sichern            

;------------
	ldi	temp3,5			
	clr temp2
	clr	temp1			
wait1s_w:	
	dec	temp1
	brne	wait1s_w
	dec	temp2		
	brne	wait1s_w
	dec	temp3
	brne	wait1s_w
;------------
	pop temp3      		; temp3 wiederherstellen                    
	pop temp2      		; temp2 wiederherstellen                    
	pop temp1      		; temp1 wiederherstellen                    
ret


-----------------------------SLAVE-----------------------------------------

.include "m8def.inc"


; TWI SLAVE EINSTELLUNGEN
.equ TWI_SLAVE_ADRESSE				= 127	; eigene SLAVE ADRESSE 1...127			
.equ TWI_GENERAL_CALL_enable		= 0		; 1=Generral Call enabled / 0=disabled	
; REGISTER
.def DATA=R15
.def ANZEIGE=R21

.def TEMP = R16
.def TEMP1= R17
.def TEMP2= R18
.def TEMP3= R19
.def TEMP4= R20


.cseg
						;Beginn eines Code-Segmentes
.org 0					;Startadresse=0
	rjmp RESET      	; Reset Handler                           
.org 0x011				; Two-wire Serial Interface Handler 
	rjmp TWSI        
      	  

RESET:                        
	
;STACK initialisieren		
	ldi 	temp, LOW(RAMEND)
    out 	SPL, temp
    ldi 	temp, HIGH(RAMEND)
    out 	SPH, temp
; PORT B + D alles AUSGÄNGE	
	ser 	temp
	out 	DDRB, temp
	out 	DDRD, temp
; PORT C alles EINGÄNGE		
	clr 	TEMP
	out 	DDRC,temp
; TWI INITIALISIERUNG		
	rcall 	TWI_INI
; STARTWERTE				
	clr 	DATA
	sbi		PORTB,0
; alle Interrupts freigeben

sei 


LOOP:
	out	PORTD,ANZEIGE
	rjmp LOOP
	
TWSI:						; TWI INTERRUPT-Routine	
	push 	temp          	; temp auf dem Stack sichern            
	in 		TEMP,SREG		; Einlesen des SREG 
	push 	TEMP	    	; Schreiben von  SREG  im Stack (KOPIE)

	
	in		temp,TWDR
	mov		ANZEIGE,temp
	com		ANZEIGE

;	rcall 	wait_1s	
	
	ldi 	temp,(1<<TWINT)|(1<<TWEA)|(1<<TWEN)|(1<<TWIE)	;das TWINT-Flag löschen
	out 	TWCR,temp

	pop		TEMP			; LESEN von SREG vom STACK (KOPIE)
	out		SREG,TEMP		; Wiederherstellen von SREG       
	pop 	temp      		; temp wiederherstellen                    

reti


TWI_INI:
	clr		temp
	out		TWSR,temp	
	; TWI TWAR (nur SLAVE) 	Adress-Register		
	ldi 	temp,(TWI_SLAVE_ADRESSE<<TWA0)|(TWI_GENERAL_CALL_ENABLE<<TWGCE)
	out 	TWAR,temp
	; TWI TWCR 				Control-REGISTER	
	ldi 	temp, (0<<TWINT)|(1<<TWEA)|(0<<TWSTA)|(0<<TWSTO)|(0<<TWWC)|(1<<TWEN)|(0<<TWIE)
	out 	TWCR,temp
ret

TWI_ERROR:

	sbi 	PORTB,0				
	ldi 	r16, (1<<TWINT)|(1<<TWEN)|(1<<TWSTO)
	out 	TWCR, r16				
	ldi 	r16, (0<<TWEN)
	out 	TWCR, r16	
 	rcall 	TWI_INI	
	rcall 	wait_1s	
	cbi 	PORTB,0
ret

; Wait for TWINT Flag set. 
TWI_TWINT_wait:
	in 		temp, TWCR
	sbrs 	temp, TWINT
	rjmp 	TWI_TWINT_wait
ret

WAIT_1s:
	push temp1           ; temp1 auf dem Stack sichern            
	push temp2           ; temp2 auf dem Stack sichern            
	push temp3           ; temp3 auf dem Stack sichern            

;------------
	ldi	temp3,5			
	clr temp2
	clr	temp1			
wait1s_w:	
	dec	temp1
	brne	wait1s_w
	dec	temp2		
	brne	wait1s_w
	dec	temp3
	brne	wait1s_w
;------------
	pop temp3      		; temp3 wiederherstellen                    
	pop temp2      		; temp2 wiederherstellen                    
	pop temp1      		; temp1 wiederherstellen                    
ret