=== InOutTest.vhd ===
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity InOutTest is
end InOutTest;

architecture Behavioral of InOutTest is

component Test is
	port (
	   sig1   : inout std_logic
	);
end component;
	
signal sig1      : std_logic;

begin

test0: Test
	port map(
		sig1   => sig1 
	);

sig1 <= '1';

end Behavioral;


=== Test.v ===
`timescale 1ns / 1ps

module Test(sig1);
	
	inout            sig1;

	assign   sig1 = 1'bZ;	

	wire     sig1_int;
	assign   sig1_int = sig1;

endmodule