////////////////////////////////////////////////////////////////////////////// // // Xilinx, Inc. 2002 www.xilinx.com // // XAPP 224 - Data Recovery // ////////////////////////////////////////////////////////////////////////////// // // File name : top_v2_fast.v // // Description : Generic top level file to use data recovery module in a Virtex2, // uses two dcms to generate two 90 degree phased clocks at up to 210 Mhz in a -5 . // // Date - revision : May 21st 2006 - v 2.4 // // Author : NJS // // Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are // provided to you "as is". Xilinx and its licensors make and you // receive no warranties or conditions, express, implied, // statutory or otherwise, and Xilinx specifically disclaims any // implied warranties of merchantability, non-infringement,or // fitness for a particular purpose. Xilinx does not warrant that // the functions contained in these designs will meet your // requirements, or that the operation of these designs will be // uninterrupted or error free, or that defects in the Designs // will be corrected. Furthermore, Xilinx does not warrantor // make any representations regarding use or the results of the // use of the designs in terms of correctness, accuracy, // reliability, or otherwise. // // LIMITATION OF LIABILITY. In no event will Xilinx or its // licensors be liable for any loss of data, lost profits,cost // or procurement of substitute goods or services, or for any // special, incidental, consequential, or indirect damages // arising from the use or operation of the designs or // accompanying documentation, however caused and on any theory // of liability. This limitation will apply even if Xilinx // has been advised of the possibility of such damage. This // limitation shall apply not-withstanding the failure of the // essential purpose of any limited remedies herein. // // Copyright © 2002 Xilinx, Inc. // All rights reserved // ////////////////////////////////////////////////////////////////////////////// // `timescale 1 ps / 1ps module top_v2_fast ( clkin, // clock input rstin, // reset input datain, // data input dummy, // dummy output for recovered data dvalid, // recovered data valid when high locked) ; // DLL locked input clkin, rstin, datain ; output [1:0] dummy, dvalid ; output locked ; reg [1:0] dummy, dvalid; wire clk ; wire clkdcm ; wire clkint; wire clk90; wire clk90dcm; wire [1:0] dummyint ; wire [1:0] dvalidint ; wire locked0 ; wire locked1 ; wire low ; // synthesis attribute CLKOUT_PHASE_SHIFT of dcm_1 "FIXED" // synthesis attribute PHASE_SHIFT of dcm_1 "64" // synthesis attribute DLL_FREQUENCY_MODE of dcm_1 "HIGH" assign locked = locked0 & locked1 ; assign low = 1'b0 ; DCM #(.CLKIN_PERIOD (2.5), .DLL_FREQUENCY_MODE ("HIGH")) dcm_0( .CLKIN(clkint), .CLKFB(clk), .DSSEN(low), .PSINCDEC(low), .PSEN(low), .PSCLK(low), .RST(rstin), .CLK0(clkdcm), .LOCKED(locked0)) ; // synthesis translate_off // // Simulation attributes for DCM // defparam dcm_1.CLKOUT_PHASE_SHIFT = "FIXED" ; defparam dcm_1.PHASE_SHIFT = 64 ; // synthesis translate_on // DCM #(.CLKIN_PERIOD (2.5), .CLKOUT_PHASE_SHIFT ("FIXED"), .PHASE_SHIFT (64), // set to 0 for the moment .DLL_FREQUENCY_MODE ("HIGH")) dcm_1( .CLKIN (clkint), .CLKFB (clk90), .DSSEN (low), .PSINCDEC (low), .PSEN (low), .PSCLK (low), .RST (rstin), .CLK0 (clk90dcm), .LOCKED (locked1)) ; IBUFG ibufg1(.I(clkin), .O(clkint) ); BUFG bufg1(.I(clkdcm), .O(clk) ); BUFG bufg2(.I(clk90dcm), .O(clk90) ); data_recovery_virtex2_fast drmodule ( .data (datain), .rst (rstin), .clk (clk), .clk90 (clk90), .sdata (dummyint), .dv (dvalidint) ); always @(posedge clk or posedge rstin) begin if (rstin) begin dummy = 2'b00; dvalid = 2'b00; end else begin dummy = dummyint; dvalid = dvalidint; end end endmodule