;*******************************************************

; Testprojekt
; SN, 2005/04

; V2.0 for AT2313
; gibt zum Start die VersionsNr auf der seriellen aus
; Encoder muss an PB.0 und PB.1 angeschlossen sein
; Taster muss an PB.2 
; Dreh nach rechts gibt +, links - aus
; Drücken gibt 1, loslassen 0 aus
;
; V2.1 for ATMega32
;  SPH muss gesetzt werden
;  URSEL muss auf 1 gesetzt werden (sonst nix serielle)
;  Ausgabe auf PortC hinzugefügt (LED toggelt)
;*******************************************************


;.include "8515def.inc"
.include "m32def.inc"
;.include "tn2313def.inc"

.def Temp 		=r16 ; Temporary register
.def Delay 		=r17 ; Delay variable 1
.def Delay2 	=r18 ; Delay variable 2
.def OutChar 	=r19
.def PortB_old 	=r20
.def EncIn 		=r21
.def EncInOld 	=r22
.def Temp2 		=r23
.def OutByte	=r24

.equ	LF = 0x0a
.equ	CR = 0x0d

.equ	BIT0 = 1
.equ	BIT1 = 2
.equ	BIT2 = 4
.equ	BIT3 = 8
.equ	BIT4 = 0x10
.equ	BIT5 = 0x20
.equ	BIT6 = 0x40
.equ	BIT7 = 0x80


;***** Vectortable ***** 

.org	0
RESET:
	jmp		main


;***** constants ***** 

Hello:	.db	"Encoder Test V2.1",0x0d, 0x0a,0

EncTbl:	.db	1,3,0,2

;***** Initialization
MAIN:
	ser		Temp
	ldi		temp, LOW(RAMEND)	; load last RAM address
	out		SPL, temp		; init stackpointer
	ldi		temp, HIGH(RAMEND)	; load last RAM address
	out		SPH, temp		; init stackpointer
	call	dly

Port_Init:
	ldi		temp, 0			; define B as Input (default)
	out		DDRB, temp
	ldi		temp, 0xff		; PullUp's ein
	out		PORTB, temp
	ldi		temp, 0xff		; define C as Output
	out		DDRC, temp
	ldi		OutByte, ~1
	out		PORTC, OutByte		; reset PortC outputs

USART_Init:
	; Set baud rate (9600 @ 3,86 Mhz)
	ldi		temp,0
	out 	UBRRH, temp
	ldi		temp, 23
	out 	UBRRL, temp
	; Enable receiver and transmitter
	ldi 	temp, (1<<RXEN)|(1<<TXEN)
	out 	UCSRB,temp
	; Set frame format: 8data, 1stop bit
	ldi 	r16, (1<<URSEL)|(0<<USBS)|(3<<UCSZ0)
	out 	UCSRC,r16

;**** Initial message
SayHello:
	ldi		ZL,LOW(hello*2)
	ldi		ZH,HIGH(hello*2)
	call	TxString

	in		EncInOld, PINB				; akt Status lesen

;**** endless loop
LOOP:
	in		temp, PINB
	mov		EncIn, temp					; save Input

	andi	temp, (BIT0 | BIT1)			; Encoderbits ausmaskieren
	mov		temp2, EncInOld				; get old status
	andi	temp2,(BIT0 | BIT1)

	cp		temp, temp2
	breq	ChkPushBtn

	ldi		ZL,LOW(EncTbl*2)			; load address of table w old states
	ldi		ZH,HIGH(EncTbl*2)
	add		ZL, temp					; add index
	lpm		temp, Z
	cp		temp, temp2					; compare w prev status
	breq	StepNeg						; ok, found neg Step
	
	com		temp						; reverse test
	andi	temp, (BIT0|BIT1)
	ldi		ZL,LOW(EncTbl*2)			; load address of table w old states
	ldi		ZH,HIGH(EncTbl*2)
	add		ZL, temp					; add index
	cp		temp, temp2					; compare w prev status
	breq	StepPos						; ok, found pos Step
	rjmp	ChkPushBtn					; not ok, skipped Step


StepPos:
	ldi		OutChar, '+'
	rcall	TxChar
	sec
	ror		OutByte
	brcs	SP1
	ror		OutByte
SP1:out		PortC, OutByte
	rjmp	OutCR

StepNeg:
	ldi		OutChar, '-'
	rcall	TxChar
	sec
	rol		OutByte
	brcs	SN1
	rol		OutByte
SN1:out		PortC, OutByte
	rjmp	OutCR

OutCR:
	ldi		OutChar, CR
	rcall	TxChar
	ldi		OutChar, LF
	rcall	TxChar

ChkPushBtn:
	mov		temp,EncIn
	eor		temp,EncInOld
	andi	temp,BIT2
	breq	ChkPushBtn2

	ldi		OutChar, '0'
	sbrs	EncIn,2
	inc		OutChar
	rcall	TxChar

	ldi		OutChar, CR
	rcall	TxChar
	ldi		OutChar, LF
	rcall	TxChar

ChkPushBtn2:
	mov		temp,EncIn
	eor		temp,EncInOld
	andi	temp,BIT3
	breq	ChkPushBtn3

	ldi		OutChar, '2'
	sbrs	EncIn,3
	inc		OutChar
	sbi		PortC,0
	rcall	TxChar

	ldi		OutChar, CR
	rcall	TxChar
	ldi		OutChar, LF
	rcall	TxChar

ChkPushBtn3:
	mov		temp,EncIn
	eor		temp,EncInOld
	andi	temp,BIT5
	breq	EncEnd

	ldi		OutChar, '4'
	sbrs	EncIn,5
	inc		OutChar
	cbi		PortC,0
	rcall	TxChar

	ldi		OutChar, CR
	rcall	TxChar
	ldi		OutChar, LF
	rcall	TxChar



EncEnd:	
	mov		EncInOld, EncIn

	;rcall 	dly
	rjmp	LOOP


; *********** Subroutines *********** 

TxString:
	lpm		OutChar,Z
	tst		OutChar
	breq	TxStringExit
	rcall	TxChar
	adiw	ZL,1
	jmp	TxString
TxStringExit:
	ret

TxChar:
	sbis	UCSRA, UDRE
	jmp	TxChar
	out		UDR, OutChar
	ret

	;**** Now wait a while to make LED changes visible.
DLY:
	;ret
	dec		Delay
	brne	DLY
	dec		Delay2
	brne	DLY
	ret