Version 4
SHEET 1 992 680
WIRE -64 112 -96 112
WIRE 32 112 -64 112
WIRE 144 112 112 112
WIRE 272 112 224 112
WIRE 368 112 272 112
WIRE -64 144 -64 112
WIRE 272 144 272 112
WIRE -64 240 -64 224
WIRE 272 240 272 208
FLAG 272 240 0
FLAG -64 240 0
FLAG -96 112 FPGA_output_Pin
FLAG 368 112 SDRAM_input_Pin
SYMBOL res 240 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 0.026R
SYMBOL ind 128 96 R90
WINDOW 0 5 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName L1
SYMATTR Value 12.48n
SYMBOL cap 256 144 R0
SYMATTR InstName C1
SYMATTR Value 6p
SYMBOL voltage -64 128 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value PULSE(0 3.3 0.000000001 0.0000000006 0.0000000006 0.000000004 0.000000008)
TEXT -98 264 Left 2 !.tran 0 0.000000030 0 0.000000000001