Version 4
SHEET 1 1128 680
WIRE 320 -80 80 -80
WIRE 80 -48 80 -80
WIRE 320 16 320 -80
WIRE 80 48 80 32
WIRE -640 112 -720 112
WIRE -592 112 -640 112
WIRE -480 112 -512 112
WIRE -400 112 -400 32
WIRE -400 112 -480 112
WIRE -256 112 -400 112
WIRE -16 112 -16 48
WIRE -16 112 -160 112
WIRE 80 112 -16 112
WIRE 112 112 80 112
WIRE 224 112 192 112
WIRE 272 112 224 112
WIRE 320 112 320 80
WIRE 320 112 272 112
WIRE -640 128 -640 112
WIRE -480 128 -480 112
WIRE -256 144 -320 144
WIRE -96 144 -160 144
WIRE 80 144 80 112
WIRE 224 144 224 112
WIRE 320 144 320 112
WIRE -720 176 -720 112
WIRE -640 208 -640 192
WIRE -480 208 -480 192
WIRE 80 240 80 208
WIRE 224 240 224 208
WIRE 320 240 320 208
WIRE -720 272 -720 256
FLAG 80 240 0
FLAG -720 272 0
FLAG -400 32 FPGA_output_Pin
FLAG -16 48 SDRAM_input_Pin
FLAG -96 144 0
FLAG -320 144 0
FLAG -480 208 0
FLAG -640 208 0
FLAG 320 240 0
FLAG 80 48 0
FLAG 224 240 0
FLAG 272 112 ramc
SYMBOL cap 64 144 R0
SYMATTR InstName C1
SYMATTR Value 2p
SYMBOL voltage -720 160 R0
WINDOW 123 0 0 Left 2
WINDOW 39 24 124 Left 2
SYMATTR SpiceLine Rser=20
SYMATTR InstName V1
SYMATTR Value PULSE(0 3.3 1n 0.6n 0.6n 4n 8n)
SYMBOL tline -208 128 R0
SYMATTR InstName T1
SYMATTR Value Td=0.1n Z0=80
SYMBOL ind -608 128 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 5n
SYMBOL cap -496 128 R0
SYMATTR InstName C2
SYMATTR Value 2p
SYMBOL cap -656 128 R0
SYMATTR InstName C3
SYMATTR Value 2p
SYMBOL diode 304 208 M180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value DCL
SYMBOL ind 96 128 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L2
SYMATTR Value 5n
SYMBOL diode 304 80 M180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D2
SYMATTR Value DCL
SYMBOL voltage 80 -64 R0
SYMATTR InstName V2
SYMATTR Value 3.3
SYMBOL cap 208 144 R0
SYMATTR InstName C4
SYMATTR Value 2p
TEXT -696 360 Left 2 !.tran 0 30n 0 10p
TEXT -704 408 Left 2 !.model DCL D(RS=10)
TEXT -344 200 Left 4 ;2cm Leitung