Started : "Synthesize". WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 12 days, this program will not operate. For more information about this product, please refer to the Evaluation Agreement, which was shipped to you along with the Evaluation CDs. To purchase an annual license for this software, please contact your local Field Applications Engineer (FAE) or salesperson. If you have any questions, or if we can assist in any way, please send an email to: eval@xilinx.com Thank You! ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file "C:/Ruder/Code/invPendel/Version3/conv.vhd" in Library work. Architecture behavioral of Entity conv is up to date. Compiling vhdl file "C:/Ruder/Code/invPendel/Version3/counter.vhd" in Library work. Entity compiled. Entity (Architecture ) compiled. Compiling vhdl file "C:/Ruder/Code/invPendel/Version3/upcnt5.vhd" in Library work. Entity compiled. Entity (Architecture ) compiled. Compiling vhdl file "C:/Ruder/Code/invPendel/Version3/convSigned.vhd" in Library work. Architecture behavioral of Entity convsigned is up to date. Compiling vhdl file "C:/Ruder/Code/invPendel/Version3/key_debounce.vhd" in Library work. Architecture behavioral of Entity key_debounce is up to date. Compiling vhdl file "C:/Ruder/Code/invPendel/Version3/convLV.vhd" in Library work. Architecture behavioral of Entity convlv is up to date. Compiling vhdl file "C:/Ruder/Code/invPendel/Version3/hex2led.vhd" in Library work. Architecture behavioral of Entity hex2led is up to date. Compiling vhdl file "C:/Ruder/Code/invPendel/Version3/hex2led2.vhd" in Library work. Architecture behavioral of Entity hex2led2 is up to date. Compiling vhdl file "C:/Ruder/Code/invPendel/Version3/display.vhd" in Library work. Architecture behavioral of Entity display is up to date. Compiling vhdl file "C:/Ruder/Code/invPendel/Version3/invPenBib.vhd" in Library work. Architecture invpenbib of Entity invpenbib is up to date. Compiling vhdl file "C:/Ruder/Code/invPendel/Version3/simpleSPI.vhd" in Library work. Architecture behavioral of Entity simplespi is up to date. Compiling vhdl file "C:/Ruder/Code/invPendel/Version3/dcm1.vhd" in Library work. Architecture behavioral of Entity dcm1 is up to date. Compiling vhdl file "C:/Ruder/Code/invPendel/Version3/spiController.vhd" in Library work. Architecture behavioral of Entity spicontroler is up to date. Compiling vhdl file "C:/Ruder/Code/invPendel/Version3/diff2.vhd" in Library work. Architecture behavioral of Entity diff2 is up to date. Compiling vhdl file "C:/Ruder/Code/invPendel/Version3/kalib.vhd" in Library work. Architecture behavioral of Entity kalib is up to date. Compiling vhdl file "C:/Ruder/Code/invPendel/Version3/zRegler.vhd" in Library work. Architecture behavioral of Entity zregler is up to date. Compiling vhdl file "C:/Ruder/Code/invPendel/Version3/pwm.vhd" in Library work. Architecture behavioral of Entity pwm is up to date. Compiling vhdl file "C:/Ruder/Code/invPendel/Version3/dispSigned16.vhd" in Library work. Architecture behavioral of Entity dispsigned16 is up to date. Compiling vhdl file "C:/Ruder/Code/invPendel/Version3/stateMachine.vhd" in Library work. Architecture behavioral of Entity statemachine is up to date. Compiling vhdl file "C:/Ruder/Code/invPendel/Version3/invPendel.vhd" in Library work. Entity compiled. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:753 - "C:/Ruder/Code/invPendel/Version3/invPendel.vhd" line 114: Unconnected output port 'CLKIN_IBUFG_OUT' of component 'dcm1'. Entity analyzed. Unit generated. Analyzing Entity (Architecture ). WARNING:Xst:766 - "C:/Ruder/Code/invPendel/Version3/dcm1.vhd" line 98: Generating a Black Box for component . WARNING:Xst:766 - "C:/Ruder/Code/invPendel/Version3/dcm1.vhd" line 102: Generating a Black Box for component . WARNING:Xst:766 - "C:/Ruder/Code/invPendel/Version3/dcm1.vhd" line 106: Generating a Black Box for component . WARNING:Xst:766 - "C:/Ruder/Code/invPendel/Version3/dcm1.vhd" line 110: Generating a Black Box for component . WARNING:Xst:753 - "C:/Ruder/Code/invPendel/Version3/dcm1.vhd" line 114: Unconnected output port 'CLK90' of component 'DCM'. WARNING:Xst:753 - "C:/Ruder/Code/invPendel/Version3/dcm1.vhd" line 114: Unconnected output port 'CLK180' of component 'DCM'. WARNING:Xst:753 - "C:/Ruder/Code/invPendel/Version3/dcm1.vhd" line 114: Unconnected output port 'CLK270' of component 'DCM'. WARNING:Xst:753 - "C:/Ruder/Code/invPendel/Version3/dcm1.vhd" line 114: Unconnected output port 'CLK2X' of component 'DCM'. WARNING:Xst:753 - "C:/Ruder/Code/invPendel/Version3/dcm1.vhd" line 114: Unconnected output port 'CLK2X180' of component 'DCM'. WARNING:Xst:753 - "C:/Ruder/Code/invPendel/Version3/dcm1.vhd" line 114: Unconnected output port 'CLKFX180' of component 'DCM'. WARNING:Xst:753 - "C:/Ruder/Code/invPendel/Version3/dcm1.vhd" line 114: Unconnected output port 'STATUS' of component 'DCM'. WARNING:Xst:753 - "C:/Ruder/Code/invPendel/Version3/dcm1.vhd" line 114: Unconnected output port 'LOCKED' of component 'DCM'. WARNING:Xst:753 - "C:/Ruder/Code/invPendel/Version3/dcm1.vhd" line 114: Unconnected output port 'PSDONE' of component 'DCM'. WARNING:Xst:766 - "C:/Ruder/Code/invPendel/Version3/dcm1.vhd" line 114: Generating a Black Box for component . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). WARNING:Xst:753 - "C:/Ruder/Code/invPendel/Version3/stateMachine.vhd" line 47: Unconnected output port 'key_up' of component 'key_debounce'. WARNING:Xst:753 - "C:/Ruder/Code/invPendel/Version3/stateMachine.vhd" line 53: Unconnected output port 'key_up' of component 'key_debounce'. WARNING:Xst:753 - "C:/Ruder/Code/invPendel/Version3/stateMachine.vhd" line 59: Unconnected output port 'key_up' of component 'key_debounce'. WARNING:Xst:753 - "C:/Ruder/Code/invPendel/Version3/stateMachine.vhd" line 65: Unconnected output port 'key_up' of component 'key_debounce'. Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). debounce = 1000 Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "C:/Ruder/Code/invPendel/Version3/key_debounce.vhd". Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit xor2 for signal <$n0008> created at line 31. Found 10-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Counter(s). inferred 5 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/Ruder/Code/invPendel/Version3/counter.vhd". Found 2-bit register for signal . Found 12-bit up counter for signal . Found 2-bit up counter for signal . Summary: inferred 2 Counter(s). inferred 2 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/Ruder/Code/invPendel/Version3/display.vhd". Found 1-of-4 decoder for signal . Found 8-bit 4-to-1 multiplexer for signal . Summary: inferred 8 Multiplexer(s). inferred 1 Decoder(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/Ruder/Code/invPendel/Version3/hex2led2.vhd". Found 16x8-bit ROM for signal . Summary: inferred 1 ROM(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/Ruder/Code/invPendel/Version3/hex2led.vhd". Found 16x8-bit ROM for signal . Summary: inferred 1 ROM(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/Ruder/Code/invPendel/Version3/convLV.vhd". Found 16x4-bit ROM for signal <$n0000>. Summary: inferred 1 ROM(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/Ruder/Code/invPendel/Version3/conv.vhd". Unit synthesized. Synthesizing Unit . Related source file is "C:/Ruder/Code/invPendel/Version3/convSigned.vhd". WARNING:Xst:646 - Signal > is assigned but never used. Found 16-bit subtractor for signal . Summary: inferred 1 Adder/Subtractor(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/Ruder/Code/invPendel/Version3/upcnt5.vhd". WARNING:Xst:1778 - Inout is assigned but never used. Found 5-bit up counter for signal . Summary: inferred 1 Counter(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/Ruder/Code/invPendel/Version3/simpleSPI.vhd". WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:1780 - Signal is never used or assigned. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 00000001. WARNING:Xst:646 - Signal is assigned but never used. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 11 | | Transitions | 21 | | Inputs | 5 | | Outputs | 4 | | Clock | clk (rising_edge) | | Power Up State | idle | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found 16-bit register for signal . Found 24-bit register for signal . Found 1-bit register for signal . Found 5-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal >. Summary: inferred 1 Finite State Machine(s). inferred 1 Counter(s). inferred 44 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/Ruder/Code/invPendel/Version3/stateMachine.vhd". Register > equivalent to has been removed Found finite state machine for signal . ----------------------------------------------------------------------- | States | 11 | | Transitions | 41 | | Inputs | 8 | | Outputs | 12 | | Clock | clk (rising_edge) | | Power Up State | st_standby | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found 4x1-bit ROM for signal . Found 4x1-bit ROM for signal . Found 4-bit register for signal . Found 8-bit register for signal . Found 8-bit register for signal . Found 8-bit register for signal . Found 8-bit register for signal . Found 2-bit register for signal >. Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 8-bit addsub for signal <$n0038>. Found 8-bit addsub for signal <$n0039>. Found 8-bit addsub for signal <$n0040>. Found 8-bit addsub for signal <$n0041>. Found 4-bit register for signal . Found 4-bit register for signal . Found 4-bit 4-to-1 multiplexer for signal . Found 8-bit 4-to-1 multiplexer for signal . Found 8-bit 4-to-1 multiplexer for signal . Found 8-bit 4-to-1 multiplexer for signal . Found 2-bit register for signal . Found 2-bit 4-to-1 multiplexer for signal . Found 8-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 2 ROM(s). inferred 59 D-type flip-flop(s). inferred 4 Adder/Subtractor(s). inferred 30 Multiplexer(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/Ruder/Code/invPendel/Version3/dispSigned16.vhd". WARNING:Xst:646 - Signal > is assigned but never used. Found 32-bit adder for signal <$n0002>. Found 32-bit adder for signal <$n0006>. Found 32-bit subtractor for signal <$n0009> created at line 55. Found 32-bit adder for signal <$n0010>. Found 32-bit adder for signal <$n0015>. Found 32-bit subtractor for signal <$n0016> created at line 54. Found 32-bit adder for signal <$n0017>. Found 32-bit adder for signal <$n0018>. Found 32-bit subtractor for signal <$n0023> created at line 56. Found 32-bit adder for signal <$n0024>. Found 32-bit adder for signal <$n0025>. Found 32-bit adder for signal <$n0026>. Found 32-bit subtractor for signal <$n0027> created at line 56. Found 32-bit adder for signal <$n0028>. Found 32-bit comparator less for signal <$n0043> created at line 49. Found 32-bit subtractor for signal . Summary: inferred 15 Adder/Subtractor(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/Ruder/Code/invPendel/Version3/pwm.vhd". Found 1-bit register for signal . Found 24-bit comparator greatequal for signal <$n0002> created at line 34. Found 12-bit up counter for signal . Summary: inferred 1 Counter(s). inferred 1 D-type flip-flop(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/Ruder/Code/invPendel/Version3/zRegler.vhd". WARNING:Xst:646 - Signal > is assigned but never used. Found 16x8-bit multiplier for signal <$n0000> created at line 26. Found 16x8-bit multiplier for signal <$n0001> created at line 26. Found 27-bit adder for signal <$n0002> created at line 26. Found 19x8-bit multiplier for signal <$n0003> created at line 26. Found 27-bit adder for signal <$n0004>. Found 19x8-bit multiplier for signal <$n0005> created at line 26. Found 27-bit adder for signal <$n0006>. Found 54-bit subtractor for signal . Summary: inferred 4 Adder/Subtractor(s). inferred 4 Multiplier(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/Ruder/Code/invPendel/Version3/kalib.vhd". WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. Found 16-bit register for signal . Found 16-bit register for signal . Found 19-bit adder for signal <$n0000> created at line 34. Found 19-bit adder for signal <$n0001>. Found 19-bit adder for signal <$n0003> created at line 42. Found 19-bit adder for signal <$n0004>. Found 19-bit adder for signal <$n0006>. Found 19-bit adder for signal <$n0007>. Found 19-bit adder for signal <$n0008>. Found 19-bit adder for signal <$n0009>. Found 19-bit adder for signal <$n0010>. Found 19-bit adder for signal <$n0011>. Found 19-bit adder for signal <$n0012>. Found 19-bit adder for signal <$n0013>. Found 19-bit adder for signal <$n0014>. Found 19-bit adder for signal <$n0015>. Found 19-bit adder for signal <$n0016>. Found 19-bit adder for signal <$n0017>. Found 19-bit adder for signal <$n0018>. Found 19-bit adder for signal <$n0019>. Summary: inferred 32 D-type flip-flop(s). inferred 18 Adder/Subtractor(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/Ruder/Code/invPendel/Version3/diff2.vhd". WARNING:Xst:646 - Signal > is assigned but never used. Found 19-bit register for signal . Found 16-bit register for signal . Found 19-bit adder for signal <$n0002> created at line 42. Found 19-bit adder for signal <$n0003> created at line 46. Found 19x19-bit multiplier for signal <$n0004> created at line 49. Found 19-bit adder for signal <$n0005>. Found 19-bit adder for signal <$n0006>. Found 19-bit adder for signal <$n0007>. Found 19-bit adder for signal <$n0008>. Found 19-bit adder for signal <$n0009>. Found 19-bit adder for signal <$n0010>. Found 19-bit adder for signal <$n0011>. Found 19-bit adder for signal <$n0012>. Found 19-bit adder for signal <$n0013>. Found 19-bit adder for signal <$n0014>. Found 19-bit adder for signal <$n0015>. Found 19-bit adder for signal <$n0016>. Found 19-bit subtractor for signal <$n0017> created at line 49. Found 1-bit register for signal . Found 3-bit up counter for signal . Found 19-bit register for signal . Found 19-bit register for signal . Found 38-bit register for signal . Found 19-bit register for signal . Found 16-bit register for signal . Found 304-bit register for signal . INFO:Xst:738 - HDL ADVISOR - 304 flip-flops were inferred for signal . You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time. Summary: inferred 1 Counter(s). inferred 451 D-type flip-flop(s). inferred 15 Adder/Subtractor(s). inferred 1 Multiplier(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/Ruder/Code/invPendel/Version3/spiController.vhd". Found 4x1-bit ROM for signal . Found 9-bit up counter for signal . Found 16-bit register for signal . Found 16-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 ROM(s). inferred 1 Counter(s). inferred 33 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/Ruder/Code/invPendel/Version3/dcm1.vhd". Unit synthesized. Synthesizing Unit . Related source file is "C:/Ruder/Code/invPendel/Version3/invPendel.vhd". WARNING:Xst:1780 - Signal is never used or assigned. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0000000000000000. WARNING:Xst:1780 - Signal is never used or assigned. WARNING:Xst:646 - Signal > is assigned but never used. Found 16-bit adder for signal <$n0001> created at line 151. Found 16-bit adder for signal <$n0002>. Found 16-bit adder for signal <$n0004> created at line 152. Found 16-bit adder for signal <$n0005>. Found 16-bit adder for signal <$n0007>. Found 16-bit adder for signal <$n0008>. Found 16-bit 16-to-1 multiplexer for signal . Found 16-bit subtractor for signal . Found 16-bit subtractor for signal . Summary: inferred 8 Adder/Subtractor(s). inferred 16 Multiplexer(s). Unit synthesized. INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing. ========================================================================= HDL Synthesis Report Macro Statistics # ROMs : 11 16x4-bit ROM : 4 16x8-bit ROM : 4 4x1-bit ROM : 3 # Multipliers : 6 16x8-bit multiplier : 2 19x19-bit multiplier : 2 19x8-bit multiplier : 2 # Adders/Subtractors : 98 16-bit adder : 6 16-bit subtractor : 3 19-bit adder : 64 19-bit subtractor : 2 27-bit adder : 3 32-bit adder : 10 32-bit subtractor : 5 54-bit subtractor : 1 8-bit addsub : 4 # Counters : 13 10-bit up counter : 4 12-bit up counter : 2 2-bit up counter : 1 3-bit up counter : 2 5-bit up counter : 3 9-bit up counter : 1 # Registers : 97 1-bit register : 33 16-bit register : 11 19-bit register : 40 2-bit register : 2 24-bit register : 1 38-bit register : 2 4-bit register : 3 8-bit register : 5 # Comparators : 2 24-bit comparator greatequal : 1 32-bit comparator less : 1 # Multiplexers : 11 1-bit 4-to-1 multiplexer : 6 16-bit 16-to-1 multiplexer : 1 8-bit 4-to-1 multiplexer : 4 # Decoders : 1 1-of-4 decoder : 1 # Xors : 4 1-bit xor2 : 4 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Analyzing FSM for best encoding. Optimizing FSM on signal with one-hot encoding. --------------------------- State | Encoding --------------------------- st_standby | 00000000001 st_kalib | 00000000010 st_active | 00000000100 st_k1 | 00000001000 st_k2 | 00000010000 st_k3 | 00000100000 st_k4 | 00001000000 st_k1a | 00010000000 st_k2a | 00100000000 st_k3a | 01000000000 st_k4a | 10000000000 --------------------------- Analyzing FSM for best encoding. Optimizing FSM on signal with sequential encoding. ------------------------- State | Encoding ------------------------- idle | 0000 assert_ssn1 | 0001 assert_ssn2 | 0010 unmask_sck | 0011 xfer_bit | 0100 assert_done | 0101 chk_start | 0110 mask_sck | 0111 hold_ssn1 | 1000 hold_ssn2 | 1001 negate_ssn | 1010 ------------------------- Synthesizing (advanced) Unit . Found pipelined multiplier on signal <_n0004>: - 1 pipeline level(s) found in a register connected to the multiplier macro output. Pushing register(s) into the multiplier macro. Found 2-bit shift register for signal <0>>. Found 2-bit shift register for signal <1>>. Found 2-bit shift register for signal <2>>. Found 2-bit shift register for signal <3>>. Found 2-bit shift register for signal <4>>. Found 2-bit shift register for signal <5>>. Found 2-bit shift register for signal <6>>. Found 2-bit shift register for signal <7>>. Found 2-bit shift register for signal <8>>. Found 2-bit shift register for signal <9>>. Found 2-bit shift register for signal <10>>. Found 2-bit shift register for signal <11>>. Found 2-bit shift register for signal <12>>. Found 2-bit shift register for signal <13>>. Found 2-bit shift register for signal <14>>. Found 2-bit shift register for signal <15>>. Found 2-bit shift register for signal <16>>. Found 2-bit shift register for signal <17>>. Found 2-bit shift register for signal <18>>. Found 2-bit shift register for signal >. Found 2-bit shift register for signal >. Found 2-bit shift register for signal >. Found 2-bit shift register for signal >. Found 2-bit shift register for signal >. Found 2-bit shift register for signal >. Found 2-bit shift register for signal >. Found 2-bit shift register for signal >. Found 2-bit shift register for signal >. Found 2-bit shift register for signal >. Found 2-bit shift register for signal >. Found 2-bit shift register for signal >. Found 2-bit shift register for signal >. Found 2-bit shift register for signal >. Found 2-bit shift register for signal >. Found 2-bit shift register for signal >. Unit synthesized (advanced). Synthesizing (advanced) Unit . Found 5-bit shift register for signal >. Unit synthesized (advanced). WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch <2> is unconnected in block . WARNING:Xst:1291 - FF/Latch <3> is unconnected in block . WARNING:Xst:1291 - FF/Latch <4> is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . ========================================================================= Advanced HDL Synthesis Report Macro Statistics # FSMs : 2 # ROMs : 11 16x4-bit ROM : 4 16x8-bit ROM : 4 4x1-bit ROM : 3 # Multipliers : 6 16x8-bit multiplier : 2 19x19-bit registered multiplier : 2 19x8-bit multiplier : 2 # Adders/Subtractors : 98 16-bit adder : 6 16-bit subtractor : 3 19-bit adder : 64 19-bit subtractor : 2 27-bit adder : 3 32-bit adder : 10 32-bit subtractor : 5 54-bit subtractor : 1 8-bit addsub : 4 # Counters : 13 10-bit up counter : 4 12-bit up counter : 2 2-bit up counter : 1 3-bit up counter : 2 5-bit up counter : 3 9-bit up counter : 1 # Registers : 525 Flip-Flops : 525 # Shift Registers : 71 2-bit shift register : 70 5-bit shift register : 1 # Comparators : 2 24-bit comparator greatequal : 1 32-bit comparator less : 1 # Multiplexers : 11 1-bit 4-to-1 multiplexer : 6 16-bit 16-to-1 multiplexer : 1 8-bit 4-to-1 multiplexer : 4 # Decoders : 1 1-of-4 decoder : 1 # Xors : 4 1-bit xor2 : 4 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . Loading device for application Rf_Device from file '3s200.nph' in environment C:\Programme\Embedded\XILINX\ISE. INFO:Xst:2146 - In block , Shifter > > > > are equivalent, Xst will keep only >. WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block invPendel, actual ratio is 89. FlipFlop STATE_MACHINE1/k2_7 has been replicated 2 time(s) FlipFlop STATE_MACHINE1/k4_7 has been replicated 2 time(s) ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s200ft256-4 Number of Slices: 1742 out of 1920 90% Number of Slice Flip Flops: 1020 out of 3840 26% Number of 4 input LUTs: 2260 out of 3840 58% Number used as logic: 2195 Number used as Shift registers: 65 Number of bonded IOBs: 33 out of 173 19% IOB Flip Flops: 1 Number of MULT18X18s: 4 out of 12 33% Number of GCLKs: 8 out of 8 100% Number of DCM_ADVs: 1 out of 4 25% ========================================================================= TIMING REPORT Clock Information: ------------------ ----------------------------------------------------------------------+---------------------------------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | ----------------------------------------------------------------------+---------------------------------------------------+-------+ STATE_MACHINE1/kalib_links1 | BUFG | 32 | STATE_MACHINE1/kalib_rechts | NONE | 32 | clk | DCM1_1/DCM_INST:CLK0 | 130 | clk | DCM1_1/DCM_INST:CLKFX | 13 | clk | DCM1_1/DCM_INST:CLKDV | 34 | SPICONTROLER1/done_help1(SPICONTROLER1/SIMPLESPI1/spi_state_Out11:O) | BUFG(*)(SPICONTROLER1/phase) | 33 | done1(SPICONTROLER1/done1:O) | BUFG(*)(DIFF2_2/z_queue_15_13) | 552 | DIFF2_2/compute1 | BUFG | 108 | DIFF2_1/compute1 | BUFG | 108 | sclk_OBUF(SPICONTROLER1/SIMPLESPI1/sck_out1:O) | NONE(*)(SPICONTROLER1/SIMPLESPI1/data_int_6) | 23 | SPICONTROLER1/SIMPLESPI1/rcv_load(SPICONTROLER1/SIMPLESPI1/_n002222:O)| NONE(*)(SPICONTROLER1/SIMPLESPI1/data_help_14) | 16 | SPICONTROLER1/SIMPLESPI1/sck_1(SPICONTROLER1/SIMPLESPI1/sck_11:O) | NONE(*)(SPICONTROLER1/SIMPLESPI1/BIT_CNTR/q_int_2)| 5 | ----------------------------------------------------------------------+---------------------------------------------------+-------+ (*) These 5 clock signal(s) are generated by combinatorial logic, and XST is not able to identify which are the primary clock signals. Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic. INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. Timing Summary: --------------- Speed Grade: -4 Minimum period: 156.270ns (Maximum Frequency: 6.399MHz) Minimum input arrival time before clock: 1.825ns Maximum output required time after clock: 92.158ns Maximum combinational path delay: No path found ========================================================================= Process "Synthesize" completed successfully Started : "Translate". Command Line: ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc invPendel.ucf -p xc3s200-ft256-4 invPendel.ngc invPendel.ngd Reading NGO file 'C:/Ruder/Code/invPendel/Version3/invPendel.ngc' ... Applying constraints in "invPendel.ucf" to the design... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Writing NGD file "invPendel.ngd" ... Writing NGDBUILD log file "invPendel.bld"... NGDBUILD done. Process "Translate" completed successfully Started : "Map". Using target part "3s200ft256-4". Mapping design into LUTs... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 3 Logic Utilization: Number of Slice Flip Flops: 1,005 out of 3,840 26% Number of 4 input LUTs: 2,363 out of 3,840 61% Logic Distribution: Number of occupied Slices: 1,687 out of 1,920 87% Number of Slices containing only related logic: 1,687 out of 1,687 100% Number of Slices containing unrelated logic: 0 out of 1,687 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number 4 input LUTs: 2,486 out of 3,840 64% Number used as logic: 2,363 Number used as a route-thru: 58 Number used as Shift registers: 65 Number of bonded IOBs: 33 out of 173 19% IOB Flip Flops: 16 Number of MULT18X18s: 4 out of 12 33% Number of GCLKs: 8 out of 8 100% Number of DCMs: 1 out of 4 25% Total equivalent gate count for design: 60,613 Additional JTAG gate count for IOBs: 1,584 Peak Memory Usage: 155 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "invPendel_map.mrp" for details. Process "Map" completed successfully Started : "Place & Route". Constraints file: invPendel.pcf. WARNING:Par:331 - You are using an evaluation version of Xilinx Software. In 12 days, this program will not operate. For more information about this product, please refer to the Evaluation Agreement, which was shipped to you along with the Evaluation CDs. To purchase an annual license for this software, please contact your local Field Applications Engineer (FAE) or salesperson. If you have any questions, or if we can assist in any way, please send an email to: eval@xilinx.com Thank You! Loading device for application Rf_Device from file '3s200.nph' in environment C:\Programme\Embedded\XILINX\ISE. "invPendel" is an NCD, version 3.1, device xc3s200, package ft256, speed -4 Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". For a balance between the fastest runtime and best performance, set the effort level to "med". Device speed data version: "PRODUCTION 1.37 2005-11-04". Device Utilization Summary: Number of BUFGMUXs 8 out of 8 100% Number of DCMs 1 out of 4 25% Number of External IOBs 33 out of 173 19% Number of LOCed IOBs 33 out of 33 100% Number of MULT18X18s 4 out of 12 33% Number of Slices 1687 out of 1920 87% Number of SLICEMs 33 out of 960 3% Overall effort level (-ol): Standard Placer effort level (-pl): High Placer cost table entry (-t): 1 Router effort level (-rl): Standard Starting Placer Phase 1.1 Phase 1.1 (Checksum:98dad4) REAL time: 6 secs Phase 2.31 Phase 2.31 (Checksum:1312cfe) REAL time: 6 secs Phase 3.2 ...... ... Phase 3.2 (Checksum:1c9c37d) REAL time: 8 secs Phase 4.8 .................................................................................. ............ ............................................................................................................................................................................ .............. ........ ................................................... Phase 4.8 (Checksum:bfa187) REAL time: 20 secs Phase 5.5 Phase 5.5 (Checksum:2faf07b) REAL time: 20 secs Phase 6.18 Phase 6.18 (Checksum:39386fa) REAL time: 22 secs Phase 7.5 Phase 7.5 (Checksum:42c1d79) REAL time: 22 secs Writing design to file invPendel.ncd Total REAL time to Placer completion: 23 secs Total CPU time to Placer completion: 20 secs Starting Router Phase 1: 8779 unrouted; REAL time: 23 secs Phase 2: 7805 unrouted; REAL time: 23 secs Phase 3: 3285 unrouted; REAL time: 24 secs Phase 4: 3285 unrouted; (25093) REAL time: 25 secs Phase 5: 3327 unrouted; (0) REAL time: 25 secs Phase 6: 0 unrouted; (5909) REAL time: 31 secs Phase 7: 0 unrouted; (5909) REAL time: 31 secs Phase 8: 0 unrouted; (5909) REAL time: 39 secs WARNING:Route:447 - CLK Net:sclk_OBUF may have excessive skew because 1 NON-CLK pins failed to route using a CLK template. WARNING:Route:447 - CLK Net:SPICONTROLER1/SIMPLESPI1/sck_1 may have excessive skew because 2 NON-CLK pins failed to route using a CLK template. Total REAL time to Router completion: 39 secs Total CPU time to Router completion: 36 secs Generating "PAR" statistics. ************************** Generating Clock Report ************************** +---------------------+--------------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +---------------------+--------------+------+------+------------+-------------+ | DIFF2_2/compute | BUFGMUX0| No | 49 | 0.003 | 1.013 | +---------------------+--------------+------+------+------------+-------------+ | clkSPI | BUFGMUX1| No | 22 | 0.001 | 1.011 | +---------------------+--------------+------+------+------------+-------------+ | DIFF2_1/compute | BUFGMUX6| No | 48 | 0.001 | 1.011 | +---------------------+--------------+------+------+------------+-------------+ | clkPWM | BUFGMUX3| No | 7 | 0.039 | 1.050 | +---------------------+--------------+------+------+------------+-------------+ | clk0 | BUFGMUX2| No | 105 | 0.042 | 1.052 | +---------------------+--------------+------+------+------------+-------------+ | done | BUFGMUX4| No | 262 | 0.006 | 1.016 | +---------------------+--------------+------+------+------------+-------------+ |STATE_MACHINE1/kalib | | | | | | | _links | BUFGMUX5| No | 16 | 0.002 | 1.012 | +---------------------+--------------+------+------+------------+-------------+ |SPICONTROLER1/done_h | | | | | | | elp | BUFGMUX7| No | 17 | 0.003 | 1.014 | +---------------------+--------------+------+------+------------+-------------+ | sclk_OBUF | Local| | 13 | 0.218 | 2.704 | +---------------------+--------------+------+------+------------+-------------+ |SPICONTROLER1/SIMPLE | | | | | | | SPI1/sck_1 | Local| | 5 | 0.000 | 1.522 | +---------------------+--------------+------+------+------------+-------------+ |STATE_MACHINE1/kalib | | | | | | | _rechts | Local| | 16 | 0.351 | 2.760 | +---------------------+--------------+------+------+------------+-------------+ |SPICONTROLER1/SIMPLE | | | | | | | SPI1/rcv_load | Local| | 8 | 0.177 | 2.028 | +---------------------+--------------+------+------+------------+-------------+ * Net Skew is the difference between the minimum and maximum routing only delays for the net. Note this is different from Clock Skew which is reported in TRCE timing report. Clock Skew is the difference between the minimum and maximum path delays which includes logic delays. Timing Score: 0 Asterisk (*) preceding a constraint indicates it was not met. This may be due to a setup or hold violation. ------------------------------------------------------------------------------------------------------ Constraint | Requested | Actual | Logic | Absolute |Number of | | | Levels | Slack |errors ------------------------------------------------------------------------------------------------------ Autotimespec constraint for clock net DIF | N/A | 14.902ns | 18 | N/A | N/A F2_2/compute | | | | | ------------------------------------------------------------------------------------------------------ Autotimespec constraint for clock net clk | N/A | 9.172ns | 1 | N/A | N/A SPI | | | | | ------------------------------------------------------------------------------------------------------ Autotimespec constraint for clock net DIF | N/A | 16.628ns | 17 | N/A | N/A F2_1/compute | | | | | ------------------------------------------------------------------------------------------------------ Autotimespec constraint for clock net clk | N/A | 6.829ns | 6 | N/A | N/A PWM | | | | | ------------------------------------------------------------------------------------------------------ Autotimespec constraint for clock net scl | N/A | 3.581ns | 0 | N/A | N/A k_OBUF | | | | | ------------------------------------------------------------------------------------------------------ Autotimespec constraint for clock net clk | N/A | 7.057ns | 3 | N/A | N/A 0 | | | | | ------------------------------------------------------------------------------------------------------ Autotimespec constraint for clock net don | N/A | 3.523ns | 0 | N/A | N/A e | | | | | ------------------------------------------------------------------------------------------------------ Autotimespec constraint for clock net SPI | N/A | 6.258ns | 0 | N/A | N/A CONTROLER1/done_help | | | | | ------------------------------------------------------------------------------------------------------ Autotimespec constraint for clock net SPI | N/A | 2.824ns | 2 | N/A | N/A CONTROLER1/SIMPLESPI1/sck_1 | | | | | ------------------------------------------------------------------------------------------------------ All constraints were met. INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value. Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 42 secs Total CPU time to PAR completion: 38 secs Peak Memory Usage: 159 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Number of error messages: 0 Number of warning messages: 3 Number of info messages: 1 Writing design to file invPendel.ncd PAR done! Process "Place & Route" completed successfully Started : "Generate Post-Place & Route Static Timing". Loading device for application Rf_Device from file '3s200.nph' in environment C:\Programme\Embedded\XILINX\ISE. "invPendel" is an NCD, version 3.1, device xc3s200, package ft256, speed -4 Analysis completed Thu Jan 04 15:20:32 2007 -------------------------------------------------------------------------------- Generating Report ... Number of warnings: 0 Total time: 6 secs Process "Generate Post-Place & Route Static Timing" completed successfully Started : "Generate Programming File". WARNING:PhysDesignRules:372 - Gated clock. Clock net sclk_OBUF is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net SPICONTROLER1/SIMPLESPI1/sck_1 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net SPICONTROLER1/SIMPLESPI1/rcv_load is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM comp DCM1_1/DCM_INST/DCM1_1/DCM_INST, consult the device Interactive Data Sheet. Process "Generate Programming File" completed successfully