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-- Company: 
-- Engineer: 
-- 
-- Create Date: 13.07.2014 21:47:53
-- Design Name: 
-- Module Name: Mehrfachaddierer - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Mehrfachaddierer is
    generic (Breite:integer:=32);
    Port ( AV : in STD_LOGIC_VECTOR (Breite-1 downto 0);
           BV : in STD_LOGIC_VECTOR (Breite-1 downto 0);
           ErgebnisV : out STD_LOGIC_VECTOR (Breite-1 downto 0);
           Carry : out STD_LOGIC);
end Mehrfachaddierer;

architecture Behavioral of Mehrfachaddierer is
    signal CV:STD_LOGIC_VECTOR(Breite downto 0):=(others=>'0');
    component Addierer is
    Port ( A : in STD_LOGIC;
           B : in STD_LOGIC;
           C : in STD_LOGIC;
           Summe : out STD_LOGIC;
           Carry : out STD_LOGIC);
    end component;
begin
        L: for i in 0 to Breite-1 generate
            A: Addierer port map(AV(i),BV(i),CV(i),ErgebnisV(i),CV(i+1));
        end generate;
        Carry<=CV(Breite);
end Behavioral;