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-- Company: 
-- Engineer: 
-- 
-- Create Date: 13.07.2014 21:43:20
-- Design Name: 
-- Module Name: Addierer - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Addierer is
    Port ( A : in STD_LOGIC;
           B : in STD_LOGIC;
           C : in STD_LOGIC;
           Summe : out STD_LOGIC;
           Carry : out STD_LOGIC);
end Addierer;

architecture Behavioral of Addierer is
begin
    Carry<=(A and B) or (A and C) or (B and C) after 30ns;
    Summe<=A xor B xor C after 20ns;
end Behavioral;