Started : "Synthesize - XST". Running xst... Command Line: xst -intstyle ise -ifn "test.xst" -ofn "test.syr" Reading design: test.prj ========================================================================= * HDL Parsing * ========================================================================= Parsing VHDL file "test.vhd" into library work Parsing entity . Parsing architecture of entity . ========================================================================= * HDL Elaboration * ========================================================================= Elaborating entity (architecture ) from library . ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "test.vhd". Register equivalent to has been removed Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 1 1-bit register : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= ========================================================================= Advanced HDL Synthesis Report Macro Statistics # Registers : 1 Flip-Flops : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block test, actual ratio is 0. FlipFlop out1 has been replicated 1 time(s) to handle iob=true attribute. Final Macro Processing ... ========================================================================= Final Register Report Macro Statistics # Registers : 2 Flip-Flops : 2 ========================================================================= ========================================================================= * Partition Report * ========================================================================= Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- ========================================================================= * Design Summary * ========================================================================= Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clk | BUFGP | 2 | -----------------------------------+------------------------+-------+ Asynchronous Control Signals Information: ---------------------------------------- No asynchronous control signals found in this design Timing Summary: --------------- Speed Grade: -2 Minimum period: No path found Minimum input arrival time before clock: 3.448ns Maximum output required time after clock: 4.118ns Maximum combinational path delay: No path found ========================================================================= Process "Synthesize - XST" completed successfully