Version 4 SHEET 1 1708 3400 WIRE -336 -800 -336 -816 WIRE -336 -800 -432 -800 WIRE -432 -768 -432 -800 WIRE -608 -624 -896 -624 WIRE -432 -624 -432 -688 WIRE -432 -624 -528 -624 WIRE -336 -624 -432 -624 WIRE -176 -624 -336 -624 WIRE -336 -592 -336 -624 WIRE -784 -544 -816 -544 WIRE -672 -544 -720 -544 WIRE -1056 -480 -1152 -480 WIRE -816 -480 -816 -544 WIRE -816 -480 -976 -480 WIRE -336 -480 -336 -512 WIRE -224 -480 -336 -480 WIRE -336 -464 -336 -480 WIRE -896 -432 -896 -624 WIRE -848 -432 -896 -432 WIRE -816 -432 -816 -480 WIRE -784 -432 -816 -432 WIRE -672 -416 -672 -544 WIRE -672 -416 -720 -416 WIRE -512 -416 -672 -416 WIRE -400 -416 -432 -416 WIRE -848 -400 -848 -432 WIRE -784 -400 -848 -400 WIRE -336 -192 -336 -368 FLAG -1360 -560 VCC FLAG -1360 -480 0 FLAG -752 -448 VCC FLAG -752 -384 0 FLAG -336 -192 0 FLAG -896 -352 0 FLAG -176 -624 Vm FLAG -1152 -480 VREF FLAG -336 -816 0 FLAG -224 -480 Emitter FLAG 368 -608 Vm FLAG 368 -464 0 FLAG -1312 -256 0 FLAG -1312 -336 VREF FLAG 208 -128 Vm FLAG 208 -48 0 SYMBOL voltage -1360 -576 R0 SYMATTR InstName V2 SYMATTR Value 5 SYMBOL res -624 -608 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R3 SYMATTR Value 68k SYMBOL res -880 -336 R180 WINDOW 0 36 76 Left 2 WINDOW 3 36 40 Left 2 SYMATTR InstName R4 SYMATTR Value 33k SYMBOL current -432 -768 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName I1 SYMATTR Value PULSE(0 250m 1ms 50m) SYMBOL npn -400 -464 R0 SYMATTR InstName Q1 SYMATTR Value 2N3055 SYMBOL res -416 -432 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R5 SYMATTR Value 470 SYMBOL Opamps\\opamp2 -752 -480 R0 SYMATTR InstName U1 SYMATTR Value MCP601 SYMBOL res -352 -608 R0 SYMATTR InstName R10 SYMATTR Value .1 SYMBOL cap 352 -528 R0 SYMATTR InstName C3 SYMATTR Value 1000µF SYMATTR SpiceLine Rser={R_STEP} SYMBOL res -960 -496 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R8 SYMATTR Value 1k SYMBOL cap -720 -560 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C4 SYMATTR Value 22n SYMBOL voltage -1312 -352 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V1 SYMATTR Value 2 SYMBOL res 352 -624 R0 SYMATTR InstName ESR SYMATTR Value 1 SYMBOL current 208 -128 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName I2 SYMATTR Value PULSE(0 120m 300m 100u 100u 50m) TEXT -1816 88 Left 2 !.tran 500m startup TEXT -616 -512 Left 2 ;Shuntregler TEXT -1016 -160 Left 2 !.step param CURR LIST 10m 100m 250m 450m TEXT 784 -696 Left 2 ;Parameter: ESR (in der Schaltung Widerstand verwenden); stabil ab 1E\nR8 / C4 : Zeitkonstante verringert die Verstärkung für hohe Frequenzen; TEXT -3808 -1768 Left 2 !.SUBCKT MCP601 1 2 3 4 5\n* | | | | |\n* | | | | Output\n* | | | Negative Supply\n* | | Positive Supply\n* | Inverting Input\n* Non-inverting Input\n*\n********************************************************************************\n* Software License Agreement *\n* *\n* The software supplied herewith by Microchip Technology Incorporated (the *\n* 'Company') is intended and supplied to you, the Company's customer, for use *\n* soley and exclusively on Microchip products. *\n* *\n* The software is owned by the Company and/or its supplier, and is protected *\n* under applicable copyright laws. All rights are reserved. Any use in *\n* violation of the foregoing restrictions may subject the user to criminal *\n* sanctions under applicable laws, as well as to civil liability for the *\n* breach of the terms and conditions of this license. *\n* *\n* THIS SOFTWARE IS PROVIDED IN AN 'AS IS' CONDITION. NO WARRANTIES, WHETHER *\n* EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED *\n* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO *\n* THIS SOFTWARE. THE COMPANY SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR *\n* SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. *\n********************************************************************************\n*\n* The following op-amps are covered by this model:\n* MCP601,MCP602,MCP603,MCP604\n*\n* Revision History:\n* REV A: 30-Jun-99, BCB (created model)\n* REV B: 10-Jul-99, BCB (corrected DC Iq)\n* REV C: 30-Nov-99, BCB (".subckt" on first line, moved L, W to model)\n* REV D: 17-Jul-02, KEB (improved model)\n* REV E: 27-Aug-06, HNV (added over temperature, improved output stage, \n* fixed overdrive recovery time)\n* (MC_RQ, 27-Aug-06, Level 1.17) \n* \n* Recommendations:\n* Use PSPICE (other simulators may require translation)\n* For a quick, effective design, use a combination of: data sheet\n* specs, bench testing, and simulations with this macromodel\n* For high impedance circuits, set GMIN=100F in the .OPTIONS statement\n*\n* Supported:\n* Typical performance for temperature range (-40 to 125) degrees Celsius\n* DC, AC, Transient, and Noise analyses.\n* Most specs, including: offsets, DC PSRR, DC CMRR, input impedance,\n* open loop gain, voltage ranges, supply current, ... , etc.\n* Temperature effects for Ibias, Iquiescent, Iout short circuit \n* current, Vsat on both rails, Slew Rate vs. Temp and P.S.\n*\n* Not Supported:\n* Chip select (MCP603)\n* Some Variation in specs vs. Power Supply Voltage\n* Monte Carlo (Vos, Ib),Process variation \n* Distortion (detailed non-linear behavior)\n* Behavior outside normal operating region\n*\n* Input Stage \nV10 3 10 1.00 \nR10 10 11 771K \nR11 10 12 771K \nG10 10 11 10 11 129U \nG11 10 12 10 12 129U \nC11 11 12 2P\nC12 1 0 6P \nE12 71 14 POLY(4) 20 0 21 0 26 0 27 0 1.00M 15 15 1 1 \nG12 1 0 62 0 1m \nM12 11 14 15 15 NMI\nG13 1 2 62 0 .015m \nM14 12 2 15 15 NMI \nG14 2 0 62 0 1m \nC14 2 0 6P \nI15 15 4 40.0U \nV16 16 4 -300M \nGD16 16 1 TABLE {V(16,1)} ((-100,-1p)(0,0)(1m,1u)(2m,10m)) \nV13 3 13 1.2 \nGD13 2 13 TABLE {V(2,13)} ((-100,-1p)(0,0)(1m,1u)(2m,10m)) \nR71 1 0 20.0E12 \nR72 2 0 20.0E12 \nR73 1 2 20.0E12 \nI80 1 2 400F \n* \n* Noise, PSRR, and CMRR \nI20 21 20 423U \nD20 20 0 DN1 \nD21 0 21 DN1 \nG26 0 26 POLY(2) 3 0 4 0 0.00 -50.1U -63.0U \nR26 26 0 1\nE271 275 0 1 0 1\nE272 276 0 2 0 1\nR271 275 271 12k\nR272 276 272 12k\nR273 271 0 1k\nR274 272 0 1k\nC271 275 271 8.5p\nC272 276 272 8.5p\nG27 0 27 POLY(2) 271 0 272 0 -555U 100U 100U \nR27 27 0 1 \n* \n* Open Loop Gain, Slew Rate \nG30 0 30 12 11 1 \nR30 30 0 1.00K \nI31 0 31 DC 109.7 \nR31 31 0 1 TC=-3.87M,-2.12U \nGD31 30 0 TABLE {V(30,31)} ((-100,-1n)(0,0)(1m,0.1)(2m,2)) \nI32 32 0 DC 120 \nR32 32 0 1 TC=-3.71M,-4.74U \nGD32 0 30 TABLE {V(30,32)} ((-2m,2)(-1m,0.1)(0,0)(100,-1n)) \nG33 0 33 30 0 1m \nR33 33 0 1K \nG34 0 34 33 0 334M \nR34 34 0 1K \nC34 34 0 17.4U \nG37 0 37 34 0 1m \nR37 37 0 1K \nC37 37 0 27P\nG38 0 38 37 0 1m \nR38 39 0 1K \nL38 38 39 44U\nE38 35 0 38 0 1 \nG35 33 0 TABLE {V(35,3)} ((-1,-1n)(0,0)(5,1n))(6,1)) \nG36 33 0 TABLE {V(35,4)} ((-5,-1)((-4,-1n)(0,0)(1,1n)) \n* \n* Output Stage \nR80 50 0 100MEG \nG50 0 50 57 96 2 \nR58 57 96 0.50 \nR57 57 0 500 \nC58 5 0 2.00P \nG57 0 57 POLY(3) 3 0 4 0 35 0 0 0.2M 0.22M 2.00M \nGD55 55 57 TABLE {V(55,57)} ((-2m,-1)(-1m,-1m)(0,0)(10,1n)) \nGD56 57 56 TABLE {V(57,56)} ((-2m,-1)(-1m,-1m)(0,0)(10,1n)) \nE55 55 0 POLY(2) 3 0 51 0 -2.4M 1 -58.8M \nE56 56 0 POLY(2) 4 0 52 0 1.7M 1 -32.3M \nR51 51 0 1k \nR52 52 0 1k \nGD51 50 51 TABLE {V(50,51)} ((-10,-1n)(0,0)(1m,1m)(2m,1)) \nGD52 50 52 TABLE {V(50,52)} ((-2m,-1)(-1m,-1m)(0,0)(10,1n)) \nG53 3 0 POLY(1) 51 0 -40.0U 1M \nG54 0 4 POLY(1) 52 0 -40.0U -1M \n* \n* Current Limit \nG99 96 5 99 0 1 \nR98 0 98 1 TC=-4.33M,9.53U \nG97 0 98 TABLE { V(96,5) } ((-11.0,-15.0M)(-1.00M,-14.8M)(0,0)(1.00M,14.8M)(11.0,15.0M)) \nE97 99 0 VALUE { V(98)*((V(3)-V(4))*233M + 183M)} \nD98 4 5 DESD \nD99 5 3 DESD \n* \n* Temperature / Voltage Sensitive IQuiscent \nR61 0 61 1 TC=-3.20M,-8.90U \nG61 3 4 61 0 1 \nG60 0 61 TABLE {V(3, 4)} \n+ ((0,0)(900M,0.1U)(1.1,10.0U)(1.3,40.0U) \n+ (1.6,60.0U)(2.5,200U)(5.5,220U)) \n* \n* Temperature Sensistive offset voltage \nI73 0 70 DC 1uA \nR74 0 70 1 TC=2.5 \nE75 1 71 70 0 1 \n* \n* Temp Sensistive IBias \nI62 0 62 DC 1uA \nR62 0 62 REXP 99U \n* Extra Lines for LTSPICE\nCD13 2 13 10P\nCD16 16 1 10P\nCD31 30 31 100P\nCD32 30 32 100P\nCD55 57 55 100P\nCD56 57 56 100P\nCD51 51 50 100P\nCD52 52 50 100P\nCD98 0 98 10P \n* \n* Models \n.MODEL NMI NMOS(L=2.00U W=42.0U KP=20.0U LEVEL=1 ) \n.MODEL DESD D N=1 IS=1.00E-15 \n.MODEL DN1 D IS=1P KF=0.35F AF=1 \n.MODEL REXP RES TCE= 9.1 \n.ENDS MCP601