----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------------------------------------------------------
entity speicher is
Port ( 
		clk 		: in  STD_LOGIC;								-- clock 48MHz
		reset 		: in  STD_LOGIC;								-- asynch reset
		controll_frame 	: in  STD_LOGIC;								-- controll_frame
		feedback_frame 	: in  STD_LOGIC;								-- feedback_frame
		daten_reg 	: in  STD_LOGIC_VECTOR (133 downto 0);						-- data from MAX in shift reg.
		reset_count 	: in  STD_LOGIC;								-- Impuls to save Data
		M14 		: out  STD_LOGIC								-- M14 RS232 output
		);
end speicher;
----------------------------------------------------------------------------------
architecture Behavioral of speicher is
----------------------------------------------------------------------------------
component Transmitter is 
port (
		reset      : in  std_logic;                    	-- asynch reset
      clk        : in  std_logic;                     		-- clock 48 MHz
      data       : in  std_logic_vector(7 downto 0);  		-- data input
      data_ready : in  std_logic;                     		-- control signal
      tx_ready   : out std_logic;                     		-- transmitter ready for new data
      tx         : out std_logic				-- transmitter output
		);  																	
end component;																
----------------------------------------------------------------------------------
component ram is															
port (																		
		clka			: IN  std_logic;				-- clock
		dina			: IN  std_logic_VECTOR(55 downto 0);		-- data IN
		addra			: IN  std_logic_VECTOR(12 downto 0);		-- addres
		wea			: IN  std_logic_VECTOR (0 downto 0);		-- if data IN then 1 
		douta			: OUT std_logic_VECTOR(55 downto 0)		-- data OUT 
		);
end component;
----------------------------------------------------------------------------------
signal sr 			: STD_LOGIC_VECTOR(55 downto 0);
signal sr_2			: STD_LOGIC_VECTOR(55 downto 0);
signal zaehler		: STD_LOGIC_VECTOR (2 downto 0);
signal data			: STD_LOGIC_VECTOR (7 downto 0);
signal count 		: STD_LOGIC_VECTOR(12 downto 0):= "0000000000000";
signal count_2    : STD_LOGIC_VECTOR(12 downto 0):= "0000000000000";
signal addra		: STD_LOGIC_VECTOR(12 downto 0):= "0000000000000";
signal data_ready	: STD_LOGIC := '0';
signal tx_ready   : STD_LOGIC;
signal wea			: std_logic_VECTOR(0 downto 0);
signal reset_count_not : STD_LOGIC;
begin
----------------------------------------------------------------------------------
Transmitter_1 : Transmitter port map(
reset 		=> reset,
clk			=> clk,
data			=> data,
data_ready 	=> data_ready,
tx_ready		=> tx_ready,
tx				=> M14
);
----------------------------------------------------------------------------------
Ram_1 : ram port map(
clka			=> clk,
dina			=> sr,
addra			=> addra,
wea			=> wea,
douta			=> sr_2
);