-- -- FSM for control of -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity FSM is Port ( clk : in std_logic; -- system clock, ~1 MHz start : in std_logic; -- start pulse dig0 : in std_logic_vector(6 downto 0); -- data for digit 0 dig1 : in std_logic_vector(6 downto 0); -- data for digit 1 dig2 : in std_logic_vector(6 downto 0); -- data for digit 2 dig3 : in std_logic_vector(6 downto 0); -- data for digit 3 data : out std_logic_vector(6 downto 0); -- data bus adr : out std_logic_vector(1 downto 0); -- address bus n_wr : out std_logic; -- write strobe n_clr : out std_logic; -- display clear n_blank : out std_logic); -- display blank end FSM; architecture Behavioral of FSM is type t_data_array is array (3 downto 0) of std_logic_vector(7 downto 0); type t_adr_array is array (3 downto 0) of std_logic_vector(3 downto 0); type t_state is (stop, write, pulse, pulse_end); constant data_array: t_data_array:=(x"48", x"65", x"6C", x"70"); constant adr_array: t_adr_array:=(x"3" , x"2" , x"1" , x"0"); signal state : t_state; signal cnt: std_logic_vector(1 downto 0); signal mux: std_logic_vector(6 downto 0); begin -- MUX mux: process (dig0, dig1, dig2, dig3, cnt) begin case cnt is when "00" => mux <= dig0; when "01" => mux <= dig1; when "10" => mux <= dig2; when "11" => mux <= dig3; when others => mux <= 0; end case; end process mux; -- FSM -- -- when start is '1', a sequence of 4 bytes is written to the LED display -- process(clk) variable index: integer; begin if rising_edge(clk) then index := conv_integer(cnt); case state is when stop => n_wr <= '1'; n_clr <= '1'; n_blank <= '1'; cnt <= "00"; if start = '1' then state <= write; end if; when write => data <= mux; adr <= cnt; cnt <= cnt +1; state <= pulse; when pulse => n_wr <= '0'; state <= pulse_end; when pulse_end => n_wr <= '1'; if cnt =3 then state <= stop; else state <= write; end if; when others => state <= stop; end case; end if; end process; end Behavioral;