-- Display the Left Score ( Using Std_Logic_Vectors instead of integers ) if ( clk = '1' and clk'event) then if ((pixel >= "0001000" ) and ( pixel <= "0001011" )) and ((line >= "000000" ) and (line <= "000111" )) then number_address(6 downto 3) <= CONV_STD_LOGIC_VECTOR(lscore,4); elsif ((pixel >= "01000000" ) and ( pixel <= "01000011" )) and ((line >= "000000" ) and (line <= "000111" )) then number_address(6 downto 3) <= CONV_STD_LOGIC_VECTOR(rscore,4); else number_address(6 downto 3) <= "0001"; end if; end if; if ((pixel >= "0001000") and (pixel <= "0001011" )) and ((line >= "000000") and (line <= "000111" ) ) then case pixel( 1 downto 0 ) is when "00" => if ( number_data(3) = '1' ) then next_COLOR <= "10"; end if; when "01" => if ( number_data(2) = '1' ) then next_COLOR <= "10"; end if; when "10" => if ( number_data(1) = '1' ) then next_COLOR <= "10"; end if; when "11" => if ( number_data(0) = '1' ) then next_COLOR <= "10"; end if; when others => NULL; end case; end if; -- Display the Right Score if ((pixel >= "01000000") and (pixel <= "01000011" )) and ((line >= "000000") and (line <= "000111")) then case pixel(1 downto 0) is when "00" => if (number_data(3) = '1') then next_COLOR <= "10"; end if; when "01" => if (number_data(2) = '1') then next_COLOR <= "10"; end if; when "10" => if (number_data(1) = '1') then next_COLOR <= "10"; end if; when "11" => if (number_data(0) = '1') then next_COLOR <= "10"; end if; when others => NULL; end case; end if; __________________________________ Die auszugebenen Zahlen stehen in einer anderen Datei folgendermaßen ------------------------------------------------------------------ -- Copyright (c) 1995-2005 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------ -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version : 8.1i -- \ \ Application : -- / / Filename : testram.vhd -- /___/ /\ Timestamp : 9/20/2005 11:04:05 -- \ \ / \ -- \___\/\___\ -- -- -- This Entity contains an array of data elements representing VGA display patterns library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity testram is Port ( address: in std_logic_vector(6 downto 0); data: out std_logic_vector(3 downto 0) ); end testram; architecture behavioral of testram is type mem_array is array (0 to 79) of std_logic_vector(3 downto 0); constant characters: mem_array := ( -- 0 "0000", "1111", "1001", "1001", "1001", "1001", "1001", "1111", -- 1 "0000", "0001", "0001", "0001", "0001", "0001", "0001", "0001", -- 2 "0000", "1111", "0001", "0001", "1111", "1000", "1000", "1111", -- 3 "0000", "1111", "0001", "0001", "1111", "0001", "0001", "1111", -- 4 "0000", "1001", "1001", "1001", "1111", "0001", "0001", "0001", -- 5 "0000", "1111", "1000", "1000", "1111", "0001", "0001", "1111", -- 6 "0000", "1111", "1000", "1000", "1111", "1001", "1001", "1111", -- 7 "0000", "1111", "0001", "0001", "0001", "0001", "0001", "0001", -- 8 "0000", "1111", "1001", "1001", "1111", "1001", "1001", "1111", -- 9 "0000", "1111", "1001", "1001", "1111", "0001", "0001", "0001" ); begin process (address ) begin data <= characters(conv_integer(address)); end process; end behavioral;