library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SimulatorPod is
		generic( n : integer := 22);
		Port (USER_CLOCK: in  std_logic;  								-- 40 MHz Clock, 25ns
			  Reset_in : in std_logic;										-- Reset Eingang
			  FPGA_Status : out std_logic;								-- FPGA Status zum Prozessor
			  Pulse_nullen : in std_logic;								-- FPGA Eingang zum Pulse Nullen
			  PulsOutPin : out std_logic;									-- Puls Ausgang 1
			  TriggerOutPin: out std_logic;								-- Puls Ausgang 2 für den Trigger
           Pulseenable : in std_logic;									-- Pulseaktivierung 
			  SwitchOutPin: out std_logic;								-- Puls Ausgang für den Switch
			  Switchenable : in std_logic;								-- Pulseaktivierung für Switch
			  StbyOprIn : in std_logic;									-- Aktivierung HVPS von Prozessor
			  StbyOprOut : out std_logic;									-- Aktivierung HVPS zum OpAmp
			  GPIO_LED1: out std_logic;									-- LED 1
			  GPIO_LED2: out std_logic;								   -- LED 2
			  sclk      : in std_logic;									--	Dateneingang SPI Clock 
           CS        : in std_logic;									--	Dateneingang SPI Chip Select
           MOSI  :  in STD_LOGIC											--	Dateneingang SPI MOSI
			  );
end SimulatorPod;

architecture Pulsausgabe of SimulatorPod is
	type PulseTyp is array(0 to 15) of std_logic_vector(11 downto 0);					-- 12 Pulse Speicher mit max. 12Bit für 102,4µs
		signal Pulse : PulseTyp := (x"000", x"000", x"000", x"000", x"000", x"000", x"000", x"000", x"000", x"000", x"000", x"000", x"000", x"000", x"000", x"000");

	type PulsePauseTyp is array(0 to 15) of std_logic_vector(16 downto 0);			-- 12 Pulsepausen mit max. 17Bit für 3,2ms
		signal PulsePause : PulsePauseTyp := ("00000000000000000","00000000000000000","00000000000000000","00000000000000000","00000000000000000","00000000000000000","00000000000000000","00000000000000000","00000000000000000","00000000000000000","00000000000000000","00000000000000000","00000000000000000","00000000000000000","00000000000000000","00000000000000000");
	
	signal PulseZaehler: std_logic_vector(11 downto 0):= (others=>'0');				-- 12 Bit Pulsezähler
	signal PulsePausenZaehler: std_logic_vector(16 downto 0) := (others=>'0');		-- 16 Bit Pulsepausenzähler
	
	signal TriggerPulsZeit: std_logic_vector(2 downto 0);									-- Triggerpuls Zähler
	
	signal PulseOut: std_logic;																	-- Pulse Ausgang
	signal TriggerPulseOut: std_logic;															-- Pulse Trigger Ausgang
	signal SwitchOut: std_logic;																	-- Switch Ausgang
	signal Operate: std_logic;																		-- StBy-Operate
	signal FPGAgeladen: std_logic;																-- Pulse im FPGA geladen

	signal Pulsenr : integer range 0 to 15 := 0;												-- 16 Pulse können abgefahren werden
   
	signal DST     : STD_LOGIC_VECTOR (n-1 downto 0):=(others=>'0');					-- SPI Empfangswort
   signal sclkSR  : STD_LOGIC_VECTOR (1 downto 0):=(others=>'0');						-- SPI
   signal sclkCS  : STD_LOGIC_VECTOR (1 downto 0):=(others=>'0');						-- SPI
	
	signal LEDCounter: std_logic_vector(24 downto 0); 										-- Zähler für LED blinken
	signal LEDout: std_logic;																		-- Ausgang für LED12
	signal LEDout2: std_logic;																		-- Ausgang für LED34

begin
	Prescaler: process(USER_CLOCK)
	begin
		-- Pulseausgabe
		-- Wenn Clock-Flanke ansteigt
		if rising_edge(USER_CLOCK) then		
		  if Pulseenable = '1' then
			-- Pulse ausgeben
			If PulseZaehler < Pulse(Pulsenr) then
				PulseZaehler <= PulseZaehler + 1;
				pulseout <= '1';
			else
				PulsePausenZaehler <= PulsePausenZaehler + 1;
				pulseout <= '0';			
			end if;			

			-- PulsePause
			if PulsePausenZaehler >= PulsePause(Pulsenr) then
				PulseZaehler <= (others => '0');
				PulsePausenZaehler <= (others => '0');
				TriggerPulsZeit <= (others => '0');				
				Pulsenr <= Pulsenr +1;
			end if;

			--- Triggerausgang setzen
			if Pulsenr = 0 and Pulse(0) > "000" and TriggerPulsZeit < 4 then
				TriggerPulseOut <= '1';
				TriggerPulsZeit <= TriggerPulsZeit +1;
			else
				TriggerPulseOut <= '0';
			end if;		

			--- Es können nur Pulse 0-16 gesetzt werden, beim 17. also zurück zur 0		
			--- Ist ein neuer Puls leer, dann wieder mit Pulse 0 beginnen		
			if Pulsenr >= 16 or Pulse(Pulsenr) = "000" then 
				Pulsenr <= 0;
				TriggerPulsZeit <= (others => '0');
			end if;
			
			--- keine Pulse geladen, dann den FPGA Status auf 0 setzen
			if Pulse(0) = "000000000000" then
				FPGAgeladen <= '0';
			else
				FPGAgeladen <= '1';
			end if;

		 else
			pulseout <= '0';
			TriggerPulseOut <= '0';
       end if;

		-- Switchout
		 if switchenable = '1' then
			switchout <= pulseout;
		 else
			switchout <= '0';
		 end if;

		-- Standby Operate
		 if StbyOprIn = '1' then
			Operate <= '1';
		 else
			Operate <= '0';
		 end if;


		end if;
		
		
		--- SPI Routine  
		-- Wenn Clock-Flanke ansteigt
		if rising_edge(USER_CLOCK) then  
       if Pulseenable = '0' then		
			sclkSR  <= sclkSR(0) & sclk;
			sclkCS  <= sclkCS(0) & CS;			
			if CS = '0' then
				if sclkSR="01" then                 		-- steigende Flanke am SCLK
					DST  <= DST(n-2 downto 0) & MOSI; 		-- Daten ins SR einlesen
				end if;
			else
				if sclkCS="01" then                 		-- steigende Flanke am CS
					if DST(n-1) = '1' then
					--- Pulsedaten
						Pulsenr <= to_integer(unsigned(DST(n-2 downto n-5)));
						Pulse(Pulsenr) <= DST(n-11 downto 0)  ;	
					else
					--- Pulsepausedaten
						pulsenr <= to_integer(unsigned(DST(n-2 downto n-5)));
						PulsePause(Pulsenr) <= DST(n-6 downto 0)  ;					
					end if;										
				end if;
			end if;
		 end if;

		 -- RESET gedrückt oder Pulse_nullen Signal
		 if Reset_in = '0' or Pulse_nullen = '0' then
				for i in 0 to 15 loop
					Pulse(i) <= "000000000000";
					PuLsePause(i) <= "00000000000000000";			
				end loop;
		
			pulseout <= '0';
			TriggerPulseOut <= '0';
			switchout <= '0';
			Operate <= '0';		
		 end if;

		end if;
		

		--Sekunden-LED hochzählen oder Resetten
		-- Wenn Clock-Flanke ansteigt
		if rising_edge(USER_CLOCK) then  
			if Reset_in <= '0' then
				LEDout <= '0';
				LEDout2 <= '0';
			else	
				if LEDCounter < "1001100010010110100000000" then
					LEDCounter <= LEDCounter + 1;
				else
					LEDout <= not LEDout;
					LEDCounter <= (others => '0');
				end if;
				if Pulseenable = '1' then		
					LEDout2 <= not LEDout;
				else
					LEDout2 <= '0';		
				end if;			
			end if;
		end if;
		
	end process Prescaler;
	
	-- Pins für PulseOut setzen
	PulsOutPin <= not pulseout;
	TriggerOutPin <= not TriggerPulseOut;
	SwitchOutPin <= not switchout;
	
	--Pins für Status setzen
	StbyOprOut <= not Operate;
	FPGA_Status <= FPGAgeladen;
	
	-- Pins für LEDs setzen
	GPIO_LED1 <= LEDout;
	GPIO_LED2 <= LEDout2;


end Pulsausgabe;