use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity test is generic (COUNT_WIDTH:integer := 4); Port ( clock : in STD_LOGIC; reset : in STD_LOGIC; count_direction : in STD_LOGIC; count : inout STD_LOGIC_VECTOR(COUNT_WIDTH-1 downto 0)); end test; architecture Behavioral of test is begin CountProcess: process (clock, reset) begin if reset='1' then count <= (others => '0'); elsif clock='1' and clock'event then if count_direction = '1' then count <= count + 1; else count <= count - 1; end if; end if; end process; end Behavioral;