"C:\lscc\iCEcube2.2015.04\sbt_backend\bin\win32\opt\synpwrap\synpwrap.exe" -prj "RamTest_syn.prj" -log "RamTest_Implmnt/RamTest.srr" Copyright (C) 1992-2014 Lattice Semiconductor Corporation. All rights reserved. ==contents of RamTest_Implmnt/RamTest.srr #Build: Synplify Pro J-2015.03L, Build 030R, Apr 20 2015 #install: C:\lscc\iCEcube2.2015.04\synpbase #OS: Windows 7 6.1 #Hostname: IN1565 #Implementation: RamTest_Implmnt Synopsys HDL Compiler, version comp201503p1, Build 058R, built Apr 20 2015 @N|Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Synopsys Verilog Compiler, version comp201503p1, Build 058R, built Apr 20 2015 @N|Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. @I::"C:\lscc\iCEcube2.2015.04\synpbase\lib\generic\sb_ice40.v" @I::"C:\lscc\iCEcube2.2015.04\synpbase\lib\vlog\hypermods.v" @I::"C:\lscc\iCEcube2.2015.04\synpbase\lib\vlog\umr_capim.v" @I::"C:\lscc\iCEcube2.2015.04\synpbase\lib\vlog\scemi_objects.v" @I::"C:\lscc\iCEcube2.2015.04\synpbase\lib\vlog\scemi_pipes.svh" @I::"C:\Users\wagnersn\Desktop\VerilogRamTest\RamTest\main - Kopie.v" Verilog syntax check successful! Compiler output is up to date. No re-compile necessary Selecting top level module ram_access @N: CG364 :"C:\Users\wagnersn\Desktop\VerilogRamTest\RamTest\main - Kopie.v":84:7:84:13|Synthesizing module fillRam @N: CG364 :"C:\Users\wagnersn\Desktop\VerilogRamTest\RamTest\main - Kopie.v":2:7:2:16|Synthesizing module ram_access @W: CS263 :"C:\Users\wagnersn\Desktop\VerilogRamTest\RamTest\main - Kopie.v":47:11:47:17|Port-width mismatch for port counter. Formal has width 25, Actual 8 @W: CG360 :"C:\Users\wagnersn\Desktop\VerilogRamTest\RamTest\main - Kopie.v":14:6:14:13|No assignment to wire newclock @W: CG360 :"C:\Users\wagnersn\Desktop\VerilogRamTest\RamTest\main - Kopie.v":17:6:17:13|No assignment to wire fiforclk @W: CG360 :"C:\Users\wagnersn\Desktop\VerilogRamTest\RamTest\main - Kopie.v":18:12:18:19|No assignment to wire fifodout @W: CG360 :"C:\Users\wagnersn\Desktop\VerilogRamTest\RamTest\main - Kopie.v":20:6:20:13|No assignment to wire fifowclk At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Oct 06 14:23:18 2015 ###########################################################] Synopsys Netlist Linker, version comp201503p1, Build 058R, built Apr 20 2015 @N|Running in 64-bit mode @N: NF107 :"C:\Users\wagnersn\Desktop\VerilogRamTest\RamTest\main - Kopie.v":2:7:2:16|Selected library: work cell: ram_access view verilog as top level @N: NF107 :"C:\Users\wagnersn\Desktop\VerilogRamTest\RamTest\main - Kopie.v":2:7:2:16|Selected library: work cell: ram_access view verilog as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Oct 06 14:23:18 2015 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Oct 06 14:23:18 2015 ###########################################################] Synopsys Netlist Linker, version comp201503p1, Build 058R, built Apr 20 2015 @N|Running in 64-bit mode File C:\Users\wagnersn\Desktop\VerilogRamTest\RamTest\RamTest_Implmnt\synwork\RamTest_comp.srs changed - recompiling @N: NF107 :"C:\Users\wagnersn\Desktop\VerilogRamTest\RamTest\main - Kopie.v":2:7:2:16|Selected library: work cell: ram_access view verilog as top level @N: NF107 :"C:\Users\wagnersn\Desktop\VerilogRamTest\RamTest\main - Kopie.v":2:7:2:16|Selected library: work cell: ram_access view verilog as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Oct 06 14:23:20 2015 ###########################################################] Pre-mapping Report Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1178R, Built Apr 22 2015 10:50:52 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03L Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) Reading constraint file: C:\Users\wagnersn\Desktop\VerilogRamTest\RamTest\timingconstraint.sdc @L: C:\Users\wagnersn\Desktop\VerilogRamTest\RamTest\RamTest_Implmnt\RamTest_scck.rpt Printing clock summary report in "C:\Users\wagnersn\Desktop\VerilogRamTest\RamTest\RamTest_Implmnt\RamTest_scck.rpt" file @N: MF248 |Running in 64-bit mode. @N: MF666 |Clock conversion enabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) ICG Latch Removal Summary: Number of ICG latches removed: 0 Number of ICG latches not removed: 0 syn_allowed_resources : blockrams=16 set on top level netlist ram_access Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 132MB) @S |Clock Summary ***************** Start Requested Requested Clock Clock Clock Frequency Period Type Group ------------------------------------------------------------------------- CLK_3P3_MHZ 3.3 MHz 303.000 declared default_clkgroup ========================================================================= Finished Pre Mapping Phase. @N: BN225 |Writing default property annotation file C:\Users\wagnersn\Desktop\VerilogRamTest\RamTest\RamTest_Implmnt\RamTest.sap. Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 132MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Oct 06 14:23:20 2015 ###########################################################] Map & Optimize Report Synopsys Lattice Technology Mapper, Version maplat, Build 1178R, Built Apr 22 2015 10:50:52 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03L Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) @N: MF248 |Running in 64-bit mode. @N: MF666 |Clock conversion enabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 132MB) Available hyper_sources - for debug and ip models None Found @N: MT204 |Auto Constrain mode is disabled because clocks are defined in the SDC file CLK_3P3_MHZ Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 132MB) @N: BN362 :"c:\users\wagnersn\desktop\verilogramtest\ramtest\main - kopie.v":90:1:90:6|Removing sequential instance led in hierarchy view:work.fillRam(verilog) because there are no references to its outputs @A: BN291 :"c:\users\wagnersn\desktop\verilogramtest\ramtest\main - kopie.v":90:1:90:6|Boundary register led packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @N: BN362 :"c:\users\wagnersn\desktop\verilogramtest\ramtest\main - kopie.v":90:1:90:6|Removing sequential instance counter[24] in hierarchy view:work.fillRam(verilog) because there are no references to its outputs @A: BN291 :"c:\users\wagnersn\desktop\verilogramtest\ramtest\main - kopie.v":90:1:90:6|Boundary register counter[24] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 132MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 132MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 132MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 132MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 132MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 132MB) Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 132MB) Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 132MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:00s 296.94ns 32 / 24 @N: FX1016 :"c:\users\wagnersn\desktop\verilogramtest\ramtest\main - kopie.v":3:7:3:17|SB_GB_IO inserted on the port CLK_3P3_MHZ. @N: FX1017 :|SB_GB inserted on the net testFill.counter_i[23]. Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 132MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 132MB) #### START OF CLOCK OPTIMIZATION REPORT #####[ 1 non-gated/non-generated clock tree(s) driving 24 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks ================================= Non-Gated/Non-Generated Clocks ================================= Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance -------------------------------------------------------------------------------------------------- @K:CKID0001 CLK_3P3_MHZ_ibuf_gb_io SB_GB_IO 24 testFill.counter[2] ================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 132MB) Writing Analyst data base C:\Users\wagnersn\Desktop\VerilogRamTest\RamTest\RamTest_Implmnt\synwork\RamTest_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 132MB) Writing EDIF Netlist and constraint files @N: BW103 |Synopsys Constraint File time units using default value of 1ns @N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF J-2015.03L Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB) Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 131MB peak: 133MB) Found clock CLK_3P3_MHZ with period 303.00ns @S |##### START OF TIMING REPORT #####[ # Timing Report written on Tue Oct 06 14:23:21 2015 # Top view: ram_access Requested Frequency: 3.3 MHz Wire load mode: top Paths requested: 5 Constraint File(s): C:\Users\wagnersn\Desktop\VerilogRamTest\RamTest\timingconstraint.sdc @N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: 294.277 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group -------------------------------------------------------------------------------------------------------------------- CLK_3P3_MHZ 3.3 MHz 114.6 MHz 303.000 8.723 294.277 declared default_clkgroup ==================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------ Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------ CLK_3P3_MHZ CLK_3P3_MHZ | 303.000 294.278 | No paths - | No paths - | No paths - ================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: CLK_3P3_MHZ ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------- testFill.counter[1] CLK_3P3_MHZ SB_DFFE Q fifodin[1] 0.796 294.277 testFill.counter[0] CLK_3P3_MHZ SB_DFFE Q fifodin[0] 0.796 294.471 testFill.counter[2] CLK_3P3_MHZ SB_DFFE Q fifodin[2] 0.796 294.478 testFill.counter[3] CLK_3P3_MHZ SB_DFFE Q fifodin[3] 0.796 294.678 testFill.counter[4] CLK_3P3_MHZ SB_DFFE Q fifodin[4] 0.796 294.878 testFill.counter[5] CLK_3P3_MHZ SB_DFFE Q fifodin[5] 0.796 295.077 testFill.counter[6] CLK_3P3_MHZ SB_DFFE Q fifodin[6] 0.796 295.277 testFill.counter[7] CLK_3P3_MHZ SB_DFFE Q fifodin[7] 0.796 295.478 testFill.counter[8] CLK_3P3_MHZ SB_DFFE Q counter[8] 0.796 295.678 testFill.counter[9] CLK_3P3_MHZ SB_DFFE Q counter[9] 0.796 295.878 ============================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------- testFill.counter[23] CLK_3P3_MHZ SB_DFF D counter 302.845 294.277 testFill.counter[22] CLK_3P3_MHZ SB_DFFE D counter_1[22] 302.845 294.478 testFill.counter[21] CLK_3P3_MHZ SB_DFFE D counter_1[21] 302.845 294.678 testFill.counter[20] CLK_3P3_MHZ SB_DFFE D counter_1[20] 302.845 294.878 testFill.counter[19] CLK_3P3_MHZ SB_DFFE D counter_1[19] 302.845 295.077 testFill.counter[18] CLK_3P3_MHZ SB_DFFE D counter_1[18] 302.845 295.277 testFill.counter[17] CLK_3P3_MHZ SB_DFFE D counter_1[17] 302.845 295.478 testFill.counter[16] CLK_3P3_MHZ SB_DFFE D counter_1[16] 302.845 295.678 testFill.counter[15] CLK_3P3_MHZ SB_DFFE D counter_1[15] 302.845 295.878 testFill.counter[14] CLK_3P3_MHZ SB_DFFE D counter_1[14] 302.845 296.077 =================================================================================================== Worst Path Information *********************** Path information for path number 1: Requested Period: 303.000 - Setup time: 0.155 + Clock delay at ending point: 0.000 (ideal) = Required time: 302.845 - Propagation time: 8.568 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 294.278 Number of logic level(s): 23 Starting point: testFill.counter[1] / Q Ending point: testFill.counter[23] / D The start point is clocked by CLK_3P3_MHZ [rising] on pin C The end point is clocked by CLK_3P3_MHZ [rising] on pin C Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------- testFill.counter[1] SB_DFFE Q Out 0.796 0.796 - fifodin[1] Net - - 0.834 - 3 testFill.counter_1_cry_1_c SB_CARRY I0 In - 1.630 - testFill.counter_1_cry_1_c SB_CARRY CO Out 0.380 2.009 - counter_1_cry_1 Net - - 0.014 - 2 testFill.counter_1_cry_2_c SB_CARRY CI In - 2.023 - testFill.counter_1_cry_2_c SB_CARRY CO Out 0.186 2.209 - counter_1_cry_2 Net - - 0.014 - 2 testFill.counter_1_cry_3_c SB_CARRY CI In - 2.223 - testFill.counter_1_cry_3_c SB_CARRY CO Out 0.186 2.409 - counter_1_cry_3 Net - - 0.014 - 2 testFill.counter_1_cry_4_c SB_CARRY CI In - 2.423 - testFill.counter_1_cry_4_c SB_CARRY CO Out 0.186 2.609 - counter_1_cry_4 Net - - 0.014 - 2 testFill.counter_1_cry_5_c SB_CARRY CI In - 2.623 - testFill.counter_1_cry_5_c SB_CARRY CO Out 0.186 2.809 - counter_1_cry_5 Net - - 0.014 - 2 testFill.counter_1_cry_6_c SB_CARRY CI In - 2.823 - testFill.counter_1_cry_6_c SB_CARRY CO Out 0.186 3.009 - counter_1_cry_6 Net - - 0.014 - 2 testFill.counter_1_cry_7_c SB_CARRY CI In - 3.023 - testFill.counter_1_cry_7_c SB_CARRY CO Out 0.186 3.209 - counter_1_cry_7 Net - - 0.014 - 2 testFill.counter_1_cry_8_c SB_CARRY CI In - 3.223 - testFill.counter_1_cry_8_c SB_CARRY CO Out 0.186 3.409 - counter_1_cry_8 Net - - 0.014 - 2 testFill.counter_1_cry_9_c SB_CARRY CI In - 3.423 - testFill.counter_1_cry_9_c SB_CARRY CO Out 0.186 3.609 - counter_1_cry_9 Net - - 0.014 - 2 testFill.counter_1_cry_10_c SB_CARRY CI In - 3.623 - testFill.counter_1_cry_10_c SB_CARRY CO Out 0.186 3.809 - counter_1_cry_10 Net - - 0.014 - 2 testFill.counter_1_cry_11_c SB_CARRY CI In - 3.823 - testFill.counter_1_cry_11_c SB_CARRY CO Out 0.186 4.009 - counter_1_cry_11 Net - - 0.014 - 2 testFill.counter_1_cry_12_c SB_CARRY CI In - 4.023 - testFill.counter_1_cry_12_c SB_CARRY CO Out 0.186 4.209 - counter_1_cry_12 Net - - 0.014 - 2 testFill.counter_1_cry_13_c SB_CARRY CI In - 4.223 - testFill.counter_1_cry_13_c SB_CARRY CO Out 0.186 4.409 - counter_1_cry_13 Net - - 0.014 - 2 testFill.counter_1_cry_14_c SB_CARRY CI In - 4.423 - testFill.counter_1_cry_14_c SB_CARRY CO Out 0.186 4.609 - counter_1_cry_14 Net - - 0.014 - 2 testFill.counter_1_cry_15_c SB_CARRY CI In - 4.623 - testFill.counter_1_cry_15_c SB_CARRY CO Out 0.186 4.809 - counter_1_cry_15 Net - - 0.014 - 2 testFill.counter_1_cry_16_c SB_CARRY CI In - 4.823 - testFill.counter_1_cry_16_c SB_CARRY CO Out 0.186 5.009 - counter_1_cry_16 Net - - 0.014 - 2 testFill.counter_1_cry_17_c SB_CARRY CI In - 5.023 - testFill.counter_1_cry_17_c SB_CARRY CO Out 0.186 5.209 - counter_1_cry_17 Net - - 0.014 - 2 testFill.counter_1_cry_18_c SB_CARRY CI In - 5.223 - testFill.counter_1_cry_18_c SB_CARRY CO Out 0.186 5.409 - counter_1_cry_18 Net - - 0.014 - 2 testFill.counter_1_cry_19_c SB_CARRY CI In - 5.423 - testFill.counter_1_cry_19_c SB_CARRY CO Out 0.186 5.609 - counter_1_cry_19 Net - - 0.014 - 2 testFill.counter_1_cry_20_c SB_CARRY CI In - 5.623 - testFill.counter_1_cry_20_c SB_CARRY CO Out 0.186 5.809 - counter_1_cry_20 Net - - 0.014 - 2 testFill.counter_1_cry_21_c SB_CARRY CI In - 5.823 - testFill.counter_1_cry_21_c SB_CARRY CO Out 0.186 6.009 - counter_1_cry_21 Net - - 0.014 - 2 testFill.counter_1_cry_22_c SB_CARRY CI In - 6.023 - testFill.counter_1_cry_22_c SB_CARRY CO Out 0.186 6.209 - counter_1_cry_22 Net - - 0.386 - 1 testFill.counter_RNO[23] SB_LUT4 I3 In - 6.595 - testFill.counter_RNO[23] SB_LUT4 O Out 0.465 7.061 - counter Net - - 1.507 - 1 testFill.counter[23] SB_DFF D In - 8.568 - ============================================================================================== Total path delay (propagation time + setup) of 8.722 is 5.701(65.4%) logic and 3.021(34.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 131MB peak: 133MB) Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 131MB peak: 133MB) --------------------------------------- Resource Usage Report for ram_access Mapping to part: ice40lp1kqn84 Cell usage: GND 1 use SB_CARRY 22 uses SB_DFF 1 use SB_DFFE 23 uses SB_GB 1 use VCC 1 use SB_LUT4 31 uses I/O ports: 8 I/O primitives: 8 SB_GB_IO 1 use SB_IO 7 uses I/O Register bits: 0 Register bits not including I/Os: 24 (1%) Total load per clock: CLK_3P3_MHZ: 1 Mapping Summary: Total LUTs: 31 (2%) Distribution of All Consumed LUTs = LUT4 Distribution of All Consumed Luts 31 = 31 Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 133MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Oct 06 14:23:21 2015 ###########################################################] Synthesis exit by 0. Current Implementation RamTest_Implmnt its sbt path: C:/Users/wagnersn/Desktop/VerilogRamTest/RamTest/RamTest_Implmnt\sbt Synthesis succeeded. Synthesis runtime 4 seconds