library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity test3 is
port (

	clk_i     : in  std_logic;
	reset_i   : in  std_logic;
	
	
	PWD_DN    : in std_logic;
	tx_sync_o : out std_logic;
	
	o: out std_logic_vector(5 downto 0));
	
	
end test3;

architecture test_arch of test3 is

signal Input0	:	std_logic_vector(5 downto 0);
signal Input1	:	std_logic_vector(5 downto 0);

 

begin
Input0 <= "000000";
Input1 <= "000000";

process(clk_i)
begin

if (clk_i'event and clk_i = '0') then -- fallende Taktflanke
		if reset_i = '0' then
		
O <= Input0 + Input1;


--else

--o <= "000000";
--o <= "101101";

end if;
end if;
end process;


end test_arch;