--------------------------- Logical States of DAC-Port. --------------------------- main() { DAC-Port state: BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7 --------------------------------------------------------- H H H H H H H H ltc1257_ll_init() { DAC-Port state: BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7 --------------------------------------------------------- L H H H H H H H } ltc1257_ll_write(21845) { DAC-Port state: # BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7 | Description -------------------------------------------------------------------------- 00 L H H H H H H H Loop entrance 00 L L H H H H H H DATA bit output 00 H L H H H H H H CLK pulled high & shifted 00 L L H H H H H H CLK pulled low 01 L L H H H H H H Loop entrance 01 L H H H H H H H DATA bit output 01 H H H H H H H H CLK pulled high & shifted 01 L H H H H H H H CLK pulled low 02 L H H H H H H H Loop entrance 02 L L H H H H H H DATA bit output 02 H L H H H H H H CLK pulled high & shifted 02 L L H H H H H H CLK pulled low 03 L L H H H H H H Loop entrance 03 L H H H H H H H DATA bit output 03 H H H H H H H H CLK pulled high & shifted 03 L H H H H H H H CLK pulled low 04 L H H H H H H H Loop entrance 04 L L H H H H H H DATA bit output 04 H L H H H H H H CLK pulled high & shifted 04 L L H H H H H H CLK pulled low 05 L L H H H H H H Loop entrance 05 L H H H H H H H DATA bit output 05 H H H H H H H H CLK pulled high & shifted 05 L H H H H H H H CLK pulled low 06 L H H H H H H H Loop entrance 06 L L H H H H H H DATA bit output 06 H L H H H H H H CLK pulled high & shifted 06 L L H H H H H H CLK pulled low 07 L L H H H H H H Loop entrance 07 L H H H H H H H DATA bit output 07 H H H H H H H H CLK pulled high & shifted 07 L H H H H H H H CLK pulled low 08 L H H H H H H H Loop entrance 08 L L H H H H H H DATA bit output 08 H L H H H H H H CLK pulled high & shifted 08 L L H H H H H H CLK pulled low 09 L L H H H H H H Loop entrance 09 L H H H H H H H DATA bit output 09 H H H H H H H H CLK pulled high & shifted 09 L H H H H H H H CLK pulled low 10 L H H H H H H H Loop entrance 10 L L H H H H H H DATA bit output 10 H L H H H H H H CLK pulled high & shifted 10 L L H H H H H H CLK pulled low 11 L L H H H H H H Loop entrance 11 L H H H H H H H DATA bit output 11 H H H H H H H H CLK pulled high & shifted 11 L H H H H H H H CLK pulled low L H H H H H H H CLK pulled low L H L H H H H H LOAD pulled low L H H H H H H H LOAD pulled high } }