00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012 #ifndef MCU_H
00013 #define MCU_H
00014
00015
00016
00017
00018
00019
00020 #if defined(__ICCAVR__) || defined(__IAR_SYSTEMS_ASM__)
00021
00022 SFR_B(PINA, 0x00)
00023 SFR_B(DDRA, 0x01)
00024 SFR_B(PORTA, 0x02)
00025
00026 SFR_B(PINB, 0x03)
00027 SFR_B(DDRB, 0x04)
00028 SFR_B(PORTB, 0x05)
00029
00030 SFR_B(PINC, 0x06)
00031 SFR_B(DDRC, 0x07)
00032 SFR_B(PORTC, 0x08)
00033
00034 SFR_B(PIND, 0x09)
00035 SFR_B(DDRD, 0x0A)
00036 SFR_B(PORTD, 0x0B)
00037
00038 SFR_B(PINE, 0x0C)
00039 SFR_B(DDRE, 0x0D)
00040 SFR_B(PORTE, 0x0E)
00041
00042 SFR_B(PINF, 0x0F)
00043 SFR_B(DDRF, 0x10)
00044 SFR_B(PORTF, 0x11)
00045
00046 SFR_B(PING, 0x12)
00047 SFR_B(DDRG, 0x13)
00048 SFR_B(PORTG, 0x14)
00049
00050 SFR_B(TIFR0, 0x15)
00051 SFR_B(TIFR1, 0x16)
00052 SFR_B(TIFR2, 0x17)
00053 SFR_B(TIFR3, 0x18)
00054
00055 SFR_B(EIFR, 0x1C)
00056 SFR_B(EIMSK, 0x1D)
00057
00058 SFR_B(GPIOR0, 0x1E)
00059
00060 SFR_B(EECR, 0x1F)
00061 SFR_B(EEDR, 0x20)
00062 SFR_W(EEAR, 0x21)
00063
00064 SFR_B(GTCCR, 0x23)
00065
00066 SFR_B(TCCR0A, 0x24)
00067 SFR_B(TCNT0, 0x26)
00068 SFR_B(OCR0A, 0x27)
00069
00070 SFR_B(TCCR0B, 0x25)
00071
00072
00073 SFR_B(GPIOR1, 0x2A)
00074 SFR_B(GPIOR2, 0x2B)
00075
00076 SFR_B(SPCR, 0x2C)
00077 SFR_B(SPSR, 0x2D)
00078 SFR_B(SPDR, 0x2E)
00079
00080 SFR_B(ACSR, 0x30)
00081
00082 SFR_B(OCDR, 0x31)
00083
00084 SFR_B(SMCR, 0x33)
00085 SFR_B(MCUSR, 0x34)
00086 SFR_B(MCUCR, 0x35)
00087
00088 SFR_B(SPMCSR, 0x37)
00089
00090 SFR_B(RAMPZ, 0x3B)
00091
00092 SFR_W(SP, 0x3D)
00093 SFR_B(SREG, 0x3F)
00094
00095 SFR_B(PLLCSR, 0x29);
00096
00097 SFR_B_EXT(WDTCR, 0x60)
00098 SFR_B_EXT(WDTCSR, 0x60)
00099 SFR_B_EXT(CLKPR, 0x61)
00100 SFR_B_EXT(OSCCAL, 0x66)
00101
00102 SFR_B_EXT(EICRA, 0x69)
00103 SFR_B_EXT(EICRB, 0x6A)
00104
00105 SFR_B_EXT(TIMSK0, 0x6E)
00106 SFR_B_EXT(TIMSK1, 0x6F)
00107 SFR_B_EXT(TIMSK2, 0x70)
00108 SFR_B_EXT(TIMSK3, 0x71)
00109
00110 SFR_B_EXT(XMCRA, 0x74)
00111 SFR_B_EXT(XMCRB, 0x75)
00112
00113 SFR_W_EXT(ADC, 0x78)
00114 SFR_B_EXT(ADCSRA, 0x7A)
00115 SFR_B_EXT(ADCSRB, 0x7B)
00116 SFR_B_EXT(ADMUX, 0x7C)
00117
00118 SFR_B_EXT(DIDR0, 0x7E)
00119 SFR_B_EXT(DIDR1, 0x7F)
00120
00121 SFR_B_EXT(TCCR1A, 0x80)
00122 SFR_B_EXT(TCCR1B, 0x81)
00123 SFR_B_EXT(TCCR1C, 0x82)
00124 SFR_W_EXT(TCNT1, 0x84)
00125 SFR_W_EXT(ICR1, 0x86)
00126 SFR_W_EXT(OCR1A, 0x88)
00127 SFR_W_EXT(OCR1B, 0x8A)
00128 SFR_W_EXT(OCR1C, 0x8C)
00129
00130 SFR_B_EXT(TCCR3A, 0x90)
00131 SFR_B_EXT(TCCR3B, 0x91)
00132 SFR_B_EXT(TCCR3C, 0x92)
00133 SFR_W_EXT(TCNT3, 0x94)
00134 SFR_W_EXT(ICR3, 0x96)
00135 SFR_W_EXT(OCR3A, 0x98)
00136 SFR_W_EXT(OCR3B, 0x9A)
00137 SFR_W_EXT(OCR3C, 0x9C)
00138
00139 SFR_B_EXT(TCCR2A, 0xB0)
00140 SFR_B_EXT(TCCR2B, 0xB1)
00141 SFR_B_EXT(TCNT2, 0xB2)
00142 SFR_B_EXT(OCR2A, 0xB3)
00143
00144 SFR_B_EXT(ASSR, 0xB6)
00145
00146 SFR_B_EXT(TWBR, 0xB8)
00147 SFR_B_EXT(TWSR, 0XB9)
00148 SFR_B_EXT(TWAR, 0xBA)
00149 SFR_B_EXT(TWDR, 0xBB)
00150 SFR_B_EXT(TWCR, 0xBC)
00151
00152
00153 SFR_B_EXT(UCSR1A, 0xC8)
00154 SFR_B_EXT(UCSR1B, 0xC9)
00155 SFR_B_EXT(UCSR1C, 0xCA)
00156 SFR_W_EXT(UBRR1, 0xCC)
00157
00158
00159 SFR_B_EXT(UDR1, 0xCE)
00160
00161 SFR_B_EXT(PCICR, 0x68)
00162 SFR_B_EXT(PCIFR, 0x3B)
00163 SFR_B_EXT(PCMSK0, 0x6B)
00164
00165
00166
00167
00168
00169 SFR_B_EXT(UHWCON, 0xD7);
00170
00171
00172
00173 SFR_B_EXT(USBCON, 0xD8);
00174 SFR_B_EXT(USBSTA, 0xD9);
00175 SFR_B_EXT(USBINT, 0xDA);
00176 SFR_B_EXT(UDPADDH, 0xDC);
00177 SFR_B_EXT(UDPADDL, 0xDB);
00178 SFR_B_EXT(OTGCON, 0xDD);
00179 SFR_B_EXT(OTGTCON, 0xF9);
00180 SFR_B_EXT(OTGIEN, 0xDE);
00181 SFR_B_EXT(OTGINT, 0xDF);
00182
00183
00184
00185 SFR_B_EXT(UDCON, 0xE0);
00186 SFR_B_EXT(UDINT, 0xE1);
00187 SFR_B_EXT(UDIEN, 0xE2);
00188 SFR_B_EXT(UDADDR, 0xE3);
00189 SFR_B_EXT(UDFNUMH, 0xE5);
00190 SFR_B_EXT(UDFNUML, 0xE4);
00191 SFR_B_EXT(UDMFN, 0xE6);
00192 SFR_B_EXT(UDTST, 0xE7);
00193
00194
00195
00196 SFR_B_EXT(UENUM, 0xE9);
00197 SFR_B_EXT(UERST, 0xEA);
00198 SFR_B_EXT(UECONX, 0xEB);
00199 SFR_B_EXT(UECFG0X, 0xEC);
00200 SFR_B_EXT(UECFG1X, 0xED);
00201 SFR_B_EXT(UESTA0X, 0xEE);
00202 SFR_B_EXT(UESTA1X, 0xEF);
00203 SFR_B_EXT(UEINTX, 0xE8);
00204 SFR_B_EXT(UEIENX, 0xF0);
00205 SFR_B_EXT(UEDATX, 0xF1);
00206 SFR_B_EXT(UEBCHX, 0xF3);
00207 SFR_B_EXT(UEBCLX, 0xF2);
00208 SFR_B_EXT(UEINT, 0xF4);
00209
00210
00211
00212 SFR_B_EXT(UHCON, 0x9E);
00213 SFR_B_EXT(UHINT, 0x9F);
00214 SFR_B_EXT(UHIEN, 0xA0);
00215 SFR_B_EXT(UHADDR, 0xA1);
00216 SFR_B_EXT(UHFNUMH, 0xA3);
00217 SFR_B_EXT(UHFNUML, 0xA2);
00218 SFR_B_EXT(UHFLEN, 0xA4);
00219
00220
00221
00222 SFR_B_EXT(UPNUM, 0xA7);
00223 SFR_B_EXT(UPRST, 0xA8);
00224 SFR_B_EXT(UPCONX, 0xA9);
00225 SFR_B_EXT(UPCFG0X, 0xAA);
00226 SFR_B_EXT(UPCFG1X, 0xAB);
00227 SFR_B_EXT(UPCFG2X, 0xAD);
00228 SFR_B_EXT(UPSTAX, 0xAC);
00229 SFR_B_EXT(UPINRQX, 0xA5);
00230 SFR_B_EXT(UPERRX, 0xF5);
00231 SFR_B_EXT(UPINTX, 0xA6);
00232 SFR_B_EXT(UPIENX, 0xAE);
00233 SFR_B_EXT(UPDATX, 0xAF);
00234 SFR_B_EXT(UPBCHX, 0xF7);
00235 SFR_B_EXT(UPBCLX, 0xF6);
00236 SFR_B_EXT(UPINT, 0xF8);
00237
00238
00239
00240
00241
00242
00243
00244 #define RESET_vect (0x00)
00245 #define INT0_vect (0x04)
00246 #define INT1_vect (0x08)
00247 #define INT2_vect (0x0C)
00248 #define INT3_vect (0x10)
00249 #define INT4_vect (0x14)
00250 #define INT5_vect (0x18)
00251 #define INT6_vect (0x1C)
00252 #define INT7_vect (0x20)
00253 #define PCINT0_vect (0x24)
00254 #define USB_GENERAL_vect (0x28)
00255 #define USB_ENDPOINT_PIPE_vect (0x2C)
00256 #define WDT_vect (0x30)
00257 #define TIMER2_COMPA_vect (0x34)
00258 #define TIMER2_COMPB_vect (0x38)
00259 #define TIMER2_OVF_vect (0x3C)
00260 #define TIMER1_CAPT_vect (0x40)
00261 #define TIMER1_COMPA_vect (0x44)
00262 #define TIMER1_COMPB_vect (0x48)
00263 #define TIMER1_COMPC_vect (0x4C)
00264 #define TIMER1_OVF_vect (0x50)
00265 #define TIMER0_COMPA_vect (0x54)
00266 #define TIMER0_COMPB_vect (0x58)
00267 #define TIMER0_OVF_vect (0x5C)
00268 #define SPI_STC_vect (0x60)
00269 #define USART1_RXC_vect (0x64)
00270 #define USART1_UDRE_vect (0x68)
00271 #define USART1_TXC_vect (0x6C)
00272 #define ANA_COMP_vect (0x70)
00273 #define ADC_vect (0x74)
00274 #define EE_RDY_vect (0x78)
00275 #define TIMER3_CAPT_vect (0x7C)
00276 #define TIMER3_COMPA_vect (0x80)
00277 #define TIMER3_COMPB_vect (0x84)
00278 #define TIMER3_COMPC_vect (0x88)
00279 #define TIMER3_OVF_vect (0x8C)
00280 #define TWI_vect (0x90)
00281 #define SPM_RDY_vect (0x94)
00282
00283 #endif
00284
00285 #ifdef __CODEVISIONAVR__
00286
00287 #define PINA (*(volatile unsigned char *)0x20)
00288 #define DDRA (*(volatile unsigned char *)0x21)
00289 #define PORTA (*(volatile unsigned char *)0x22)
00290
00291 #define PINB (*(volatile unsigned char *)0x23)
00292 #define DDRB (*(volatile unsigned char *)0x24)
00293 #define PORTB (*(volatile unsigned char *)0x25)
00294
00295 #define PINC (*(volatile unsigned char *)0x26)
00296 #define DDRC (*(volatile unsigned char *)0x27)
00297 #define PORTC (*(volatile unsigned char *)0x28)
00298
00299 #define PIND (*(volatile unsigned char *)0x29)
00300 #define DDRD (*(volatile unsigned char *)0x2A)
00301 #define PORTD (*(volatile unsigned char *)0x2B)
00302
00303 #define PINE (*(volatile unsigned char *)0x2C)
00304 #define DDRE (*(volatile unsigned char *)0x2D)
00305 #define PORTE (*(volatile unsigned char *)0x2E)
00306
00307 #define PINF (*(volatile unsigned char *)0x2F)
00308 #define DDRF (*(volatile unsigned char *)0x30)
00309 #define PORTF (*(volatile unsigned char *)0x31)
00310
00311 #define PING (*(volatile unsigned char *)0x32)
00312 #define DDRG (*(volatile unsigned char *)0x33)
00313 #define PORTG (*(volatile unsigned char *)0x34)
00314
00315 #define TIFR0 (*(volatile unsigned char *)0x35)
00316 #define TIFR1 (*(volatile unsigned char *)0x36)
00317 #define TIFR2 (*(volatile unsigned char *)0x37)
00318 #define TIFR3 (*(volatile unsigned char *)0x38)
00319
00320 #define EIFR (*(volatile unsigned char *)0x3C)
00321 #define EIMSK (*(volatile unsigned char *)0x3D)
00322
00323 #define GPIOR0 (*(volatile unsigned char *)0x3E)
00324
00325 #define EECR (*(volatile unsigned char *)0x3F)
00326 #define EEDR (*(volatile unsigned char *)0x40)
00327 #define EEAR (*(volatile unsigned int *)0x41)
00328
00329 #define GTCCR (*(volatile unsigned char *)0x43)
00330
00331 #define TCCR0A (*(volatile unsigned char *)0x44)
00332 #define TCNT0 (*(volatile unsigned char *)0x46)
00333 #define OCR0A (*(volatile unsigned char *)0x47)
00334
00335 #define GPIOR1 (*(volatile unsigned char *)0x4A)
00336 #define GPIOR2 (*(volatile unsigned char *)0x4B)
00337
00338 #define SPCR (*(volatile unsigned char *)0x4C)
00339 #define SPSR (*(volatile unsigned char *)0x4D)
00340 #define SPDR (*(volatile unsigned char *)0x4E)
00341
00342 #define ACSR (*(volatile unsigned char *)0x50)
00343
00344 #define OCDR (*(volatile unsigned char *)0x51)
00345
00346 #define SMCR (*(volatile unsigned char *)0x53)
00347 #define MCUSR (*(volatile unsigned char *)0x53)
00348 #define MCUCR (*(volatile unsigned char *)0x53)
00349
00350 #define SPMCSR (*(volatile unsigned char *)0x57)
00351
00352 #define RAMPZ (*(volatile unsigned char *)0x5B)
00353
00354 #define SP (*(volatile unsigned int *)0x5D)
00355 #define SREG (*(volatile unsigned char *)0x5F)
00356
00357 #define WDTCR (*(volatile unsigned char *)0x60)
00358 #define CLKPR (*(volatile unsigned char *)0x61)
00359 #define OSCCAL (*(volatile unsigned char *)0x66)
00360
00361 #define EICRA (*(volatile unsigned char *)0x69)
00362 #define EICRB (*(volatile unsigned char *)0x6A)
00363
00364 #define TIMSK0 (*(volatile unsigned char *)0x6E)
00365 #define TIMSK1 (*(volatile unsigned char *)0x6F)
00366 #define TIMSK2 (*(volatile unsigned char *)0x70)
00367 #define TIMSK3 (*(volatile unsigned char *)0x71)
00368
00369 #define XMCRA (*(volatile unsigned char *)0x74)
00370 #define XMCRB (*(volatile unsigned char *)0x75)
00371
00372 #define ADC (*(volatile unsigned int *)0x78)
00373 #define ADCSRA (*(volatile unsigned char *)0x7A)
00374 #define ADCSRB (*(volatile unsigned char *)0x7B)
00375 #define ADMUX (*(volatile unsigned char *)0x7C)
00376
00377 #define DIDR0 (*(volatile unsigned char *)0x7E)
00378 #define DIDR1 (*(volatile unsigned char *)0x7F)
00379
00380 #define TCCR1A (*(volatile unsigned char *)0x80)
00381 #define TCCR1B (*(volatile unsigned char *)0x81)
00382 #define TCCR1C (*(volatile unsigned char *)0x82)
00383 #define TCNT1 (*(volatile unsigned int *)0x84)
00384 #define ICR1 (*(volatile unsigned int *)0x86)
00385 #define OCR1A (*(volatile unsigned int *)0x88)
00386 #define OCR1B (*(volatile unsigned int *)0x8A)
00387 #define OCR1C (*(volatile unsigned int *)0x8C)
00388
00389 #define TCCR3A (*(volatile unsigned char *)0x90)
00390 #define TCCR3B (*(volatile unsigned char *)0x91)
00391 #define TCCR3C (*(volatile unsigned char *)0x92)
00392 #define TCNT3 (*(volatile unsigned int *)0x94)
00393 #define ICR3 (*(volatile unsigned int *)0x96)
00394 #define OCR3A (*(volatile unsigned int *)0x98)
00395 #define OCR3B (*(volatile unsigned int *)0x9A)
00396 #define OCR3C (*(volatile unsigned int *)0x9C)
00397
00398 #define TCCR2A (*(volatile unsigned char *)0xB0)
00399 #define TCNT2 (*(volatile unsigned char *)0xB2)
00400 #define OCR2A (*(volatile unsigned char *)0xB3)
00401
00402 #define ASSR (*(volatile unsigned char *)0xB6)
00403
00404 #define TWBR (*(volatile unsigned char *)0xB8)
00405 #define TWSR (*(volatile unsigned char *)0XB9)
00406 #define TWAR (*(volatile unsigned char *)0xBA)
00407 #define TWDR (*(volatile unsigned char *)0xBB)
00408 #define TWCR (*(volatile unsigned char *)0xBC)
00409
00410 #define UCSR0A (*(volatile unsigned char *)0xC0)
00411 #define UCSR0B (*(volatile unsigned char *)0xC1)
00412 #define UCSR0C (*(volatile unsigned char *)0xC2)
00413 #define UBRR0 (*(volatile unsigned int *)0xC4)
00414 #define UBRR0L (*(volatile unsigned char *)0xC4)
00415 #define UBRR0H (*(volatile unsigned char *)0xC5)
00416 #define UDR0 (*(volatile unsigned char *)0xC6)
00417
00418 #define UCSR1A (*(volatile unsigned char *)0xC8)
00419 #define UCSR1B (*(volatile unsigned char *)0xC9)
00420 #define UCSR1C (*(volatile unsigned char *)0xCA)
00421 #define UBRR1 (*(volatile unsigned int *)0xCC)
00422 #define UBRR1L (*(volatile unsigned char *)0xCC)
00423 #define UBRR1H (*(volatile unsigned char *)0xCD)
00424 #define UDR1 (*(volatile unsigned char *)0xCE)
00425
00426
00427
00428
00429
00430
00431
00432 #define RESET_vect 1
00433 #define INT0_vect 2
00434 #define INT1_vect 3
00435 #define INT2_vect 4
00436 #define INT3_vect 5
00437 #define INT4_vect 6
00438 #define INT5_vect 7
00439 #define INT6_vect 8
00440 #define INT7_vect 9
00441 #define TIMER2_COMP_vect 10
00442 #define TIMER2_OVF_vect 11
00443 #define TIMER1_CAPT_vect 12
00444 #define TIMER1_COMPA_vect 13
00445 #define TIMER1_COMPB_vect 14
00446 #define TIMER1_COMPC_vect 15
00447 #define TIMER1_OVF_vect 16
00448 #define TIMER0_COMP_vect 17
00449 #define TIMER0_OVF_vect 18
00450 #define CANIT_vect 19
00451 #define CANTOVF_vect 20
00452 #define SPI_STC_vect 21
00453 #define USART0_RXC_vect 22
00454 #define USART0_UDRE_vect 23
00455 #define USART0_TXC_vect 24
00456 #define ANA_COMP_vect 25
00457 #define ADC_vect 26
00458 #define EE_RDY_vect 27
00459 #define TIMER3_CAPT_vect 28
00460 #define TIMER3_COMPA_vect 29
00461 #define TIMER3_COMPB_vect 30
00462 #define TIMER3_COMPC_vect 31
00463 #define TIMER3_OVF_vect 32
00464 #define USART1_RXC_vect 33
00465 #define USART1_UDRE_vect 34
00466 #define USART1_TXC_vect 35
00467 #define TWI_vect 36
00468 #define SPM_RDY_vect 37
00469
00470 #endif
00471
00472
00473
00474
00475
00476
00477
00478 #define PINA7 7
00479 #define PINA6 6
00480 #define PINA5 5
00481 #define PINA4 4
00482 #define PINA3 3
00483 #define PINA2 2
00484 #define PINA1 1
00485 #define PINA0 0
00486
00487
00488 #define DDA7 7
00489 #define DDA6 6
00490 #define DDA5 5
00491 #define DDA4 4
00492 #define DDA3 3
00493 #define DDA2 2
00494 #define DDA1 1
00495 #define DDA0 0
00496
00497
00498 #define PORTA7 7
00499 #define PORTA6 6
00500 #define PORTA5 5
00501 #define PORTA4 4
00502 #define PORTA3 3
00503 #define PORTA2 2
00504 #define PORTA1 1
00505 #define PORTA0 0
00506
00507
00508 #define PA7 7
00509 #define PA6 6
00510 #define PA5 5
00511 #define PA4 4
00512 #define PA3 3
00513 #define PA2 2
00514 #define PA1 1
00515 #define PA0 0
00516
00517
00518 #define PINB7 7
00519 #define PINB6 6
00520 #define PINB5 5
00521 #define PINB4 4
00522 #define PINB3 3
00523 #define PINB2 2
00524 #define PINB1 1
00525 #define PINB0 0
00526
00527
00528 #define DDB7 7
00529 #define DDB6 6
00530 #define DDB5 5
00531 #define DDB4 4
00532 #define DDB3 3
00533 #define DDB2 2
00534 #define DDB1 1
00535 #define DDB0 0
00536
00537
00538 #define PB7 7
00539 #define PB6 6
00540 #define PB5 5
00541 #define PB4 4
00542 #define PB3 3
00543 #define PB2 2
00544 #define PB1 1
00545 #define PB0 0
00546
00547
00548 #define PORTB7 7
00549 #define PORTB6 6
00550 #define PORTB5 5
00551 #define PORTB4 4
00552 #define PORTB3 3
00553 #define PORTB2 2
00554 #define PORTB1 1
00555 #define PORTB0 0
00556
00557
00558 #define PINC7 7
00559 #define PINC6 6
00560 #define PINC5 5
00561 #define PINC4 4
00562 #define PINC3 3
00563 #define PINC2 2
00564 #define PINC1 1
00565 #define PINC0 0
00566
00567
00568 #define DDC7 7
00569 #define DDC6 6
00570 #define DDC5 5
00571 #define DDC4 4
00572 #define DDC3 3
00573 #define DDC2 2
00574 #define DDC1 1
00575 #define DDC0 0
00576
00577
00578 #define PC7 7
00579 #define PC6 6
00580 #define PC5 5
00581 #define PC4 4
00582 #define PC3 3
00583 #define PC2 2
00584 #define PC1 1
00585 #define PC0 0
00586
00587
00588 #define PORTC7 7
00589 #define PORTC6 6
00590 #define PORTC5 5
00591 #define PORTC4 4
00592 #define PORTC3 3
00593 #define PORTC2 2
00594 #define PORTC1 1
00595 #define PORTC0 0
00596
00597
00598 #define PIND7 7
00599 #define PIND6 6
00600 #define PIND5 5
00601 #define PIND4 4
00602 #define PIND3 3
00603 #define PIND2 2
00604 #define PIND1 1
00605 #define PIND0 0
00606
00607
00608 #define DDD7 7
00609 #define DDD6 6
00610 #define DDD5 5
00611 #define DDD4 4
00612 #define DDD3 3
00613 #define DDD2 2
00614 #define DDD1 1
00615 #define DDD0 0
00616
00617
00618 #define PD7 7
00619 #define PD6 6
00620 #define PD5 5
00621 #define PD4 4
00622 #define PD3 3
00623 #define PD2 2
00624 #define PD1 1
00625 #define PD0 0
00626
00627
00628 #define PORTD7 7
00629 #define PORTD6 6
00630 #define PORTD5 5
00631 #define PORTD4 4
00632 #define PORTD3 3
00633 #define PORTD2 2
00634 #define PORTD1 1
00635 #define PORTD0 0
00636
00637
00638 #define PINE7 7
00639 #define PINE6 6
00640 #define PINE5 5
00641 #define PINE4 4
00642 #define PINE3 3
00643 #define PINE2 2
00644 #define PINE1 1
00645 #define PINE0 0
00646
00647
00648 #define DDE7 7
00649 #define DDE6 6
00650 #define DDE5 5
00651 #define DDE4 4
00652 #define DDE3 3
00653 #define DDE2 2
00654 #define DDE1 1
00655 #define DDE0 0
00656
00657
00658 #define PE7 7
00659 #define PE6 6
00660 #define PE5 5
00661 #define PE4 4
00662 #define PE3 3
00663 #define PE2 2
00664 #define PE1 1
00665 #define PE0 0
00666
00667
00668 #define PORTE7 7
00669 #define PORTE6 6
00670 #define PORTE5 5
00671 #define PORTE4 4
00672 #define PORTE3 3
00673 #define PORTE2 2
00674 #define PORTE1 1
00675 #define PORTE0 0
00676
00677
00678 #define PINF7 7
00679 #define PINF6 6
00680 #define PINF5 5
00681 #define PINF4 4
00682 #define PINF3 3
00683 #define PINF2 2
00684 #define PINF1 1
00685 #define PINF0 0
00686
00687
00688 #define DDF7 7
00689 #define DDF6 6
00690 #define DDF5 5
00691 #define DDF4 4
00692 #define DDF3 3
00693 #define DDF2 2
00694 #define DDF1 1
00695 #define DDF0 0
00696
00697
00698 #define PF7 7
00699 #define PF6 6
00700 #define PF5 5
00701 #define PF4 4
00702 #define PF3 3
00703 #define PF2 2
00704 #define PF1 1
00705 #define PF0 0
00706
00707
00708 #define PORTF7 7
00709 #define PORTF6 6
00710 #define PORTF5 5
00711 #define PORTF4 4
00712 #define PORTF3 3
00713 #define PORTF2 2
00714 #define PORTF1 1
00715 #define PORTF0 0
00716
00717
00718 #define PING4 4
00719 #define PING3 3
00720 #define PING2 2
00721 #define PING1 1
00722 #define PING0 0
00723
00724
00725 #define DDG4 4
00726 #define DDG3 3
00727 #define DDG2 2
00728 #define DDG1 1
00729 #define DDG0 0
00730
00731
00732 #define PG4 4
00733 #define PG3 3
00734 #define PG2 2
00735 #define PG1 1
00736 #define PG0 0
00737
00738
00739 #define PORTG4 4
00740 #define PORTG3 3
00741 #define PORTG2 2
00742 #define PORTG1 1
00743 #define PORTG0 0
00744
00745
00746 #define OCF0A 1
00747 #define TOV0 0
00748
00749
00750 #define ICF1 5
00751 #define OCF1C 3
00752 #define OCF1B 2
00753 #define OCF1A 1
00754 #define TOV1 0
00755
00756
00757 #define OCF2A 1
00758 #define TOV2 0
00759
00760
00761 #define ICF3 5
00762 #define OCF3C 3
00763 #define OCF3B 2
00764 #define OCF3A 1
00765 #define TOV3 0
00766
00767
00768 #define INTF7 7
00769 #define INTF6 6
00770 #define INTF5 5
00771 #define INTF4 4
00772 #define INTF3 3
00773 #define INTF2 2
00774 #define INTF1 1
00775 #define INTF0 0
00776
00777
00778 #define INT7 7
00779 #define INT6 6
00780 #define INT5 5
00781 #define INT4 4
00782 #define INT3 3
00783 #define INT2 2
00784 #define INT1 1
00785 #define INT0 0
00786
00787
00788 #define ISC31 7
00789 #define ISC30 6
00790 #define ISC21 5
00791 #define ISC20 4
00792 #define ISC11 3
00793 #define ISC10 2
00794 #define ISC01 1
00795 #define ISC00 0
00796
00797
00798 #define ISC71 7
00799 #define ISC70 6
00800 #define ISC61 5
00801 #define ISC60 4
00802 #define ISC51 3
00803 #define ISC50 2
00804 #define ISC41 1
00805 #define ISC40 0
00806
00807
00808 #define EERIE 3
00809 #define EEMWE 2
00810 #define EEWE 1
00811 #define EERE 0
00812
00813
00814 #define TSM 7
00815 #define PSR2 1
00816 #define PSR310 0
00817
00818
00819
00820 #define COM0A1 7
00821 #define COM0A0 6
00822 #define COM0B1 5
00823 #define COM0B0 4
00824 #define WGM01 1
00825 #define WGM00 0
00826
00827
00828 #define FOC0A 7
00829 #define FOC0B 6
00830
00831 #define WGM02 3
00832 #define CS02 2
00833 #define CS01 1
00834 #define CS00 0
00835
00836
00837 #define SPIE 7
00838 #define SPE 6
00839 #define DORD 5
00840 #define MSTR 4
00841 #define CPOL 3
00842 #define CPHA 2
00843 #define SPR1 1
00844 #define SPR0 0
00845
00846
00847 #define SPIF 7
00848 #define WCOL 6
00849 #define SPI2X 0
00850
00851
00852 #define ACD 7
00853 #define ACBG 6
00854 #define ACO 5
00855 #define ACI 4
00856 #define ACIE 3
00857 #define ACIC 2
00858 #define ACIS1 1
00859 #define ACIS0 0
00860
00861
00862 #define IDRD 7
00863 #define OCDR7 7
00864 #define OCDR6 6
00865 #define OCDR5 5
00866 #define OCDR4 4
00867 #define OCDR3 3
00868 #define OCDR2 2
00869 #define OCDR1 1
00870 #define OCDR0 0
00871
00872
00873 #define SM2 3
00874 #define SM1 2
00875 #define SM0 1
00876 #define SE 0
00877
00878
00879 #define JTRF 4
00880 #define WDRF 3
00881 #define BORF 2
00882 #define EXTRF 1
00883 #define PORF 0
00884
00885
00886 #define JTD 7
00887 #define PUD 4
00888 #define IVSEL 1
00889 #define IVCE 0
00890
00891
00892 #define SPMIE 7
00893 #define RWWSB 6
00894 #define SIGRD 5
00895 #define RWWSRE 4
00896 #define BLBSET 3
00897 #define PGWRT 2
00898 #define PGERS 1
00899 #define SPMEN 0
00900
00901
00902 #define RAMPZ0 0
00903
00904
00905 #define SP15 7
00906 #define SP14 6
00907 #define SP13 5
00908 #define SP12 4
00909 #define SP11 3
00910 #define SP10 2
00911 #define SP9 1
00912 #define SP8 0
00913
00914
00915 #define SP7 7
00916 #define SP6 6
00917 #define SP5 5
00918 #define SP4 4
00919 #define SP3 3
00920 #define SP2 2
00921 #define SP1 1
00922 #define SP0 0
00923
00924
00925 #define WDIF 7
00926 #define WDIE 6
00927 #define WDP3 5
00928 #define WDCE 4
00929 #define WDE 3
00930 #define WDP2 2
00931 #define WDP1 1
00932 #define WDP0 0
00933
00934
00935 #define CKLPCE 7
00936 #define CLKPCE 7 //for compatiblity
00937 #define CKLPS3 3
00938 #define CKLPS2 2
00939 #define CKLPS1 1
00940 #define CKLPS0 0
00941
00942
00943 #define OCIE0B 2
00944 #define OCIE0A 1
00945 #define TOIE0 0
00946
00947
00948 #define ICIE1 5
00949 #define OCIE1C 3
00950 #define OCIE1B 2
00951 #define OCIE1A 1
00952 #define TOIE1 0
00953
00954
00955 #define OCIE2A 1
00956 #define TOIE2 0
00957
00958
00959 #define ICIE3 5
00960 #define OCIE3C 3
00961 #define OCIE3B 2
00962 #define OCIE3A 1
00963 #define TOIE3 0
00964
00965
00966 #define SRE 7
00967 #define SRL2 6
00968 #define SRL1 5
00969 #define SRL0 4
00970 #define SRW11 3
00971 #define SRW10 2
00972 #define SRW01 1
00973 #define SRW00 0
00974
00975
00976 #define XMBK 7
00977 #define XMM2 2
00978 #define XMM1 1
00979 #define XMM0 0
00980
00981
00982 #define ADEN 7
00983 #define ADSC 6
00984 #define ADATE 5
00985 #define ADIF 4
00986 #define ADIE 3
00987 #define ADPS2 2
00988 #define ADPS1 1
00989 #define ADPS0 0
00990
00991
00992 #define ADHSM 7
00993 #define ACME 6
00994 #define ADST2 2
00995 #define ADST1 1
00996 #define ADST0 0
00997
00998
00999 #define REFS1 7
01000 #define REFS0 6
01001 #define ADLAR 5
01002 #define MUX4 4
01003 #define MUX3 3
01004 #define MUX2 2
01005 #define MUX1 1
01006 #define MUX0 0
01007
01008
01009 #define COM1A1 7
01010 #define COM1A0 6
01011 #define COM1B1 5
01012 #define COM1B0 4
01013 #define COM1C1 3
01014 #define COM1C0 2
01015 #define WGM11 1
01016 #define WGM10 0
01017
01018
01019 #define ICNC1 7
01020 #define ICES1 6
01021 #define WGM13 4
01022 #define WGM12 3
01023 #define CS12 2
01024 #define CS11 1
01025 #define CS10 0
01026
01027
01028 #define FOC1A 7
01029 #define FOC1B 6
01030 #define FOC1C 5
01031
01032
01033 #define COM3A1 7
01034 #define COM3A0 6
01035 #define COM3B1 5
01036 #define COM3B0 4
01037 #define COM3C1 3
01038 #define COM3C0 2
01039 #define WGM31 1
01040 #define WGM30 0
01041
01042
01043 #define ICNC3 7
01044 #define ICES3 6
01045 #define WGM33 4
01046 #define WGM32 3
01047 #define CS32 2
01048 #define CS31 1
01049 #define CS30 0
01050
01051
01052 #define FOC3A 7
01053 #define FOC3B 6
01054 #define FOC3C 5
01055
01056
01057 #define FOC2 7
01058 #define WGM20 6
01059 #define COM21 5
01060 #define COM20 4
01061 #define WGM21 3
01062 #define CS22 2
01063 #define CS21 1
01064 #define CS20 0
01065
01066
01067 #define EXCLK 4
01068 #define AS2 3
01069 #define TCN2UB 2
01070 #define OCR2UB 1
01071 #define TCR2UB 0
01072
01073
01074 #define TWS7 7
01075 #define TWS6 6
01076 #define TWS5 5
01077 #define TWS4 4
01078 #define TWS3 3
01079 #define TWPS1 1
01080 #define TWPS0 0
01081
01082
01083 #define TWA6 7
01084 #define TWA5 6
01085 #define TWA4 5
01086 #define TWA3 4
01087 #define TWA2 3
01088 #define TWA1 2
01089 #define TWA0 1
01090 #define TWGCE 0
01091
01092
01093 #define TWINT 7
01094 #define TWEA 6
01095 #define TWSTA 5
01096 #define TWSTO 4
01097 #define TWWC 3
01098 #define TWEN 2
01099 #define TWIE 0
01100
01101
01102 #define RXC0 7
01103 #define TXC0 6
01104 #define UDRE0 5
01105 #define FE0 4
01106 #define DOR0 3
01107 #define UPE0 2
01108 #define U2X0 1
01109 #define MPCM0 0
01110
01111
01112 #define RXCIE0 7
01113 #define TXCIE0 6
01114 #define UDRIE0 5
01115 #define RXEN0 4
01116 #define TXEN0 3
01117 #define UCSZ02 2
01118 #define RXB80 1
01119 #define TXB80 0
01120
01121
01122 #define UMSEL0 6
01123 #define UPM01 5
01124 #define UPM00 4
01125 #define USBS0 3
01126 #define UCSZ01 2
01127 #define UCSZ00 1
01128 #define UCPOL0 0
01129
01130
01131 #define RXC1 7
01132 #define TXC1 6
01133 #define UDRE1 5
01134 #define FE1 4
01135 #define DOR1 3
01136 #define UPE1 2
01137 #define U2X1 1
01138 #define MPCM1 0
01139
01140
01141 #define RXCIE1 7
01142 #define TXCIE1 6
01143 #define UDRIE1 5
01144 #define RXEN1 4
01145 #define TXEN1 3
01146 #define UCSZ12 2
01147 #define RXB81 1
01148 #define TXB81 0
01149
01150
01151 #define UMSEL1 6
01152 #define UPM11 5
01153 #define UPM10 4
01154 #define USBS1 3
01155 #define UCSZ11 2
01156 #define UCSZ10 1
01157 #define UCPOL1 0
01158
01159
01160
01161 #define PCIE0 0
01162
01163
01164 #define PCIF0 0
01165
01166
01167 #define PCINT7 7
01168 #define PCINT6 6
01169 #define PCINT5 5
01170 #define PCINT4 4
01171 #define PCINT3 3
01172 #define PCINT2 2
01173 #define PCINT1 1
01174 #define PCINT0 0
01175
01176
01177
01178
01179 #define DETACH 0 //
01180 #define RMWKUP 1 //
01181 #define LSM 2 //
01182
01183
01184 #define SUSPI 0 //
01185 #define MSOFI 1 //
01186 #define SOFI 2 //
01187 #define EORSTI 3 //
01188 #define WAKEUPI 4 //
01189 #define EORSMI 5 //
01190 #define UPRSMI 6 //
01191
01192
01193 #define SUSPE 0 //
01194 #define MSOFE 1 //
01195 #define SOFE 2 //
01196 #define EORSTE 3 //
01197 #define WAKEUPE 4 //
01198 #define EORSME 5 //
01199 #define UPRSME 6 //
01200
01201
01202 #define UDADDR0 0 //
01203 #define UDADDR1 1 //
01204 #define UDADDR2 2 //
01205 #define UDADDR3 3 //
01206 #define UDADDR4 4 //
01207 #define UDADDR5 5 //
01208 #define UDADDR6 6 //
01209 #define ADDEN 7 //
01210
01211
01212 #define UDFNUML_0 0 //
01213 #define UDFNUML_1 1 //
01214 #define UDFNUML_2 2 //
01215 #define UDFNUML_3 3 //
01216 #define UDFNUML_4 4 //
01217 #define UDFNUML_5 5 //
01218 #define UDFNUML_6 6 //
01219 #define UDFNUML_7 7 //
01220
01221
01222 #define UDFNUMH_0 0 //
01223 #define UDFNUMH_1 1 //
01224 #define UDFNUMH_2 2 //
01225
01226
01227 #define FNCERR 4 //
01228
01229
01230 #define TXINI 0 //
01231 #define STALLEDI 1 //
01232 #define RXOUTI 2 //
01233 #define RXSTPI 3 //
01234 #define NAKOUTI 4 //
01235 #define RWAL 5 //
01236 #define NAKINI 6 //
01237 #define FIFOCON 7 //
01238
01239
01240 #define UENUM_0 0 //
01241 #define UENUM_1 1 //
01242 #define UENUM_2 2 //
01243
01244
01245 #define EPRST0 0 //
01246 #define EPRST1 1 //
01247 #define EPRST2 2 //
01248 #define EPRST3 3 //
01249 #define EPRST4 4 //
01250 #define EPRST5 5 //
01251 #define EPRST6 6 //
01252
01253
01254 #define EPEN 0 //
01255 #define RSTDT 3 //
01256 #define STALLRQC 4 //
01257 #define STALLRQ 5 //
01258
01259
01260 #define EPDIR 0 //
01261 #define NYETDIS 1 //
01262 #define AUTOSW 2 //
01263 #define ISOSW 3 //
01264 #define EPTYPE0 6 //
01265 #define EPTYPE1 7 //
01266
01267
01268 #define ALLOC 1 //
01269 #define EPBK0 2 //
01270 #define EPBK1 3 //
01271 #define EPSIZE0 4 //
01272 #define EPSIZE1 5 //
01273 #define EPSIZE2 6 //
01274
01275
01276 #define NBUSYBK0 0 //
01277 #define NBUSYBK1 1 //
01278 #define DTSEQ0 2 //
01279 #define DTSEQ1 3 //
01280 #define ZLPSEEN 4 //
01281 #define UNDERFI 5 //
01282 #define OVERFI 6 //
01283 #define CFGOK 7 //
01284
01285
01286 #define CURRBK0 0 //
01287 #define CURRBK1 1 //
01288 #define CTRLDIR 2 //
01289
01290
01291 #define TXINE 0 //
01292 #define STALLEDE 1 //
01293 #define RXOUTE 2 //
01294 #define RXSTPE 3 //
01295 #define NAKOUTE 4 //
01296 #define NAKINE 6 //
01297 #define FLERRE 7 //
01298
01299
01300 #define UEDATX_0 0 //
01301 #define UEDATX_1 1 //
01302 #define UEDATX_2 2 //
01303 #define UEDATX_3 3 //
01304 #define UEDATX_4 4 //
01305 #define UEDATX_5 5 //
01306 #define UEDATX_6 6 //
01307 #define UEDATX_7 7 //
01308
01309
01310 #define UEBCLX_0 0 //
01311 #define UEBCLX_1 1 //
01312 #define UEBCLX_2 2 //
01313 #define UEBCLX_3 3 //
01314 #define UEBCLX_4 4 //
01315 #define UEBCLX_5 5 //
01316 #define UEBCLX_6 6 //
01317 #define UEBCLX_7 7 //
01318
01319
01320 #define UEBCHX_0 0 //
01321 #define UEBCHX_1 1 //
01322 #define UEBCHX_2 2 //
01323
01324
01325 #define UEINT_0 0 //
01326 #define UEINT_1 1 //
01327 #define UEINT_2 2 //
01328 #define UEINT_3 3 //
01329 #define UEINT_4 4 //
01330 #define UEINT_5 5 //
01331 #define UEINT_6 6 //
01332
01333
01334
01335
01336 #define UVREGE 0 //
01337 #define UVCONE 4 //
01338 #define UIDE 6 //
01339 #define UIMOD 7 //
01340
01341
01342 #define VBUSTE 0 //
01343 #define IDTE 1 //
01344 #define OTGPADE 4 //
01345 #define FRZCLK 5 //
01346 #define HOST 6 //
01347 #define USBE 7 //
01348
01349
01350 #define VBUS 0 //
01351 #define ID 1 //
01352 #define SPEED 3 //
01353
01354
01355 #define VBUSTI 0 //
01356 #define IDTI 1 //
01357
01358
01359
01360 #define VBUSRQC 0 //
01361 #define VBUSREQ 1 //
01362 #define VBUSHWC 2 //
01363 #define SRPSEL 3 //
01364 #define SRPREQ 4 //
01365 #define HNPREQ 5 //
01366
01367
01368 #define SRPE 0 //
01369 #define VBERRE 1 //
01370 #define BCERRE 2 //
01371 #define ROLEEXE 3 //
01372 #define HNPERRE 4 //
01373 #define STOE 5 //
01374
01375
01376 #define SRPI 0 //
01377 #define VBERRI 1 //
01378 #define BCERRI 2 //
01379 #define ROLEEXI 3 //
01380 #define HNPERRI 4 //
01381 #define STOI 5 //
01382
01383
01384
01385
01386 #define SOFEN 0 //
01387 #define RESET 1 //
01388 #define RESUME 2 //
01389
01390
01391 #define DCONNI 0 //
01392 #define DDISCI 1 //
01393 #define RSTI 2 //
01394 #define RSMEDI 3 //
01395 #define RXRSMI 4 //
01396 #define HSOFI 5 //
01397 #define HWUPI 6 //
01398
01399
01400 #define HWUPE 6
01401 #define HSOFE 5
01402 #define RXRSME 4
01403 #define RSMEDE 3
01404 #define RSTE 2
01405 #define DDISCE 1
01406 #define DCONNE 0
01407
01408
01409
01410
01411 #define UHADDR_0 0 //
01412 #define UHADDR_1 1 //
01413 #define UHADDR_2 2 //
01414 #define UHADDR_3 3 //
01415 #define UHADDR_4 4 //
01416 #define UHADDR_5 5 //
01417 #define UHADDR_6 6 //
01418
01419
01420 #define UHFNUMH_0 0 //
01421 #define UHFNUMH_1 1 //
01422 #define UHFNUMH_2 2 //
01423
01424
01425 #define UHFNUML_0 0 //
01426 #define UHFNUML_1 1 //
01427 #define UHFNUML_2 2 //
01428 #define UHFNUML_3 3 //
01429 #define UHFNUML_4 4 //
01430 #define UHFNUML_5 5 //
01431 #define UHFNUML_6 6 //
01432 #define UHFNUML_7 7 //
01433
01434
01435 #define UHFLEN_0 0 //
01436 #define UHFLEN_1 1 //
01437 #define UHFLEN_2 2 //
01438 #define UHFLEN_3 3 //
01439 #define UHFLEN_4 4 //
01440 #define UHFLEN_5 5 //
01441 #define UHFLEN_6 6 //
01442 #define UHFLEN_7 7 //
01443
01444
01445 #define INRQ0 0 //
01446 #define INRQ1 1 //
01447 #define INRQ2 2 //
01448 #define INRQ3 3 //
01449 #define INRQ4 4 //
01450 #define INRQ5 5 //
01451 #define INRQ6 6 //
01452 #define INRQ7 7 //
01453
01454
01455 #define RXINI 0 //
01456 #define RXSTALLI 1 //
01457 #define TXOUTI 2 //
01458 #define TXSTPI 3 //
01459 #define PERRI 4 //
01460
01461 #define NAKEDI 6 //
01462
01463
01464
01465 #define PNUM0 0 //
01466 #define PNUM1 1 //
01467 #define PNUM2 2 //
01468
01469
01470 #define PRST0 0 //
01471 #define PRST1 1 //
01472 #define PRST2 2 //
01473 #define PRST3 3 //
01474 #define PRST4 4 //
01475 #define PRST5 5 //
01476 #define PRST6 6 //
01477
01478
01479 #define PEN 0 //
01480
01481 #define INMODE 5 //
01482 #define PFREEZE 6 //
01483
01484
01485 #define PEPNUM0 0 //
01486 #define PEPNUM1 1 //
01487 #define PEPNUM2 2 //
01488 #define PEPNUM3 3 //
01489 #define PTOKEN0 4 //
01490 #define PTOKEN1 5 //
01491 #define PTYPE0 6 //
01492 #define PTYPE1 7 //
01493
01494
01495
01496 #define PBK0 2 //
01497 #define PBK1 3 //
01498 #define PSIZE0 4 //
01499 #define PSIZE1 5 //
01500 #define PSIZE2 6 //
01501
01502
01503 #define NBUSYK0 0 //
01504 #define NBUSYK1 1 //
01505
01506
01507
01508
01509
01510
01511
01512
01513
01514
01515
01516
01517
01518
01519
01520
01521
01522 #define RXINE 0 //
01523 #define RXSTALLE 1 //
01524 #define TXOUTE 2 //
01525 #define TXSTPE 3 //
01526 #define PERRE 4 //
01527 #define NAKEDE 6 //
01528
01529
01530
01531 #define PDAT0 0 //
01532 #define PDAT1 1 //
01533 #define PDAT2 2 //
01534 #define PDAT3 3 //
01535 #define PDAT4 4 //
01536 #define PDAT5 5 //
01537 #define PDAT6 6 //
01538 #define PDAT7 7 //
01539
01540
01541 #define PBYCT0 0 //
01542 #define PBYCT1 1 //
01543 #define PBYCT2 2 //
01544 #define PBYCT3 3 //
01545 #define PBYCT4 4 //
01546 #define PBYCT5 5 //
01547 #define PBYCT6 6 //
01548 #define PBYCT7 7 //
01549
01550
01551 #define PBYCT8 0 //
01552 #define PBYCT9 1 //
01553 #define PBYCT10 2 //
01554
01555
01556 #define PINT0 0 //
01557 #define PINT1 1 //
01558 #define PINT2 2 //
01559 #define PINT3 3 //
01560 #define PINT4 4 //
01561 #define PINT5 5 //
01562 #define PINT6 6 //
01563
01564
01565 #define DATATGL 0 //
01566 #define DATAPID 1 //
01567 #define PID 2 //
01568 #define TIMEOUT 3 //
01569 #define CRC16 4 //
01570 #define COUNTER0 5 //
01571 #define COUNTER1 6 //
01572
01573
01574 #define XL r26
01575 #define XH r27
01576 #define YL r28
01577 #define YH r29
01578 #define ZL r30
01579 #define ZH r31
01580
01581
01582
01583 #define PLLP2 4
01584 #define PLLP1 3
01585 #define PLLP0 2
01586 #define PLLE 1
01587 #define PLOCK 0
01588
01589
01590
01591
01592 #endif
01593
01594
01595
01596
01597
01598
01599
01600
01601
01602
01603
01604
01605
01606