Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (119006): Selected device 5CEBA4F23C7 for design "TFT"
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Critical Warning (169085): No exact pin location assignment(s) for 94 pins of 94 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.
Info (184020): Starting Fitter periphery placement operations
Info (11191): Automatically promoted 1 clock (1 global)
	Info (11162): clk~inputCLKENA0 with 14979 fanout uses global clock CLKCTRL_G10
Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:01
Info (176233): Starting register packing
Warning (335093): TimeQuest Timing Analyzer is analyzing 157 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'TFT.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332144): No user constrained base clocks found in the design
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
Info (176235): Finished register packing
	Extra Info (176218): Packed 1507 registers into blocks of type DSP block
	Extra Info (176220): Created 1244 register duplicates
Info (11798): Fitter preparation operations ending: elapsed time is 00:00:17
Info (170189): Fitter placement preparation operations beginning
Info (14951): The Fitter is using Advanced Physical Optimization.
Info (170190): Fitter placement preparation operations ending: elapsed time is 04:39:33
Info (170191): Fitter placement operations beginning
Info (170236): Placement optimizations have been running for 4 hour(s)
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 04:47:00
Info (170193): Fitter routing operations beginning
Info (170089): 1e+03 ns of routing delay (approximately 1.0% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report.
Info (170195): Router estimated average interconnect usage is 19% of the available device resources
	Info (170196): Router estimated peak interconnect usage is 26% of the available device resources in the region that extends from location X11_Y11 to location X21_Y22
Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
	Info (170201): Optimizations that may affect the design's routability were skipped
Info (170194): Fitter routing operations ending: elapsed time is 00:00:55
Info (11888): Total time spent on timing analysis during the Fitter is 68.39 seconds.
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:53
Info (144001): Generated suppressed messages file U:/DE0_TFT_Projekt/TFT_DEO/Testprojekte/TFT/output_files/TFT.fit.smsg
Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings
	Info: Peak virtual memory: 2718 megabytes
	Info: Processing ended: Fri Aug 12 03:09:02 2016
	Info: Elapsed time: 09:29:49
	Info: Total CPU time (on all processors): 1:00:48:12
Info: *******************************************************************