Synthesis and Ngdbuild Report synthesis: version Diamond (64-bit) 3.8.0.115.3 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved. Fri Jan 13 14:57:03 2017 Command Line: synthesis -f uart_impl_lattice.synproj -gui -msgset C:/Users/Christopher/Documents/Diamond/uart/promote.xml Synthesis options: The -a option is MachXO2. The -s option is 2. The -t option is CSBGA132. The -d option is LCMXO2-1200ZE. Using package CSBGA132. Using performance grade 2. ########################################################## ### Lattice Family : MachXO2 ### Device : LCMXO2-1200ZE ### Package : CSBGA132 ### Speed : 2 ########################################################## Optimization goal = Balanced Top-level module name = test. Target frequency = 1.000000 MHz. Maximum fanout = 1000. Timing path count = 3 BRAM utilization = 100.000000 % DSP usage = true DSP utilization = 100.000000 % fsm_encoding_style = auto resolve_mixed_drivers = 0 fix_gated_clocks = 1 Mux style = Auto Use Carry Chain = true carry_chain_length = 0 Loop Limit = 1950. Use IO Insertion = TRUE Use IO Reg = AUTO Resource Sharing = TRUE Propagate Constants = TRUE Remove Duplicate Registers = TRUE force_gsr = auto ROM style = auto RAM style = auto The -comp option is FALSE. The -syn option is FALSE. -p C:/lscc/diamond/3.8_x64/ispfpga/xo2c00/data (searchpath added) -p C:/Users/Christopher/Documents/Diamond/uart/impl (searchpath added) -p C:/Users/Christopher/Documents/Diamond/uart (searchpath added) VHDL library = work VHDL design file = C:/Users/Christopher/Documents/Diamond/uart/impl/source/test.vhd VHDL design file = C:/Users/Christopher/Documents/Diamond/uart/impl/source/osc.vhd VHDL design file = C:/Users/Christopher/Documents/Diamond/uart/impl/source/uart.vhd NGD file = uart_impl.ngd -sdc option: SDC file input not used. -lpf option: Output file option is ON. Hardtimer checking is enabled (default). The -dt option is not used. The -r option is OFF. [ Remove LOC Properties is OFF. ] Technology check ok... Analyzing Verilog file C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 Compile design. Compile Design Begin INFO - synthesis: The default VHDL library search path is now "C:/Users/Christopher/Documents/Diamond/uart/impl". VHDL-1504 Analyzing VHDL file c:/users/christopher/documents/diamond/uart/impl/source/osc.vhd. VHDL-1481 INFO - synthesis: c:/users/christopher/documents/diamond/uart/impl/source/osc.vhd(8): analyzing entity oscillator. VHDL-1012 INFO - synthesis: c:/users/christopher/documents/diamond/uart/impl/source/osc.vhd(12): analyzing architecture impl. VHDL-1010 unit test is not yet analyzed. VHDL-1485 Analyzing VHDL file c:/users/christopher/documents/diamond/uart/impl/source/uart.vhd. VHDL-1481 INFO - synthesis: c:/users/christopher/documents/diamond/uart/impl/source/uart.vhd(5): analyzing entity uart. VHDL-1012 INFO - synthesis: c:/users/christopher/documents/diamond/uart/impl/source/uart.vhd(16): analyzing architecture impl. VHDL-1010 unit test is not yet analyzed. VHDL-1485 Analyzing VHDL file c:/users/christopher/documents/diamond/uart/impl/source/test.vhd. VHDL-1481 INFO - synthesis: c:/users/christopher/documents/diamond/uart/impl/source/test.vhd(8): analyzing entity test. VHDL-1012 INFO - synthesis: c:/users/christopher/documents/diamond/uart/impl/source/test.vhd(12): analyzing architecture impl. VHDL-1010 unit test is not yet analyzed. VHDL-1485 unit test is not yet analyzed. VHDL-1485 c:/users/christopher/documents/diamond/uart/impl/source/test.vhd(8): executing test(impl) WARNING - synthesis: c:/users/christopher/documents/diamond/uart/impl/source/test.vhd(10): replacing existing netlist test(impl). VHDL-1205 Top module name (VHDL): test Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/xo2c00a/data/xo2alib.ngl'... Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/or5g00/data/orc5glib.ngl'... Loading device for application map from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.8_x64/ispfpga. Package Status: Final Version 1.42. Top-level module name = test. GSR will not be inferred because no asynchronous signal was found in the netlist. WARNING - synthesis: Initial value found on instance \uart0/shift_register_i0_i0 will be ignored. WARNING - synthesis: Initial value found on instance \uart0/shift_register_i0_i5 will be ignored. WARNING - synthesis: Initial value found on instance \uart0/shift_register_i0_i1 will be ignored. Applying 1.000000 MHz constraint to all clocks WARNING - synthesis: No user .sdc file. Results of NGD DRC are available in test_drc.log. Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/xo2c00a/data/xo2alib.ngl'... Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/or5g00/data/orc5glib.ngl'... All blocks are expanded and NGD expansion is successful. Writing NGD file uart_impl.ngd. ################### Begin Area Report (test)###################### Number of register bits => 25 of 1595 (1 % ) CCU2D => 5 FD1P3AX => 4 FD1P3IX => 8 FD1P3JX => 3 FD1S3AX => 10 GSR => 1 LUT4 => 42 OB => 2 OSCH => 1 PFUMX => 1 ################### End Area Report ################## ################### Begin BlackBox Report ###################### TSALL => 1 ################### End BlackBox Report ################## ################### Begin Clock Report ###################### Clock Nets Number of Clocks: 1 Net : osc0/clk, loads : 26 Clock Enable Nets Number of Clock Enables: 4 Top 4 highest fanout Clock Enables: Net : uart0/clk_enable_15, loads : 12 Net : uart0/clk_enable_4, loads : 1 Net : uart0/clk_enable_1, loads : 1 Net : uart0/clk_enable_10, loads : 1 Highest fanout non-clock nets Top 10 highest fanout non-clock nets: Net : tx_we, loads : 14 Net : uart0/clk_enable_15, loads : 12 Net : uart0/n723, loads : 12 Net : uart0/state_1, loads : 10 Net : uart0/state_0, loads : 10 Net : uart0/n727, loads : 10 Net : uart0/clk_counter_2, loads : 9 Net : uart0/clk_counter_6, loads : 8 Net : uart0/n174, loads : 8 Net : uart0/clk_counter_0, loads : 7 ################### End Clock Report ################## Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 1000.000000 -name | | | clk0 [get_nets clk] | 1.000 MHz| 46.356 MHz| 10 | | | -------------------------------------------------------------------------------- All constraints were met. Peak Memory Usage: 69.207 MB -------------------------------------------------------------- Elapsed CPU time for LSE flow : 1.125 secs --------------------------------------------------------------