cpldfit: version J.40 Xilinx Inc. Fitter Report Design Name: miniLA Date: 3- 5-2008, 2:57PM Device Used: XC95288XL-6-TQ144 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 229/288 ( 80%) 912 /1440 ( 63%) 559/864 ( 65%) 202/288 ( 70%) 106/117 ( 91%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 8/18 48/54 88/90 1/ 8 FB2 18/18* 9/54 36/90 0/10 FB3 7/18 37/54 86/90 3/ 5 FB4 18/18* 10/54 36/90 0/ 6 FB5 12/18 53/54 48/90 6/ 8 FB6 18/18* 10/54 36/90 0/ 8 FB7 18/18* 14/54 36/90 4/ 4* FB8 16/18 25/54 28/90 0/ 5 FB9 17/18 48/54 47/90 9/ 9* FB10 15/18 46/54 82/90 4/10 FB11 14/18 41/54 79/90 7/ 7* FB12 17/18 52/54 74/90 4/ 6 FB13 9/18 46/54 76/90 6/ 6* FB14 18/18* 43/54 56/90 7/ 8 FB15 14/18 53/54 52/90 9/ 9* FB16 10/18 24/54 52/90 8/ 8* ----- ----- ----- ----- 229/288 559/864 912/1440 68/117 * - Resource is exhausted ** Global Control Resources ** Signal 'clk_ob' mapped onto global clock net GCK1. Signal 'clk_o' mapped onto global clock net GCK2. Signal 'clk_in' mapped onto global clock net GCK3. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 37 37 | I/O : 98 109 Output : 26 26 | GCK/IO : 3 3 Bidirectional : 40 40 | GTS/IO : 4 4 GCK : 3 3 | GSR/IO : 1 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 106 106 ** Power Data ** There are 229 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************** Errors and Warnings *************************** INFO:Cpld:994 - Exhaustive fitting is trying pterm limit: 25 and input limit: 54 ************************* Summary of Mapped Logic ************************ ** 68 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State trig_o 8 8 FB1_5 20 I/O O STD FAST clk_ob 24 16 FB3_10 30 GCK/I/O GCK/O STD FAST clk_o 11 13 FB3_14 32 GCK/I/O GCK/O STD FAST st<1> 3 4 FB3_15 33 I/O O STD FAST RESET st<2> 3 4 FB5_2 34 I/O O STD FAST RESET st<3> 3 4 FB5_5 35 I/O O STD FAST RESET sram_d<31> 2 2 FB5_12 40 I/O I/O STD FAST RESET sram_d<30> 2 2 FB5_14 41 I/O I/O STD FAST RESET sram_d<29> 2 2 FB5_15 43 I/O I/O STD FAST RESET sram_d<28> 2 2 FB5_17 44 I/O I/O STD FAST RESET sram_d<27> 2 2 FB7_3 45 I/O I/O STD FAST RESET sram_d<26> 2 2 FB7_5 46 I/O I/O STD FAST RESET sram_d<25> 2 2 FB7_12 48 I/O I/O STD FAST RESET sram_d<24> 2 2 FB7_15 49 I/O I/O STD FAST RESET sram_d<23> 2 2 FB9_2 50 I/O I/O STD FAST RESET sram_d<22> 2 2 FB9_3 51 I/O I/O STD FAST RESET sram_d<21> 2 2 FB9_5 52 I/O I/O STD FAST RESET sram_d<20> 2 2 FB9_6 53 I/O I/O STD FAST RESET sram_d<19> 2 2 FB9_8 54 I/O I/O STD FAST RESET sram_d<18> 2 2 FB9_11 56 I/O I/O STD FAST RESET sram_d<17> 2 2 FB9_12 57 I/O I/O STD FAST RESET sram_d<16> 2 2 FB9_14 58 I/O I/O STD FAST RESET sram_adr<5> 2 6 FB9_17 59 I/O O STD FAST RESET dd<4> 13 22 FB10_2 117 I/O I/O STD FAST dd<5> 7 15 FB10_3 118 I/O I/O STD FAST dd<6> 7 15 FB10_5 119 I/O I/O STD FAST dd<7> 6 15 FB10_6 120 I/O I/O STD FAST sram_adr<4> 2 5 FB11_3 60 I/O O STD FAST RESET sram_adr<3> 2 4 FB11_5 61 I/O O STD FAST RESET sram_adr<2> 2 3 FB11_10 64 I/O O STD FAST RESET sram_adr<1> 2 2 FB11_11 66 I/O O STD FAST RESET sram_adr<0> 1 1 FB11_12 68 I/O O STD FAST RESET sram_adr<6> 2 7 FB11_14 69 I/O O STD FAST RESET sram_adr<7> 2 8 FB11_17 70 I/O O STD FAST RESET dd<0> 6 14 FB12_3 111 I/O I/O STD FAST dd<1> 6 14 FB12_5 112 I/O I/O STD FAST dd<2> 6 14 FB12_8 113 I/O I/O STD FAST dd<3> 12 31 FB12_12 116 I/O I/O STD FAST sram_ce_l 1 0 FB13_2 71 I/O O STD FAST sram_clk 24 16 FB13_8 74 I/O O STD FAST Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State sram_we_l 3 4 FB13_11 75 I/O O STD FAST SET sram_oe_l 3 4 FB13_14 76 I/O O STD FAST RESET sram_adsc_l 1 0 FB13_15 77 I/O O STD FAST sram_adr<8> 2 9 FB13_17 78 I/O O STD FAST RESET sram_d<6> 2 2 FB14_3 100 I/O I/O STD FAST RESET sram_d<5> 2 2 FB14_5 101 I/O I/O STD FAST RESET sram_d<4> 2 2 FB14_6 102 I/O I/O STD FAST RESET sram_d<3> 2 2 FB14_8 103 I/O I/O STD FAST RESET sram_d<2> 2 2 FB14_10 104 I/O I/O STD FAST RESET sram_d<1> 2 2 FB14_11 105 I/O I/O STD FAST RESET sram_d<0> 2 2 FB14_14 106 I/O I/O STD FAST RESET sram_adr<9> 2 10 FB15_2 79 I/O O STD FAST RESET sram_adr<10> 2 11 FB15_3 80 I/O O STD FAST RESET sram_adr<11> 2 12 FB15_8 81 I/O O STD FAST RESET sram_adr<12> 2 13 FB15_10 82 I/O O STD FAST RESET sram_adr<13> 2 14 FB15_11 83 I/O O STD FAST RESET sram_adr<14> 2 15 FB15_12 85 I/O O STD FAST RESET sram_adr<15> 2 16 FB15_14 86 I/O O STD FAST RESET sram_adr<16> 2 17 FB15_15 87 I/O O STD FAST RESET sram_d<15> 2 2 FB15_17 88 I/O I/O STD FAST RESET sram_d<14> 2 2 FB16_2 91 I/O I/O STD FAST RESET sram_d<13> 2 2 FB16_3 92 I/O I/O STD FAST RESET sram_d<12> 2 2 FB16_5 93 I/O I/O STD FAST RESET sram_d<11> 2 2 FB16_6 94 I/O I/O STD FAST RESET sram_d<10> 2 2 FB16_8 95 I/O I/O STD FAST RESET sram_d<9> 2 2 FB16_10 96 I/O I/O STD FAST RESET sram_d<8> 2 2 FB16_11 97 I/O I/O STD FAST RESET sram_d<7> 2 2 FB16_12 98 I/O I/O STD FAST RESET ** 161 Buried Nodes ** Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State trigcond_I/trig_cnt<0> 10 10 FB1_3 STD RESET timebase_I/clk_cnt<0> 6 25 FB1_4 STD RESET trigcond_I/trig_cnt<2> 12 12 FB1_9 STD RESET trigcond_I/trig_cnt<3> 13 13 FB1_10 STD RESET trigcond_I/tlen_cnt<3> 13 15 FB1_14 STD RESET trigcond_I/tlen_cnt<2> 15 15 FB1_16 STD RESET trigcond_I/trig_cnt<1> 11 11 FB1_17 STD RESET value_reg<2> 2 8 FB2_1 STD RESET value_reg<10> 2 8 FB2_2 STD RESET tsel_reg<2> 2 8 FB2_3 STD RESET tlen_reg<3> 2 8 FB2_4 STD RESET tlen_reg<2> 2 8 FB2_5 STD RESET tcnt_reg<3> 2 8 FB2_6 STD RESET tcnt_reg<2> 2 8 FB2_7 STD RESET stop 2 8 FB2_8 STD RESET psize_reg<3> 2 8 FB2_9 STD RESET psize_reg<2> 2 8 FB2_10 STD RESET mask_reg<3> 2 8 FB2_11 STD RESET mask_reg<2> 2 8 FB2_12 STD RESET mask_reg<11> 2 8 FB2_13 STD RESET mask_reg<10> 2 8 FB2_14 STD RESET edge_reg<3> 2 8 FB2_15 STD RESET edge_reg<2> 2 8 FB2_16 STD RESET edge_reg<11> 2 8 FB2_17 STD RESET edge_reg<10> 2 8 FB2_18 STD RESET timebase_I/clk_cnt<10> 12 25 FB3_5 STD RESET timebase_I/clk_cnt<7> 13 25 FB3_6 STD RESET timebase_I/clk_cnt<3> 12 25 FB3_17 STD RESET timebase_I/clk_cnt<6> 11 25 FB3_18 STD RESET value_reg<7> 2 8 FB4_1 STD RESET value_reg<4> 2 8 FB4_2 STD RESET value_reg<15> 2 8 FB4_3 STD RESET value_reg<12> 2 8 FB4_4 STD RESET tsel_reg<4> 2 8 FB4_5 STD RESET run 2 8 FB4_6 STD RESET pretrig_off 2 8 FB4_7 STD RESET mask_reg<7> 2 8 FB4_8 STD RESET mask_reg<4> 2 8 FB4_9 STD RESET mask_reg<1> 2 8 FB4_10 STD RESET mask_reg<15> 2 8 FB4_11 STD RESET Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State mask_reg<12> 2 8 FB4_12 STD RESET inv_trig 2 8 FB4_13 STD RESET epp_I/auto_inc 2 8 FB4_14 STD RESET edge_reg<7> 2 8 FB4_15 STD RESET edge_reg<4> 2 8 FB4_16 STD RESET edge_reg<15> 2 8 FB4_17 STD RESET edge_reg<12> 2 8 FB4_18 STD RESET trigcond_I/int_etrig_hit_reg 25 41 FB5_8 STD RESET trigcond_I/extrig_int 1 1 FB5_10 STD RESET trigcond_I/trig_on_d 2 2 FB5_11 STD RESET trig_on 2 3 FB5_13 STD RESET sram_I/sample_cnt_int<1> 2 3 FB5_16 STD RESET sample_cnt_en 2 2 FB5_18 STD RESET value_reg<9> 2 8 FB6_1 STD RESET value_reg<8> 2 8 FB6_2 STD RESET value_reg<3> 2 8 FB6_3 STD RESET value_reg<1> 2 8 FB6_4 STD RESET value_reg<11> 2 8 FB6_5 STD RESET value_reg<0> 2 8 FB6_6 STD RESET tsel_reg<3> 2 8 FB6_7 STD RESET tsel_reg<1> 2 8 FB6_8 STD RESET tsel_reg<0> 2 8 FB6_9 STD RESET tlen_reg<1> 2 8 FB6_10 STD RESET tlen_reg<0> 2 8 FB6_11 STD RESET tcnt_reg<1> 2 8 FB6_12 STD RESET tcnt_reg<0> 2 8 FB6_13 STD RESET psize_reg<1> 2 8 FB6_14 STD RESET psize_reg<0> 2 8 FB6_15 STD RESET mask_reg<9> 2 8 FB6_16 STD RESET mask_reg<8> 2 8 FB6_17 STD RESET epp_I/adr<0> 2 4 FB6_18 STD RESET value_reg<6> 2 8 FB7_1 STD RESET value_reg<5> 2 8 FB7_2 STD RESET value_reg<14> 2 8 FB7_4 STD RESET value_reg<13> 2 8 FB7_6 STD RESET mask_reg<6> 2 8 FB7_7 STD RESET mask_reg<5> 2 8 FB7_8 STD RESET mask_reg<14> 2 8 FB7_9 STD RESET mask_reg<13> 2 8 FB7_10 STD RESET edge_reg<6> 2 8 FB7_11 STD RESET Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State edge_reg<5> 2 8 FB7_13 STD RESET edge_reg<14> 2 8 FB7_14 STD RESET edge_reg<13> 2 8 FB7_16 STD RESET clr 2 8 FB7_17 STD RESET clk_falling_edge 2 8 FB7_18 STD RESET epp_I/d_rd_i_d 1 3 FB8_3 STD RESET epp_I/WR_l_i 1 1 FB8_4 STD RESET epp_I/RD_l_i 1 1 FB8_5 STD RESET epp_I/ALE_l_i 1 1 FB8_6 STD RESET $OpTx$$OpTx$FX_DC$187_INV$520 1 2 FB8_7 STD timebase_I/sw_read_clk_r 2 2 FB8_8 STD RESET timebase_I/sw_read_clk_f 2 2 FB8_9 STD RESET timebase_I/clk_5f<2> 2 3 FB8_10 STD RESET timebase_I/clk_5f<0> 2 4 FB8_11 STD RESET epp_I/adr<3> 2 4 FB8_12 STD RESET epp_I/adr<2> 2 4 FB8_13 STD RESET epp_I/adr<1> 2 4 FB8_14 STD RESET $OpTx$trigcond_I/int_vtrig_comp<9>/trigcond_I/int_vtrig_comp<9>_D2_INV$532 2 3 FB8_15 STD $OpTx$trigcond_I/int_vtrig_comp<8>/trigcond_I/int_vtrig_comp<8>_D2_INV$531 2 3 FB8_16 STD $OpTx$trigcond_I/int_vtrig_comp<15>/trigcond_I/int_vtrig_comp<15>_D2_INV$525 2 3 FB8_17 STD timebase_I/clk_5f<1> 3 4 FB8_18 STD RESET sram_I/sample_cnt_int<6> 2 8 FB9_4 STD RESET sram_I/sample_cnt_int<5> 2 7 FB9_7 STD RESET sram_I/sample_cnt_int<4> 2 6 FB9_9 STD RESET sram_I/sample_cnt_int<3> 2 5 FB9_10 STD RESET sram_I/sample_cnt_int<2> 2 4 FB9_13 STD RESET done 2 3 FB9_15 STD RESET adr_cnt_en 2 4 FB9_16 STD RESET state_FFd1 15 32 FB9_18 STD RESET mask_reg<0> 2 8 FB10_4 STD RESET extrig_val 2 8 FB10_7 STD RESET extrig_en 2 8 FB10_8 STD RESET edge_reg<8> 2 8 FB10_9 STD RESET edge_reg<1> 2 8 FB10_10 STD RESET edge_reg<0> 2 8 FB10_11 STD RESET epp_I/bytesel<1> 5 11 FB10_12 STD RESET epp_I/bytesel<0> 5 10 FB10_13 STD RESET state_FFd2 12 16 FB10_14 STD RESET edge_reg<9> 2 8 FB10_15 STD RESET state_FFd3 13 14 FB10_18 STD RESET Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State timebase_I/clk_cnt<14> 8 25 FB11_1 STD RESET trigcond_I/tlen_top_d 9 9 FB11_4 STD RESET timebase_I/clk_cnt<1> 9 25 FB11_6 STD RESET timebase_I/clk_cnt<5> 10 25 FB11_9 STD RESET timebase_I/clk_cnt<13> 10 25 FB11_13 STD RESET timebase_I/clk_cnt<12> 10 25 FB11_16 STD RESET timebase_I/clk_cnt<11> 10 25 FB11_18 STD RESET sample_cnt_wm 16 21 FB12_1 STD RESET sram_I/sample_cnt_int<8> 2 10 FB12_2 STD RESET sram_I/sample_cnt_int<7> 2 9 FB12_4 STD RESET sram_I/sample_cnt_int<16> 2 18 FB12_6 STD RESET sram_I/sample_cnt_int<15> 2 17 FB12_7 STD RESET sram_I/sample_cnt_int<14> 2 16 FB12_9 STD RESET sram_I/sample_cnt_int<13> 2 15 FB12_10 STD RESET sram_I/sample_cnt_int<12> 2 14 FB12_11 STD RESET sram_I/sample_cnt_int<11> 2 13 FB12_13 STD RESET sram_I/sample_cnt_int<10> 2 12 FB12_14 STD RESET sram_I/sample_cnt_int<0> 3 19 FB12_15 STD RESET clk_rd 5 12 FB12_16 STD RESET sram_I/sample_cnt_int<9> 2 11 FB12_17 STD RESET timebase_I/clk_cnt<9> 15 25 FB13_1 STD RESET timebase_I/clk_cnt<8> 14 25 FB13_3 STD RESET timebase_I/clk_cnt<4> 13 25 FB13_16 STD RESET timebase_I/clk_cnt<15> 8 25 FB14_1 STD RESET timebase_I/clk_cnt<2> 8 25 FB14_2 STD RESET timebase_I/clk_cnt<16> 6 25 FB14_4 STD RESET timebase_I/clk_cnt<17> 5 25 FB14_7 STD RESET timebase_I/clk_cnt<18> 3 25 FB14_9 STD RESET $OpTx$trigcond_I/int_vtrig_comp<2>/trigcond_I/int_vtrig_comp<2>_D2_INV$526 2 3 FB14_12 STD $OpTx$trigcond_I/int_vtrig_comp<3>/trigcond_I/int_vtrig_comp<3>_D2_INV$527 2 3 FB14_13 STD $OpTx$trigcond_I/int_vtrig_comp<4>/trigcond_I/int_vtrig_comp<4>_D2_INV$528 2 3 FB14_15 STD $OpTx$trigcond_I/int_vtrig_comp<5>/trigcond_I/int_vtrig_comp<5>_D2_INV$529 2 3 FB14_16 STD $OpTx$trigcond_I/int_vtrig_comp<6>/trigcond_I/int_vtrig_comp<6>_D2_INV$530 2 3 FB14_17 STD timebase_I/clk_2 2 20 FB14_18 STD RESET trigcond_I/int_trig_hit_reg 26 34 FB15_6 STD RESET $OpTx$trigcond_I/int_vtrig_comp<14>/trigcond_I/int_vtrig_comp<14>_D2_INV$524 2 3 FB15_9 STD $OpTx$trigcond_I/int_vtrig_comp<12>/trigcond_I/int_vtrig_comp<12>_D2_INV$523 2 3 FB15_13 STD $OpTx$trigcond_I/int_vtrig_comp<11>/trigcond_I/int_vtrig_comp<11>_D2_INV$522 2 3 FB15_16 STD $OpTx$trigcond_I/int_vtrig_comp<10>/trigcond_I/int_vtrig_comp<10>_D2_INV$521 2 3 FB15_18 STD trigcond_I/tlen_cnt<0> 20 15 FB16_15 STD RESET Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State trigcond_I/tlen_cnt<1> 16 15 FB16_18 STD RESET ** 38 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use etrg FB1_12 24 I/O I channel<4> FB2_2 9 I/O I channel<20> FB2_3 10 I/O I channel<3> FB2_5 11 I/O I channel<19> FB2_6 12 I/O I channel<2> FB2_8 13 I/O I channel<18> FB2_10 14 I/O I channel<1> FB2_12 15 I/O I channel<17> FB2_14 16 I/O I channel<0> FB2_15 17 I/O I channel<16> FB2_17 19 I/O I eclk FB3_2 28 I/O I channel<7> FB4_2 2 GTS/I/O I channel<23> FB4_5 3 GTS/I/O I channel<6> FB4_6 4 I/O I channel<22> FB4_8 5 GTS/I/O I channel<5> FB4_12 6 GTS/I/O I channel<21> FB4_14 7 I/O I clk_in FB5_8 38 GCK/I/O GCK/I channel<27> FB6_2 135 I/O I channel<11> FB6_3 136 I/O I channel<26> FB6_5 137 I/O I channel<10> FB6_6 138 I/O I channel<25> FB6_8 139 I/O I channel<9> FB6_10 140 I/O I channel<24> FB6_14 142 I/O I channel<8> FB6_15 143 GSR/I/O I channel<14> FB8_2 130 I/O I channel<29> FB8_3 131 I/O I channel<13> FB8_5 132 I/O I channel<28> FB8_8 133 I/O I channel<12> FB8_10 134 I/O I channel<31> FB10_12 126 I/O I channel<15> FB10_14 128 I/O I channel<30> FB10_17 129 I/O I drd_l FB12_2 110 I/O I dale_l FB12_10 115 I/O I dwr_l FB14_15 107 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X - Signal used as input to the macrocell logic. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 48/6 Number of signals used by logic mapping into function block: 48 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 /\4 1 FB1_1 (b) (b) (unused) 0 0 \/5 0 FB1_2 (b) (b) trigcond_I/trig_cnt<0> 10 5<- 0 0 FB1_3 (b) (b) timebase_I/clk_cnt<0> 6 1<- 0 0 FB1_4 (b) (b) trig_o 8 4<- /\1 0 FB1_5 20 I/O O (unused) 0 0 /\4 1 FB1_6 21 I/O (b) (unused) 0 0 \/5 0 FB1_7 (b) (b) (unused) 0 0 \/5 0 FB1_8 22 I/O (b) trigcond_I/trig_cnt<2> 12 10<- \/3 0 FB1_9 (b) (b) trigcond_I/trig_cnt<3> 13 8<- 0 0 FB1_10 23 I/O (b) (unused) 0 0 /\5 0 FB1_11 (b) (b) (unused) 0 0 \/5 0 FB1_12 24 I/O I (unused) 0 0 \/5 0 FB1_13 (b) (b) trigcond_I/tlen_cnt<3> 13 10<- \/2 0 FB1_14 25 I/O (b) (unused) 0 0 \/5 0 FB1_15 26 I/O (b) trigcond_I/tlen_cnt<2> 15 10<- 0 0 FB1_16 (b) (b) trigcond_I/trig_cnt<1> 11 9<- /\3 0 FB1_17 27 I/O (b) (unused) 0 0 /\5 0 FB1_18 (b) (b) Signals Used by Logic in Function Block 1: clr 17: timebase_I/clk_cnt<17> 33: trigcond_I/int_trig_hit_reg 2: extrig_en 18: timebase_I/clk_cnt<18> 34: trigcond_I/tlen_cnt<0> 3: extrig_val 19: timebase_I/clk_cnt<1> 35: trigcond_I/tlen_cnt<1> 4: inv_trig 20: timebase_I/clk_cnt<2> 36: trigcond_I/tlen_cnt<2> 5: tcnt_reg<0> 21: timebase_I/clk_cnt<3> 37: trigcond_I/tlen_cnt<3> 6: tcnt_reg<1> 22: timebase_I/clk_cnt<4> 38: trigcond_I/tlen_top_d 7: tcnt_reg<2> 23: timebase_I/clk_cnt<5> 39: trigcond_I/trig_cnt<0> 8: tcnt_reg<3> 24: timebase_I/clk_cnt<6> 40: trigcond_I/trig_cnt<1> 9: timebase_I/clk_cnt<0> 25: timebase_I/clk_cnt<7> 41: trigcond_I/trig_cnt<2> 10: timebase_I/clk_cnt<10> 26: timebase_I/clk_cnt<8> 42: trigcond_I/trig_cnt<3> 11: timebase_I/clk_cnt<11> 27: timebase_I/clk_cnt<9> 43: trigcond_I/trig_on_d 12: timebase_I/clk_cnt<12> 28: tlen_reg<0> 44: tsel_reg<0> 13: timebase_I/clk_cnt<13> 29: tlen_reg<1> 45: tsel_reg<1> 14: timebase_I/clk_cnt<14> 30: tlen_reg<2> 46: tsel_reg<2> 15: timebase_I/clk_cnt<15> 31: tlen_reg<3> 47: tsel_reg<3> 16: timebase_I/clk_cnt<16> 32: trigcond_I/extrig_int 48: tsel_reg<4> Signal 1 2 3 4 5 FB Name 0----+----0----+----0----+----0----+----0----+----0 Inputs trigcond_I/trig_cnt<0> X..........................XXXX..XXXXX............ 10 timebase_I/clk_cnt<0> X.......XXXXXXXXXXXXXXXXXXX................XXXXX.. 25 trig_o ....XXXX..............................XXXX........ 8 trigcond_I/trig_cnt<2> X..........................XXXX..XXXXXXX.......... 12 trigcond_I/trig_cnt<3> X..........................XXXX..XXXXXXXX......... 13 trigcond_I/tlen_cnt<3> XXXX.......................XXXXXXXXXX.....X....... 15 trigcond_I/tlen_cnt<2> XXXX.......................XXXXXXXXXX.....X....... 15 trigcond_I/trig_cnt<1> X..........................XXXX..XXXXXX........... 11 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 9/45 Number of signals used by logic mapping into function block: 9 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use value_reg<2> 2 0 0 3 FB2_1 (b) (b) value_reg<10> 2 0 0 3 FB2_2 9 I/O I tsel_reg<2> 2 0 0 3 FB2_3 10 I/O I tlen_reg<3> 2 0 0 3 FB2_4 (b) (b) tlen_reg<2> 2 0 0 3 FB2_5 11 I/O I tcnt_reg<3> 2 0 0 3 FB2_6 12 I/O I tcnt_reg<2> 2 0 0 3 FB2_7 (b) (b) stop 2 0 0 3 FB2_8 13 I/O I psize_reg<3> 2 0 0 3 FB2_9 (b) (b) psize_reg<2> 2 0 0 3 FB2_10 14 I/O I mask_reg<3> 2 0 0 3 FB2_11 (b) (b) mask_reg<2> 2 0 0 3 FB2_12 15 I/O I mask_reg<11> 2 0 0 3 FB2_13 (b) (b) mask_reg<10> 2 0 0 3 FB2_14 16 I/O I edge_reg<3> 2 0 0 3 FB2_15 17 I/O I edge_reg<2> 2 0 0 3 FB2_16 (b) (b) edge_reg<11> 2 0 0 3 FB2_17 19 I/O I edge_reg<10> 2 0 0 3 FB2_18 (b) (b) Signals Used by Logic in Function Block 1: dd<3>.PIN 4: epp_I/RD_l_i 7: epp_I/adr<1> 2: dd<2>.PIN 5: epp_I/WR_l_i 8: epp_I/adr<2> 3: epp_I/ALE_l_i 6: epp_I/adr<0> 9: epp_I/adr<3> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs value_reg<2> .XXXXXXXX............................... 8 value_reg<10> .XXXXXXXX............................... 8 tsel_reg<2> .XXXXXXXX............................... 8 tlen_reg<3> X.XXXXXXX............................... 8 tlen_reg<2> .XXXXXXXX............................... 8 tcnt_reg<3> X.XXXXXXX............................... 8 tcnt_reg<2> .XXXXXXXX............................... 8 stop X.XXXXXXX............................... 8 psize_reg<3> X.XXXXXXX............................... 8 psize_reg<2> .XXXXXXXX............................... 8 mask_reg<3> X.XXXXXXX............................... 8 mask_reg<2> .XXXXXXXX............................... 8 mask_reg<11> X.XXXXXXX............................... 8 mask_reg<10> .XXXXXXXX............................... 8 edge_reg<3> X.XXXXXXX............................... 8 edge_reg<2> .XXXXXXXX............................... 8 edge_reg<11> X.XXXXXXX............................... 8 edge_reg<10> .XXXXXXXX............................... 8 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB3 *********************************** Number of function block inputs used/remaining: 37/17 Number of signals used by logic mapping into function block: 37 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 /\5 0 FB3_1 (b) (b) (unused) 0 0 /\3 2 FB3_2 28 I/O I (unused) 0 0 \/5 0 FB3_3 (b) (b) (unused) 0 0 \/5 0 FB3_4 (b) (b) timebase_I/clk_cnt<10> 12 10<- \/3 0 FB3_5 (b) (b) timebase_I/clk_cnt<7> 13 8<- 0 0 FB3_6 (b) (b) (unused) 0 0 /\5 0 FB3_7 (b) (b) (unused) 0 0 \/5 0 FB3_8 (b) (b) (unused) 0 0 \/5 0 FB3_9 (b) (b) clk_ob 24 19<- 0 0 FB3_10 30 GCK/I/O GCK/O (unused) 0 0 /\5 0 FB3_11 (b) (b) (unused) 0 0 /\4 1 FB3_12 31 I/O (b) (unused) 0 0 \/5 0 FB3_13 (b) (b) clk_o 11 6<- 0 0 FB3_14 32 GCK/I/O GCK/O st<1> 3 0 /\1 1 FB3_15 33 I/O O (unused) 0 0 \/5 0 FB3_16 (b) (b) timebase_I/clk_cnt<3> 12 7<- 0 0 FB3_17 (b) (b) timebase_I/clk_cnt<6> 11 8<- /\2 0 FB3_18 (b) (b) Signals Used by Logic in Function Block 1: clk_falling_edge 14: timebase_I/clk_cnt<11> 26: timebase_I/clk_cnt<5> 2: clk_in 15: timebase_I/clk_cnt<12> 27: timebase_I/clk_cnt<6> 3: clk_rd 16: timebase_I/clk_cnt<13> 28: timebase_I/clk_cnt<7> 4: clr 17: timebase_I/clk_cnt<14> 29: timebase_I/clk_cnt<8> 5: eclk 18: timebase_I/clk_cnt<15> 30: timebase_I/clk_cnt<9> 6: state_FFd1 19: timebase_I/clk_cnt<16> 31: timebase_I/sw_read_clk_f 7: state_FFd2 20: timebase_I/clk_cnt<17> 32: timebase_I/sw_read_clk_r 8: state_FFd3 21: timebase_I/clk_cnt<18> 33: tsel_reg<0> 9: timebase_I/clk_2 22: timebase_I/clk_cnt<1> 34: tsel_reg<1> 10: timebase_I/clk_5f<1> 23: timebase_I/clk_cnt<2> 35: tsel_reg<2> 11: timebase_I/clk_5f<2> 24: timebase_I/clk_cnt<3> 36: tsel_reg<3> 12: timebase_I/clk_cnt<0> 25: timebase_I/clk_cnt<4> 37: tsel_reg<4> 13: timebase_I/clk_cnt<10> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs timebase_I/clk_cnt<10> ...X.......XXXXXXXXXXXXXXXXXXX..XXXXX... 25 timebase_I/clk_cnt<7> ...X.......XXXXXXXXXXXXXXXXXXX..XXXXX... 25 clk_ob XXX.X...XXX..........XX.......XXXXXXX... 16 clk_o .XX.X...XXX..........XX.........XXXXX... 13 st<1> ...X.XXX................................ 4 timebase_I/clk_cnt<3> ...X.......XXXXXXXXXXXXXXXXXXX..XXXXX... 25 timebase_I/clk_cnt<6> ...X.......XXXXXXXXXXXXXXXXXXX..XXXXX... 25 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** Number of function block inputs used/remaining: 10/44 Number of signals used by logic mapping into function block: 10 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use value_reg<7> 2 0 0 3 FB4_1 (b) (b) value_reg<4> 2 0 0 3 FB4_2 2 GTS/I/O I value_reg<15> 2 0 0 3 FB4_3 (b) (b) value_reg<12> 2 0 0 3 FB4_4 (b) (b) tsel_reg<4> 2 0 0 3 FB4_5 3 GTS/I/O I run 2 0 0 3 FB4_6 4 I/O I pretrig_off 2 0 0 3 FB4_7 (b) (b) mask_reg<7> 2 0 0 3 FB4_8 5 GTS/I/O I mask_reg<4> 2 0 0 3 FB4_9 (b) (b) mask_reg<1> 2 0 0 3 FB4_10 (b) (b) mask_reg<15> 2 0 0 3 FB4_11 (b) (b) mask_reg<12> 2 0 0 3 FB4_12 6 GTS/I/O I inv_trig 2 0 0 3 FB4_13 (b) (b) epp_I/auto_inc 2 0 0 3 FB4_14 7 I/O I edge_reg<7> 2 0 0 3 FB4_15 (b) (b) edge_reg<4> 2 0 0 3 FB4_16 (b) (b) edge_reg<15> 2 0 0 3 FB4_17 (b) (b) edge_reg<12> 2 0 0 3 FB4_18 (b) (b) Signals Used by Logic in Function Block 1: dd<1>.PIN 5: epp_I/RD_l_i 8: epp_I/adr<1> 2: dd<7>.PIN 6: epp_I/WR_l_i 9: epp_I/adr<2> 3: dd<4>.PIN 7: epp_I/adr<0> 10: epp_I/adr<3> 4: epp_I/ALE_l_i Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs value_reg<7> .X.XXXXXXX.............................. 8 value_reg<4> ..XXXXXXXX.............................. 8 value_reg<15> .X.XXXXXXX.............................. 8 value_reg<12> ..XXXXXXXX.............................. 8 tsel_reg<4> ..XXXXXXXX.............................. 8 run .X.XXXXXXX.............................. 8 pretrig_off ..XXXXXXXX.............................. 8 mask_reg<7> .X.XXXXXXX.............................. 8 mask_reg<4> ..XXXXXXXX.............................. 8 mask_reg<1> X..XXXXXXX.............................. 8 mask_reg<15> .X.XXXXXXX.............................. 8 mask_reg<12> ..XXXXXXXX.............................. 8 inv_trig .X.XXXXXXX.............................. 8 epp_I/auto_inc ..XXXXXXXX.............................. 8 edge_reg<7> .X.XXXXXXX.............................. 8 edge_reg<4> ..XXXXXXXX.............................. 8 edge_reg<15> .X.XXXXXXX.............................. 8 edge_reg<12> ..XXXXXXXX.............................. 8 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB5 *********************************** Number of function block inputs used/remaining: 53/1 Number of signals used by logic mapping into function block: 53 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB5_1 (b) st<2> 3 0 0 2 FB5_2 34 I/O O (unused) 0 0 0 5 FB5_3 (b) (unused) 0 0 0 5 FB5_4 (b) st<3> 3 0 0 2 FB5_5 35 I/O O (unused) 0 0 \/5 0 FB5_6 (b) (b) (unused) 0 0 \/5 0 FB5_7 (b) (b) trigcond_I/int_etrig_hit_reg 25 20<- 0 0 FB5_8 38 GCK/I/O GCK/I (unused) 0 0 /\5 0 FB5_9 (b) (b) trigcond_I/extrig_int 1 1<- /\5 0 FB5_10 39 I/O (b) trigcond_I/trig_on_d 2 0 /\1 2 FB5_11 (b) (b) sram_d<31> 2 0 0 3 FB5_12 40 I/O I/O trig_on 2 0 0 3 FB5_13 (b) (b) sram_d<30> 2 0 0 3 FB5_14 41 I/O I/O sram_d<29> 2 0 0 3 FB5_15 43 I/O I/O sram_I/sample_cnt_int<1> 2 0 0 3 FB5_16 (b) (b) sram_d<28> 2 0 0 3 FB5_17 44 I/O I/O sample_cnt_en 2 0 0 3 FB5_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$trigcond_I/int_vtrig_comp<10>/trigcond_I/int_vtrig_comp<10>_D2_INV$521 19: channel<31> 37: edge_reg<9> 2: $OpTx$trigcond_I/int_vtrig_comp<11>/trigcond_I/int_vtrig_comp<11>_D2_INV$522 20: channel<7> 38: etrg 3: $OpTx$trigcond_I/int_vtrig_comp<12>/trigcond_I/int_vtrig_comp<12>_D2_INV$523 21: clr 39: mask_reg<0> 4: $OpTx$trigcond_I/int_vtrig_comp<14>/trigcond_I/int_vtrig_comp<14>_D2_INV$524 22: edge_reg<0> 40: mask_reg<13> 5: $OpTx$trigcond_I/int_vtrig_comp<15>/trigcond_I/int_vtrig_comp<15>_D2_INV$525 23: edge_reg<10> 41: mask_reg<1> 6: $OpTx$trigcond_I/int_vtrig_comp<2>/trigcond_I/int_vtrig_comp<2>_D2_INV$526 24: edge_reg<11> 42: mask_reg<7> 7: $OpTx$trigcond_I/int_vtrig_comp<3>/trigcond_I/int_vtrig_comp<3>_D2_INV$527 25: edge_reg<12> 43: sample_cnt_en 8: $OpTx$trigcond_I/int_vtrig_comp<4>/trigcond_I/int_vtrig_comp<4>_D2_INV$528 26: edge_reg<13> 44: sram_I/sample_cnt_int<0> 9: $OpTx$trigcond_I/int_vtrig_comp<5>/trigcond_I/int_vtrig_comp<5>_D2_INV$529 27: edge_reg<14> 45: st<3> 10: $OpTx$trigcond_I/int_vtrig_comp<6>/trigcond_I/int_vtrig_comp<6>_D2_INV$530 28: edge_reg<15> 46: state_FFd1 11: $OpTx$trigcond_I/int_vtrig_comp<8>/trigcond_I/int_vtrig_comp<8>_D2_INV$531 29: edge_reg<1> 47: state_FFd2 12: $OpTx$trigcond_I/int_vtrig_comp<9>/trigcond_I/int_vtrig_comp<9>_D2_INV$532 30: edge_reg<2> 48: state_FFd3 13: channel<0> 31: edge_reg<3> 49: trig_on 14: channel<13> 32: edge_reg<4> 50: value_reg<0> 15: channel<1> 33: edge_reg<5> 51: value_reg<13> 16: channel<28> 34: edge_reg<6> 52: value_reg<1> 17: channel<29> 35: edge_reg<7> 53: value_reg<7> 18: channel<30> 36: edge_reg<8> Signal 1 2 3 4 5 6 FB Name 0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs st<2> ....................X........................XXX............ 4 st<3> ....................X........................XXX............ 4 trigcond_I/int_etrig_hit_reg XXXXXXXXXXXXXXX....XXXXXXXXXXXXXXXXXX.XXXX.......XXXX....... 41 trigcond_I/extrig_int .....................................X...................... 1 trigcond_I/trig_on_d ....................X...........................X........... 2 sram_d<31> ..................X.........................X............... 2 trig_on ....................X.........................XX............ 3 sram_d<30> .................X..........................X............... 2 sram_d<29> ................X...........................X............... 2 sram_I/sample_cnt_int<1> ....................X.....................XX................ 3 sram_d<28> ...............X............................X............... 2 sample_cnt_en ....................X.........................X............. 2 0----+----1----+----2----+----3----+----4----+----5----+----6 0 0 0 0 0 0 *********************************** FB6 *********************************** Number of function block inputs used/remaining: 10/44 Number of signals used by logic mapping into function block: 10 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use value_reg<9> 2 0 0 3 FB6_1 (b) (b) value_reg<8> 2 0 0 3 FB6_2 135 I/O I value_reg<3> 2 0 0 3 FB6_3 136 I/O I value_reg<1> 2 0 0 3 FB6_4 (b) (b) value_reg<11> 2 0 0 3 FB6_5 137 I/O I value_reg<0> 2 0 0 3 FB6_6 138 I/O I tsel_reg<3> 2 0 0 3 FB6_7 (b) (b) tsel_reg<1> 2 0 0 3 FB6_8 139 I/O I tsel_reg<0> 2 0 0 3 FB6_9 (b) (b) tlen_reg<1> 2 0 0 3 FB6_10 140 I/O I tlen_reg<0> 2 0 0 3 FB6_11 (b) (b) tcnt_reg<1> 2 0 0 3 FB6_12 (b) (b) tcnt_reg<0> 2 0 0 3 FB6_13 (b) (b) psize_reg<1> 2 0 0 3 FB6_14 142 I/O I psize_reg<0> 2 0 0 3 FB6_15 143 GSR/I/O I mask_reg<9> 2 0 0 3 FB6_16 (b) (b) mask_reg<8> 2 0 0 3 FB6_17 (b) (b) epp_I/adr<0> 2 0 0 3 FB6_18 (b) (b) Signals Used by Logic in Function Block 1: dd<3>.PIN 5: epp_I/RD_l_i 8: epp_I/adr<1> 2: dd<1>.PIN 6: epp_I/WR_l_i 9: epp_I/adr<2> 3: dd<0>.PIN 7: epp_I/adr<0> 10: epp_I/adr<3> 4: epp_I/ALE_l_i Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs value_reg<9> .X.XXXXXXX.............................. 8 value_reg<8> ..XXXXXXXX.............................. 8 value_reg<3> X..XXXXXXX.............................. 8 value_reg<1> .X.XXXXXXX.............................. 8 value_reg<11> X..XXXXXXX.............................. 8 value_reg<0> ..XXXXXXXX.............................. 8 tsel_reg<3> X..XXXXXXX.............................. 8 tsel_reg<1> .X.XXXXXXX.............................. 8 tsel_reg<0> ..XXXXXXXX.............................. 8 tlen_reg<1> .X.XXXXXXX.............................. 8 tlen_reg<0> ..XXXXXXXX.............................. 8 tcnt_reg<1> .X.XXXXXXX.............................. 8 tcnt_reg<0> ..XXXXXXXX.............................. 8 psize_reg<1> .X.XXXXXXX.............................. 8 psize_reg<0> ..XXXXXXXX.............................. 8 mask_reg<9> .X.XXXXXXX.............................. 8 mask_reg<8> ..XXXXXXXX.............................. 8 epp_I/adr<0> ..XXXX.................................. 4 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB7 *********************************** Number of function block inputs used/remaining: 14/40 Number of signals used by logic mapping into function block: 14 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use value_reg<6> 2 0 0 3 FB7_1 (b) (b) value_reg<5> 2 0 0 3 FB7_2 (b) (b) sram_d<27> 2 0 0 3 FB7_3 45 I/O I/O value_reg<14> 2 0 0 3 FB7_4 (b) (b) sram_d<26> 2 0 0 3 FB7_5 46 I/O I/O value_reg<13> 2 0 0 3 FB7_6 (b) (b) mask_reg<6> 2 0 0 3 FB7_7 (b) (b) mask_reg<5> 2 0 0 3 FB7_8 (b) (b) mask_reg<14> 2 0 0 3 FB7_9 (b) (b) mask_reg<13> 2 0 0 3 FB7_10 (b) (b) edge_reg<6> 2 0 0 3 FB7_11 (b) (b) sram_d<25> 2 0 0 3 FB7_12 48 I/O I/O edge_reg<5> 2 0 0 3 FB7_13 (b) (b) edge_reg<14> 2 0 0 3 FB7_14 (b) (b) sram_d<24> 2 0 0 3 FB7_15 49 I/O I/O edge_reg<13> 2 0 0 3 FB7_16 (b) (b) clr 2 0 0 3 FB7_17 (b) (b) clk_falling_edge 2 0 0 3 FB7_18 (b) (b) Signals Used by Logic in Function Block 1: dd<6>.PIN 6: channel<27> 11: epp_I/adr<1> 2: dd<5>.PIN 7: epp_I/ALE_l_i 12: epp_I/adr<2> 3: channel<24> 8: epp_I/RD_l_i 13: epp_I/adr<3> 4: channel<25> 9: epp_I/WR_l_i 14: st<3> 5: channel<26> 10: epp_I/adr<0> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs value_reg<6> X.....XXXXXXX........................... 8 value_reg<5> .X....XXXXXXX........................... 8 sram_d<27> .....X.......X.......................... 2 value_reg<14> X.....XXXXXXX........................... 8 sram_d<26> ....X........X.......................... 2 value_reg<13> .X....XXXXXXX........................... 8 mask_reg<6> X.....XXXXXXX........................... 8 mask_reg<5> .X....XXXXXXX........................... 8 mask_reg<14> X.....XXXXXXX........................... 8 mask_reg<13> .X....XXXXXXX........................... 8 edge_reg<6> X.....XXXXXXX........................... 8 sram_d<25> ...X.........X.......................... 2 edge_reg<5> .X....XXXXXXX........................... 8 edge_reg<14> X.....XXXXXXX........................... 8 sram_d<24> ..X..........X.......................... 2 edge_reg<13> .X....XXXXXXX........................... 8 clr X.....XXXXXXX........................... 8 clk_falling_edge .X....XXXXXXX........................... 8 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB8 *********************************** Number of function block inputs used/remaining: 25/29 Number of signals used by logic mapping into function block: 25 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB8_1 (b) (unused) 0 0 0 5 FB8_2 130 I/O I epp_I/d_rd_i_d 1 0 0 4 FB8_3 131 I/O I epp_I/WR_l_i 1 0 0 4 FB8_4 (b) (b) epp_I/RD_l_i 1 0 0 4 FB8_5 132 I/O I epp_I/ALE_l_i 1 0 0 4 FB8_6 (b) (b) $OpTx$$OpTx$FX_DC$187_INV$520 1 0 0 4 FB8_7 (b) (b) timebase_I/sw_read_clk_r 2 0 0 3 FB8_8 133 I/O I timebase_I/sw_read_clk_f 2 0 0 3 FB8_9 (b) (b) timebase_I/clk_5f<2> 2 0 0 3 FB8_10 134 I/O I timebase_I/clk_5f<0> 2 0 0 3 FB8_11 (b) (b) epp_I/adr<3> 2 0 0 3 FB8_12 (b) (b) epp_I/adr<2> 2 0 0 3 FB8_13 (b) (b) epp_I/adr<1> 2 0 0 3 FB8_14 (b) (b) $OpTx$trigcond_I/int_vtrig_comp<9>/trigcond_I/int_vtrig_comp<9>_D2_INV$532 2 0 0 3 FB8_15 (b) (b) $OpTx$trigcond_I/int_vtrig_comp<8>/trigcond_I/int_vtrig_comp<8>_D2_INV$531 2 0 0 3 FB8_16 (b) (b) $OpTx$trigcond_I/int_vtrig_comp<15>/trigcond_I/int_vtrig_comp<15>_D2_INV$525 2 0 0 3 FB8_17 (b) (b) timebase_I/clk_5f<1> 3 0 0 2 FB8_18 (b) (b) Signals Used by Logic in Function Block 1: dd<3>.PIN 10: drd_l 18: mask_reg<8> 2: dd<2>.PIN 11: dwr_l 19: mask_reg<9> 3: dd<1>.PIN 12: epp_I/ALE_l_i 20: timebase_I/clk_5f<0> 4: channel<15> 13: epp_I/RD_l_i 21: timebase_I/clk_5f<1> 5: channel<8> 14: epp_I/WR_l_i 22: timebase_I/clk_5f<2> 6: channel<9> 15: epp_I/adr<0> 23: value_reg<15> 7: clr 16: epp_I/adr<1> 24: value_reg<8> 8: dale_l 17: mask_reg<15> 25: value_reg<9> 9: done Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs epp_I/d_rd_i_d ...........XXX.......................... 3 epp_I/WR_l_i ..........X............................. 1 epp_I/RD_l_i .........X.............................. 1 epp_I/ALE_l_i .......X................................ 1 $OpTx$$OpTx$FX_DC$187_INV$520 ..............XX........................ 2 timebase_I/sw_read_clk_r ......X.X............................... 2 timebase_I/sw_read_clk_f ......X.X............................... 2 timebase_I/clk_5f<2> ......X............XX................... 3 timebase_I/clk_5f<0> ......X............XXX.................. 4 epp_I/adr<3> X..........XXX.......................... 4 epp_I/adr<2> .X.........XXX.......................... 4 epp_I/adr<1> ..X........XXX.......................... 4 $OpTx$trigcond_I/int_vtrig_comp<9>/trigcond_I/int_vtrig_comp<9>_D2_INV$532 .....X............X.....X............... 3 $OpTx$trigcond_I/int_vtrig_comp<8>/trigcond_I/int_vtrig_comp<8>_D2_INV$531 ....X............X.....X................ 3 $OpTx$trigcond_I/int_vtrig_comp<15>/trigcond_I/int_vtrig_comp<15>_D2_INV$525 ...X............X.....X................. 3 timebase_I/clk_5f<1> ......X............XXX.................. 4 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB9 *********************************** Number of function block inputs used/remaining: 48/6 Number of signals used by logic mapping into function block: 48 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 /\5 0 FB9_1 (b) (b) sram_d<23> 2 0 /\2 1 FB9_2 50 I/O I/O sram_d<22> 2 0 0 3 FB9_3 51 I/O I/O sram_I/sample_cnt_int<6> 2 0 0 3 FB9_4 (b) (b) sram_d<21> 2 0 0 3 FB9_5 52 I/O I/O sram_d<20> 2 0 0 3 FB9_6 53 I/O I/O sram_I/sample_cnt_int<5> 2 0 0 3 FB9_7 (b) (b) sram_d<19> 2 0 0 3 FB9_8 54 I/O I/O sram_I/sample_cnt_int<4> 2 0 0 3 FB9_9 (b) (b) sram_I/sample_cnt_int<3> 2 0 0 3 FB9_10 (b) (b) sram_d<18> 2 0 0 3 FB9_11 56 I/O I/O sram_d<17> 2 0 0 3 FB9_12 57 I/O I/O sram_I/sample_cnt_int<2> 2 0 0 3 FB9_13 (b) (b) sram_d<16> 2 0 0 3 FB9_14 58 I/O I/O done 2 0 0 3 FB9_15 (b) (b) adr_cnt_en 2 0 0 3 FB9_16 (b) (b) sram_adr<5> 2 0 \/3 0 FB9_17 59 I/O O state_FFd1 15 10<- 0 0 FB9_18 (b) (b) Signals Used by Logic in Function Block 1: adr_cnt_en 17: sram_I/sample_cnt_int<12> 33: sram_adr<2> 2: channel<16> 18: sram_I/sample_cnt_int<13> 34: sram_adr<3> 3: channel<17> 19: sram_I/sample_cnt_int<14> 35: sram_adr<4> 4: channel<18> 20: sram_I/sample_cnt_int<15> 36: st<3> 5: channel<19> 21: sram_I/sample_cnt_int<16> 37: state_FFd1 6: channel<20> 22: sram_I/sample_cnt_int<1> 38: state_FFd2 7: channel<21> 23: sram_I/sample_cnt_int<2> 39: state_FFd3 8: channel<22> 24: sram_I/sample_cnt_int<3> 40: stop 9: channel<23> 25: sram_I/sample_cnt_int<4> 41: tcnt_reg<0> 10: clr 26: sram_I/sample_cnt_int<5> 42: tcnt_reg<1> 11: pretrig_off 27: sram_I/sample_cnt_int<6> 43: tcnt_reg<2> 12: sample_cnt_en 28: sram_I/sample_cnt_int<7> 44: tcnt_reg<3> 13: sample_cnt_wm 29: sram_I/sample_cnt_int<8> 45: trigcond_I/trig_cnt<0> 14: sram_I/sample_cnt_int<0> 30: sram_I/sample_cnt_int<9> 46: trigcond_I/trig_cnt<1> 15: sram_I/sample_cnt_int<10> 31: sram_adr<0> 47: trigcond_I/trig_cnt<2> 16: sram_I/sample_cnt_int<11> 32: sram_adr<1> 48: trigcond_I/trig_cnt<3> Signal 1 2 3 4 5 FB Name 0----+----0----+----0----+----0----+----0----+----0 Inputs sram_d<23> ........X..........................X.............. 2 sram_d<22> .......X...........................X.............. 2 sram_I/sample_cnt_int<6> .........X.X.X.......XXXXX........................ 8 sram_d<21> ......X............................X.............. 2 sram_d<20> .....X.............................X.............. 2 sram_I/sample_cnt_int<5> .........X.X.X.......XXXX......................... 7 sram_d<19> ....X..............................X.............. 2 sram_I/sample_cnt_int<4> .........X.X.X.......XXX.......................... 6 sram_I/sample_cnt_int<3> .........X.X.X.......XX........................... 5 sram_d<18> ...X...............................X.............. 2 sram_d<17> ..X................................X.............. 2 sram_I/sample_cnt_int<2> .........X.X.X.......X............................ 4 sram_d<16> .X.................................X.............. 2 done .........X..........................X.X........... 3 adr_cnt_en .........X..........................XXX........... 4 sram_adr<5> X.............................XXXXX............... 6 state_FFd1 .........XX.XXXXXXXXXXXXXXXXXX......XXXXXXXXXXXX.. 32 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 *********************************** FB10 *********************************** Number of function block inputs used/remaining: 46/8 Number of signals used by logic mapping into function block: 46 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 \/5 0 FB10_1 (b) (b) dd<4> 13 8<- 0 0 FB10_2 117 I/O I/O dd<5> 7 3<- /\1 0 FB10_3 118 I/O I/O mask_reg<0> 2 0 /\3 0 FB10_4 (b) (b) dd<6> 7 2<- 0 0 FB10_5 119 I/O I/O dd<7> 6 3<- /\2 0 FB10_6 120 I/O I/O extrig_val 2 0 /\3 0 FB10_7 (b) (b) extrig_en 2 0 0 3 FB10_8 121 I/O (b) edge_reg<8> 2 0 0 3 FB10_9 (b) (b) edge_reg<1> 2 0 \/1 2 FB10_10 124 I/O (b) edge_reg<0> 2 1<- \/4 0 FB10_11 125 I/O (b) epp_I/bytesel<1> 5 4<- \/4 0 FB10_12 126 I/O I epp_I/bytesel<0> 5 4<- \/4 0 FB10_13 (b) (b) state_FFd2 12 7<- 0 0 FB10_14 128 I/O I edge_reg<9> 2 0 /\3 0 FB10_15 (b) (b) (unused) 0 0 \/5 0 FB10_16 (b) (b) (unused) 0 0 \/5 0 FB10_17 129 I/O I state_FFd3 13 10<- \/2 0 FB10_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$$OpTx$FX_DC$187_INV$520 17: sram_d<6>.PIN 32: pretrig_off 2: dd<1>.PIN 18: sram_d<5>.PIN 33: run 3: dd<0>.PIN 19: sram_d<4>.PIN 34: sample_cnt_wm 4: sram_d<31>.PIN 20: clr 35: state_FFd1 5: sram_d<30>.PIN 21: done 36: state_FFd2 6: sram_d<29>.PIN 22: epp_I/ALE_l_i 37: state_FFd3 7: sram_d<28>.PIN 23: epp_I/RD_l_i 38: stop 8: sram_d<23>.PIN 24: epp_I/WR_l_i 39: tcnt_reg<0> 9: sram_d<22>.PIN 25: epp_I/adr<0> 40: tcnt_reg<1> 10: sram_d<21>.PIN 26: epp_I/adr<1> 41: tcnt_reg<2> 11: sram_d<20>.PIN 27: epp_I/adr<2> 42: tcnt_reg<3> 12: sram_d<15>.PIN 28: epp_I/adr<3> 43: trigcond_I/trig_cnt<0> 13: sram_d<14>.PIN 29: epp_I/bytesel<0> 44: trigcond_I/trig_cnt<1> 14: sram_d<13>.PIN 30: epp_I/bytesel<1> 45: trigcond_I/trig_cnt<2> 15: sram_d<12>.PIN 31: epp_I/d_rd_i_d 46: trigcond_I/trig_cnt<3> 16: sram_d<7>.PIN Signal 1 2 3 4 5 FB Name 0----+----0----+----0----+----0----+----0----+----0 Inputs dd<4> X.....X...X...X...X..XXXXXXXXX........XXXXXXXX.... 22 dd<5> X....X...X...X...X.X.XXXXXXXXX.................... 15 mask_reg<0> ..X..................XXXXXXX...................... 8 dd<6> X...X...X...X...X....XXXXXXXXX..X................. 15 dd<7> X..X...X...X...X....XXXXXXXXXX.................... 15 extrig_val ..X..................XXXXXXX...................... 8 extrig_en .X...................XXXXXXX...................... 8 edge_reg<8> ..X..................XXXXXXX...................... 8 edge_reg<1> .X...................XXXXXXX...................... 8 edge_reg<0> ..X..................XXXXXXX...................... 8 epp_I/bytesel<1> .X...................XXXXXXXXXX................... 11 epp_I/bytesel<0> ..X..................XXXXXXXX.X................... 10 state_FFd2 ...................X...........XXXXXXXXXXXXXXX.... 16 edge_reg<9> .X...................XXXXXXX...................... 8 state_FFd3 ...................X............X.XXXXXXXXXXXX.... 14 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 *********************************** FB11 *********************************** Number of function block inputs used/remaining: 41/13 Number of signals used by logic mapping into function block: 41 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use timebase_I/clk_cnt<14> 8 5<- /\2 0 FB11_1 (b) (b) (unused) 0 0 /\5 0 FB11_2 (b) (b) sram_adr<4> 2 0 \/3 0 FB11_3 60 I/O O trigcond_I/tlen_top_d 9 4<- 0 0 FB11_4 (b) (b) sram_adr<3> 2 0 /\1 2 FB11_5 61 I/O O timebase_I/clk_cnt<1> 9 4<- 0 0 FB11_6 (b) (b) (unused) 0 0 /\4 1 FB11_7 (b) (b) (unused) 0 0 \/2 3 FB11_8 (b) (b) timebase_I/clk_cnt<5> 10 5<- 0 0 FB11_9 (b) (b) sram_adr<2> 2 0 /\3 0 FB11_10 64 I/O O sram_adr<1> 2 0 0 3 FB11_11 66 I/O O sram_adr<0> 1 0 \/3 1 FB11_12 68 I/O O timebase_I/clk_cnt<13> 10 5<- 0 0 FB11_13 (b) (b) sram_adr<6> 2 0 /\2 1 FB11_14 69 I/O O (unused) 0 0 \/5 0 FB11_15 (b) (b) timebase_I/clk_cnt<12> 10 5<- 0 0 FB11_16 (b) (b) sram_adr<7> 2 0 \/3 0 FB11_17 70 I/O O timebase_I/clk_cnt<11> 10 5<- 0 0 FB11_18 (b) (b) Signals Used by Logic in Function Block 1: adr_cnt_en 15: timebase_I/clk_cnt<14> 29: tlen_reg<0> 2: clr 16: timebase_I/clk_cnt<15> 30: tlen_reg<1> 3: sram_adr<0> 17: timebase_I/clk_cnt<16> 31: tlen_reg<2> 4: sram_adr<1> 18: timebase_I/clk_cnt<17> 32: tlen_reg<3> 5: sram_adr<2> 19: timebase_I/clk_cnt<18> 33: trigcond_I/tlen_cnt<0> 6: sram_adr<3> 20: timebase_I/clk_cnt<1> 34: trigcond_I/tlen_cnt<1> 7: sram_adr<4> 21: timebase_I/clk_cnt<2> 35: trigcond_I/tlen_cnt<2> 8: sram_adr<5> 22: timebase_I/clk_cnt<3> 36: trigcond_I/tlen_cnt<3> 9: sram_adr<6> 23: timebase_I/clk_cnt<4> 37: tsel_reg<0> 10: timebase_I/clk_cnt<0> 24: timebase_I/clk_cnt<5> 38: tsel_reg<1> 11: timebase_I/clk_cnt<10> 25: timebase_I/clk_cnt<6> 39: tsel_reg<2> 12: timebase_I/clk_cnt<11> 26: timebase_I/clk_cnt<7> 40: tsel_reg<3> 13: timebase_I/clk_cnt<12> 27: timebase_I/clk_cnt<8> 41: tsel_reg<4> 14: timebase_I/clk_cnt<13> 28: timebase_I/clk_cnt<9> Signal 1 2 3 4 5 FB Name 0----+----0----+----0----+----0----+----0----+----0 Inputs timebase_I/clk_cnt<14> .X.......XXXXXXXXXXXXXXXXXXX........XXXXX......... 25 sram_adr<4> X.XXXX............................................ 5 trigcond_I/tlen_top_d .X..........................XXXXXXXX.............. 9 sram_adr<3> X.XXX............................................. 4 timebase_I/clk_cnt<1> .X.......XXXXXXXXXXXXXXXXXXX........XXXXX......... 25 timebase_I/clk_cnt<5> .X.......XXXXXXXXXXXXXXXXXXX........XXXXX......... 25 sram_adr<2> X.XX.............................................. 3 sram_adr<1> X.X............................................... 2 sram_adr<0> X................................................. 1 timebase_I/clk_cnt<13> .X.......XXXXXXXXXXXXXXXXXXX........XXXXX......... 25 sram_adr<6> X.XXXXXX.......................................... 7 timebase_I/clk_cnt<12> .X.......XXXXXXXXXXXXXXXXXXX........XXXXX......... 25 sram_adr<7> X.XXXXXXX......................................... 8 timebase_I/clk_cnt<11> .X.......XXXXXXXXXXXXXXXXXXX........XXXXX......... 25 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 *********************************** FB12 *********************************** Number of function block inputs used/remaining: 52/2 Number of signals used by logic mapping into function block: 52 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use sample_cnt_wm 16 11<- 0 0 FB12_1 (b) (b) sram_I/sample_cnt_int<8> 2 0 /\3 0 FB12_2 110 I/O I dd<0> 6 1<- 0 0 FB12_3 111 I/O I/O sram_I/sample_cnt_int<7> 2 0 /\1 2 FB12_4 (b) (b) dd<1> 6 1<- 0 0 FB12_5 112 I/O I/O sram_I/sample_cnt_int<16> 2 0 /\1 2 FB12_6 (b) (b) sram_I/sample_cnt_int<15> 2 0 \/1 2 FB12_7 (b) (b) dd<2> 6 1<- 0 0 FB12_8 113 I/O I/O sram_I/sample_cnt_int<14> 2 0 0 3 FB12_9 (b) (b) sram_I/sample_cnt_int<13> 2 0 0 3 FB12_10 115 I/O I sram_I/sample_cnt_int<12> 2 0 \/3 0 FB12_11 (b) (b) dd<3> 12 7<- 0 0 FB12_12 116 I/O I/O sram_I/sample_cnt_int<11> 2 1<- /\4 0 FB12_13 (b) (b) sram_I/sample_cnt_int<10> 2 0 /\1 2 FB12_14 (b) (b) sram_I/sample_cnt_int<0> 3 0 0 2 FB12_15 (b) (b) clk_rd 5 0 0 0 FB12_16 (b) (b) sram_I/sample_cnt_int<9> 2 0 \/3 0 FB12_17 (b) (b) (unused) 0 0 \/5 0 FB12_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$$OpTx$FX_DC$187_INV$520 19: clr 36: sram_I/sample_cnt_int<0> 2: sram_d<27>.PIN 20: epp_I/ALE_l_i 37: sram_I/sample_cnt_int<10> 3: sram_d<26>.PIN 21: epp_I/RD_l_i 38: sram_I/sample_cnt_int<11> 4: sram_d<25>.PIN 22: epp_I/WR_l_i 39: sram_I/sample_cnt_int<12> 5: sram_d<24>.PIN 23: epp_I/adr<0> 40: sram_I/sample_cnt_int<13> 6: sram_d<19>.PIN 24: epp_I/adr<1> 41: sram_I/sample_cnt_int<14> 7: sram_d<18>.PIN 25: epp_I/adr<2> 42: sram_I/sample_cnt_int<15> 8: sram_d<17>.PIN 26: epp_I/adr<3> 43: sram_I/sample_cnt_int<16> 9: sram_d<16>.PIN 27: epp_I/auto_inc 44: sram_I/sample_cnt_int<1> 10: sram_d<11>.PIN 28: epp_I/bytesel<0> 45: sram_I/sample_cnt_int<2> 11: sram_d<10>.PIN 29: epp_I/bytesel<1> 46: sram_I/sample_cnt_int<3> 12: sram_d<9>.PIN 30: epp_I/d_rd_i_d 47: sram_I/sample_cnt_int<4> 13: sram_d<8>.PIN 31: psize_reg<0> 48: sram_I/sample_cnt_int<5> 14: sram_d<3>.PIN 32: psize_reg<1> 49: sram_I/sample_cnt_int<6> 15: sram_d<2>.PIN 33: psize_reg<2> 50: sram_I/sample_cnt_int<7> 16: sram_d<1>.PIN 34: psize_reg<3> 51: sram_I/sample_cnt_int<8> 17: sram_d<0>.PIN 35: sample_cnt_en 52: sram_I/sample_cnt_int<9> 18: dd<5>.PIN Signal 1 2 3 4 5 6 FB Name 0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs sample_cnt_wm ..............................XXXX.XXXXXXXXXXXXXXXXX........ 21 sram_I/sample_cnt_int<8> ..................X...............XX.......XXXXXXX.......... 10 dd<0> X...X...X...X...X..XXXXXXX.XX............................... 14 sram_I/sample_cnt_int<7> ..................X...............XX.......XXXXXX........... 9 dd<1> X..X...X...X...X...XXXXXXX.XX............................... 14 sram_I/sample_cnt_int<16> ..................X...............XXXXXXXX.XXXXXXXXX........ 18 sram_I/sample_cnt_int<15> ..................X...............XXXXXXX..XXXXXXXXX........ 17 dd<2> X.X...X...X...X....XXXXXXX.XX............................... 14 sram_I/sample_cnt_int<14> ..................X...............XXXXXX...XXXXXXXXX........ 16 sram_I/sample_cnt_int<13> ..................X...............XXXXX....XXXXXXXXX........ 15 sram_I/sample_cnt_int<12> ..................X...............XXXX.....XXXXXXXXX........ 14 dd<3> XX...X...X...X.....XXXXXXX.XX......XXXXXXXXXXXXXXXXX........ 31 sram_I/sample_cnt_int<11> ..................X...............XXX......XXXXXXXXX........ 13 sram_I/sample_cnt_int<10> ..................X...............XX.......XXXXXXXXX........ 12 sram_I/sample_cnt_int<0> ..................X...............XXXXXXXXXXXXXXXXXX........ 19 clk_rd .................X.XXXXXXXXXXX.............................. 12 sram_I/sample_cnt_int<9> ..................X...............XX.......XXXXXXXX......... 11 0----+----1----+----2----+----3----+----4----+----5----+----6 0 0 0 0 0 0 *********************************** FB13 *********************************** Number of function block inputs used/remaining: 46/8 Number of signals used by logic mapping into function block: 46 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use timebase_I/clk_cnt<9> 15 10<- 0 0 FB13_1 (b) (b) sram_ce_l 1 1<- /\5 0 FB13_2 71 I/O O timebase_I/clk_cnt<8> 14 10<- /\1 0 FB13_3 (b) (b) (unused) 0 0 /\5 0 FB13_4 (b) (b) (unused) 0 0 /\5 0 FB13_5 (b) (b) (unused) 0 0 \/5 0 FB13_6 (b) (b) (unused) 0 0 \/5 0 FB13_7 (b) (b) sram_clk 24 19<- 0 0 FB13_8 74 I/O O (unused) 0 0 /\5 0 FB13_9 (b) (b) (unused) 0 0 /\4 1 FB13_10 (b) (b) sram_we_l 3 0 0 2 FB13_11 75 I/O O (unused) 0 0 0 5 FB13_12 (b) (unused) 0 0 0 5 FB13_13 (b) sram_oe_l 3 0 \/1 1 FB13_14 76 I/O O sram_adsc_l 1 1<- \/5 0 FB13_15 77 I/O O timebase_I/clk_cnt<4> 13 8<- 0 0 FB13_16 (b) (b) sram_adr<8> 2 0 /\3 0 FB13_17 78 I/O O (unused) 0 0 \/5 0 FB13_18 (b) (b) Signals Used by Logic in Function Block 1: adr_cnt_en 17: state_FFd3 32: timebase_I/clk_cnt<2> 2: clk_falling_edge 18: timebase_I/clk_2 33: timebase_I/clk_cnt<3> 3: clk_in 19: timebase_I/clk_5f<1> 34: timebase_I/clk_cnt<4> 4: clk_rd 20: timebase_I/clk_5f<2> 35: timebase_I/clk_cnt<5> 5: clr 21: timebase_I/clk_cnt<0> 36: timebase_I/clk_cnt<6> 6: eclk 22: timebase_I/clk_cnt<10> 37: timebase_I/clk_cnt<7> 7: sram_adr<0> 23: timebase_I/clk_cnt<11> 38: timebase_I/clk_cnt<8> 8: sram_adr<1> 24: timebase_I/clk_cnt<12> 39: timebase_I/clk_cnt<9> 9: sram_adr<2> 25: timebase_I/clk_cnt<13> 40: timebase_I/sw_read_clk_f 10: sram_adr<3> 26: timebase_I/clk_cnt<14> 41: timebase_I/sw_read_clk_r 11: sram_adr<4> 27: timebase_I/clk_cnt<15> 42: tsel_reg<0> 12: sram_adr<5> 28: timebase_I/clk_cnt<16> 43: tsel_reg<1> 13: sram_adr<6> 29: timebase_I/clk_cnt<17> 44: tsel_reg<2> 14: sram_adr<7> 30: timebase_I/clk_cnt<18> 45: tsel_reg<3> 15: state_FFd1 31: timebase_I/clk_cnt<1> 46: tsel_reg<4> 16: state_FFd2 Signal 1 2 3 4 5 FB Name 0----+----0----+----0----+----0----+----0----+----0 Inputs timebase_I/clk_cnt<9> ....X...............XXXXXXXXXXXXXXXXXXX..XXXXX.... 25 sram_ce_l .................................................. 0 timebase_I/clk_cnt<8> ....X...............XXXXXXXXXXXXXXXXXXX..XXXXX.... 25 sram_clk .XXX.X...........XXX..........XX.......XXXXXXX.... 16 sram_we_l ....X.........XXX................................. 4 sram_oe_l ....X.........XXX................................. 4 sram_adsc_l .................................................. 0 timebase_I/clk_cnt<4> ....X...............XXXXXXXXXXXXXXXXXXX..XXXXX.... 25 sram_adr<8> X.....XXXXXXXX.................................... 9 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 *********************************** FB14 *********************************** Number of function block inputs used/remaining: 43/11 Number of signals used by logic mapping into function block: 43 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use timebase_I/clk_cnt<15> 8 3<- 0 0 FB14_1 (b) (b) timebase_I/clk_cnt<2> 8 3<- 0 0 FB14_2 (b) (b) sram_d<6> 2 0 /\3 0 FB14_3 100 I/O I/O timebase_I/clk_cnt<16> 6 1<- 0 0 FB14_4 (b) (b) sram_d<5> 2 0 /\1 2 FB14_5 101 I/O I/O sram_d<4> 2 0 0 3 FB14_6 102 I/O I/O timebase_I/clk_cnt<17> 5 0 0 0 FB14_7 (b) (b) sram_d<3> 2 0 0 3 FB14_8 103 I/O I/O timebase_I/clk_cnt<18> 3 0 0 2 FB14_9 (b) (b) sram_d<2> 2 0 0 3 FB14_10 104 I/O I/O sram_d<1> 2 0 0 3 FB14_11 105 I/O I/O $OpTx$trigcond_I/int_vtrig_comp<2>/trigcond_I/int_vtrig_comp<2>_D2_INV$526 2 0 0 3 FB14_12 (b) (b) $OpTx$trigcond_I/int_vtrig_comp<3>/trigcond_I/int_vtrig_comp<3>_D2_INV$527 2 0 0 3 FB14_13 (b) (b) sram_d<0> 2 0 0 3 FB14_14 106 I/O I/O $OpTx$trigcond_I/int_vtrig_comp<4>/trigcond_I/int_vtrig_comp<4>_D2_INV$528 2 0 0 3 FB14_15 107 I/O I $OpTx$trigcond_I/int_vtrig_comp<5>/trigcond_I/int_vtrig_comp<5>_D2_INV$529 2 0 0 3 FB14_16 (b) (b) $OpTx$trigcond_I/int_vtrig_comp<6>/trigcond_I/int_vtrig_comp<6>_D2_INV$530 2 0 0 3 FB14_17 (b) (b) timebase_I/clk_2 2 0 \/3 0 FB14_18 (b) (b) Signals Used by Logic in Function Block 1: channel<0> 16: timebase_I/clk_cnt<10> 30: timebase_I/clk_cnt<6> 2: channel<1> 17: timebase_I/clk_cnt<11> 31: timebase_I/clk_cnt<7> 3: channel<2> 18: timebase_I/clk_cnt<12> 32: timebase_I/clk_cnt<8> 4: channel<3> 19: timebase_I/clk_cnt<13> 33: timebase_I/clk_cnt<9> 5: channel<4> 20: timebase_I/clk_cnt<14> 34: tsel_reg<0> 6: channel<5> 21: timebase_I/clk_cnt<15> 35: tsel_reg<1> 7: channel<6> 22: timebase_I/clk_cnt<16> 36: tsel_reg<2> 8: clr 23: timebase_I/clk_cnt<17> 37: tsel_reg<3> 9: mask_reg<2> 24: timebase_I/clk_cnt<18> 38: tsel_reg<4> 10: mask_reg<3> 25: timebase_I/clk_cnt<1> 39: value_reg<2> 11: mask_reg<4> 26: timebase_I/clk_cnt<2> 40: value_reg<3> 12: mask_reg<5> 27: timebase_I/clk_cnt<3> 41: value_reg<4> 13: mask_reg<6> 28: timebase_I/clk_cnt<4> 42: value_reg<5> 14: st<3> 29: timebase_I/clk_cnt<5> 43: value_reg<6> 15: timebase_I/clk_cnt<0> Signal 1 2 3 4 5 FB Name 0----+----0----+----0----+----0----+----0----+----0 Inputs timebase_I/clk_cnt<15> .......X......XXXXXXXXXXXXXXXXXXXXXXXX............ 25 timebase_I/clk_cnt<2> .......X......XXXXXXXXXXXXXXXXXXXXXXXX............ 25 sram_d<6> ......X......X.................................... 2 timebase_I/clk_cnt<16> .......X......XXXXXXXXXXXXXXXXXXXXXXXX............ 25 sram_d<5> .....X.......X.................................... 2 sram_d<4> ....X........X.................................... 2 timebase_I/clk_cnt<17> .......X......XXXXXXXXXXXXXXXXXXXXXXXX............ 25 sram_d<3> ...X.........X.................................... 2 timebase_I/clk_cnt<18> .......X......XXXXXXXXXXXXXXXXXXXXXXXX............ 25 sram_d<2> ..X..........X.................................... 2 sram_d<1> .X...........X.................................... 2 $OpTx$trigcond_I/int_vtrig_comp<2>/trigcond_I/int_vtrig_comp<2>_D2_INV$526 ..X.....X.............................X........... 3 $OpTx$trigcond_I/int_vtrig_comp<3>/trigcond_I/int_vtrig_comp<3>_D2_INV$527 ...X.....X.............................X.......... 3 sram_d<0> X............X.................................... 2 $OpTx$trigcond_I/int_vtrig_comp<4>/trigcond_I/int_vtrig_comp<4>_D2_INV$528 ....X.....X.............................X......... 3 $OpTx$trigcond_I/int_vtrig_comp<5>/trigcond_I/int_vtrig_comp<5>_D2_INV$529 .....X.....X.............................X........ 3 $OpTx$trigcond_I/int_vtrig_comp<6>/trigcond_I/int_vtrig_comp<6>_D2_INV$530 ......X.....X.............................X....... 3 timebase_I/clk_2 .......X......XXXXXXXXXXXXXXXXXXX................. 20 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 *********************************** FB15 *********************************** Number of function block inputs used/remaining: 53/1 Number of signals used by logic mapping into function block: 53 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB15_1 (b) sram_adr<9> 2 0 0 3 FB15_2 79 I/O O sram_adr<10> 2 0 \/3 0 FB15_3 80 I/O O (unused) 0 0 \/5 0 FB15_4 (b) (b) (unused) 0 0 \/5 0 FB15_5 (b) (b) trigcond_I/int_trig_hit_reg 26 21<- 0 0 FB15_6 (b) (b) (unused) 0 0 /\5 0 FB15_7 (b) (b) sram_adr<11> 2 0 /\3 0 FB15_8 81 I/O O $OpTx$trigcond_I/int_vtrig_comp<14>/trigcond_I/int_vtrig_comp<14>_D2_INV$524 2 0 0 3 FB15_9 (b) (b) sram_adr<12> 2 0 0 3 FB15_10 82 I/O O sram_adr<13> 2 0 0 3 FB15_11 83 I/O O sram_adr<14> 2 0 0 3 FB15_12 85 I/O O $OpTx$trigcond_I/int_vtrig_comp<12>/trigcond_I/int_vtrig_comp<12>_D2_INV$523 2 0 0 3 FB15_13 (b) (b) sram_adr<15> 2 0 0 3 FB15_14 86 I/O O sram_adr<16> 2 0 0 3 FB15_15 87 I/O O $OpTx$trigcond_I/int_vtrig_comp<11>/trigcond_I/int_vtrig_comp<11>_D2_INV$522 2 0 0 3 FB15_16 (b) (b) sram_d<15> 2 0 0 3 FB15_17 88 I/O I/O $OpTx$trigcond_I/int_vtrig_comp<10>/trigcond_I/int_vtrig_comp<10>_D2_INV$521 2 0 0 3 FB15_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$trigcond_I/int_vtrig_comp<15>/trigcond_I/int_vtrig_comp<15>_D2_INV$525 19: clr 37: sram_adr<3> 2: $OpTx$trigcond_I/int_vtrig_comp<2>/trigcond_I/int_vtrig_comp<2>_D2_INV$526 20: mask_reg<0> 38: sram_adr<4> 3: $OpTx$trigcond_I/int_vtrig_comp<3>/trigcond_I/int_vtrig_comp<3>_D2_INV$527 21: mask_reg<10> 39: sram_adr<5> 4: $OpTx$trigcond_I/int_vtrig_comp<4>/trigcond_I/int_vtrig_comp<4>_D2_INV$528 22: mask_reg<11> 40: sram_adr<6> 5: $OpTx$trigcond_I/int_vtrig_comp<5>/trigcond_I/int_vtrig_comp<5>_D2_INV$529 23: mask_reg<12> 41: sram_adr<7> 6: $OpTx$trigcond_I/int_vtrig_comp<6>/trigcond_I/int_vtrig_comp<6>_D2_INV$530 24: mask_reg<13> 42: sram_adr<8> 7: $OpTx$trigcond_I/int_vtrig_comp<8>/trigcond_I/int_vtrig_comp<8>_D2_INV$531 25: mask_reg<14> 43: sram_adr<9> 8: $OpTx$trigcond_I/int_vtrig_comp<9>/trigcond_I/int_vtrig_comp<9>_D2_INV$532 26: mask_reg<1> 44: st<3> 9: adr_cnt_en 27: mask_reg<7> 45: trigcond_I/int_etrig_hit_reg 10: channel<0> 28: sram_adr<0> 46: value_reg<0> 11: channel<10> 29: sram_adr<10> 47: value_reg<10> 12: channel<11> 30: sram_adr<11> 48: value_reg<11> 13: channel<12> 31: sram_adr<12> 49: value_reg<12> 14: channel<13> 32: sram_adr<13> 50: value_reg<13> 15: channel<14> 33: sram_adr<14> 51: value_reg<14> 16: channel<15> 34: sram_adr<15> 52: value_reg<1> 17: channel<1> 35: sram_adr<1> 53: value_reg<7> 18: channel<7> 36: sram_adr<2> Signal 1 2 3 4 5 6 FB Name 0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs sram_adr<9> ........X..................X......XXXXXXXX.................. 10 sram_adr<10> ........X..................X......XXXXXXXXX................. 11 trigcond_I/int_trig_hit_reg XXXXXXXX.XXXXXX.XXXXXXXXXXX.................XXXXXXXXX....... 34 sram_adr<11> ........X..................XX.....XXXXXXXXX................. 12 $OpTx$trigcond_I/int_vtrig_comp<14>/trigcond_I/int_vtrig_comp<14>_D2_INV$524 ..............X.........X.........................X......... 3 sram_adr<12> ........X..................XXX....XXXXXXXXX................. 13 sram_adr<13> ........X..................XXXX...XXXXXXXXX................. 14 sram_adr<14> ........X..................XXXXX..XXXXXXXXX................. 15 $OpTx$trigcond_I/int_vtrig_comp<12>/trigcond_I/int_vtrig_comp<12>_D2_INV$523 ............X.........X.........................X........... 3 sram_adr<15> ........X..................XXXXXX.XXXXXXXXX................. 16 sram_adr<16> ........X..................XXXXXXXXXXXXXXXX................. 17 $OpTx$trigcond_I/int_vtrig_comp<11>/trigcond_I/int_vtrig_comp<11>_D2_INV$522 ...........X.........X.........................X............ 3 sram_d<15> ...............X...........................X................ 2 $OpTx$trigcond_I/int_vtrig_comp<10>/trigcond_I/int_vtrig_comp<10>_D2_INV$521 ..........X.........X.........................X............. 3 0----+----1----+----2----+----3----+----4----+----5----+----6 0 0 0 0 0 0 *********************************** FB16 *********************************** Number of function block inputs used/remaining: 24/30 Number of signals used by logic mapping into function block: 24 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 /\5 0 FB16_1 (b) (b) sram_d<14> 2 0 /\1 2 FB16_2 91 I/O I/O sram_d<13> 2 0 0 3 FB16_3 92 I/O I/O (unused) 0 0 0 5 FB16_4 (b) sram_d<12> 2 0 0 3 FB16_5 93 I/O I/O sram_d<11> 2 0 0 3 FB16_6 94 I/O I/O (unused) 0 0 0 5 FB16_7 (b) sram_d<10> 2 0 0 3 FB16_8 95 I/O I/O (unused) 0 0 0 5 FB16_9 (b) sram_d<9> 2 0 0 3 FB16_10 96 I/O I/O sram_d<8> 2 0 0 3 FB16_11 97 I/O I/O sram_d<7> 2 0 0 3 FB16_12 98 I/O I/O (unused) 0 0 \/5 0 FB16_13 (b) (b) (unused) 0 0 \/5 0 FB16_14 (b) (b) trigcond_I/tlen_cnt<0> 20 15<- 0 0 FB16_15 (b) (b) (unused) 0 0 /\5 0 FB16_16 (b) (b) (unused) 0 0 \/5 0 FB16_17 (b) (b) trigcond_I/tlen_cnt<1> 16 11<- 0 0 FB16_18 (b) (b) Signals Used by Logic in Function Block 1: channel<10> 9: clr 17: tlen_reg<3> 2: channel<11> 10: extrig_en 18: trigcond_I/extrig_int 3: channel<12> 11: extrig_val 19: trigcond_I/int_trig_hit_reg 4: channel<13> 12: inv_trig 20: trigcond_I/tlen_cnt<0> 5: channel<14> 13: st<3> 21: trigcond_I/tlen_cnt<1> 6: channel<7> 14: tlen_reg<0> 22: trigcond_I/tlen_cnt<2> 7: channel<8> 15: tlen_reg<1> 23: trigcond_I/tlen_cnt<3> 8: channel<9> 16: tlen_reg<2> 24: trigcond_I/trig_on_d Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs sram_d<14> ....X.......X........................... 2 sram_d<13> ...X........X........................... 2 sram_d<12> ..X.........X........................... 2 sram_d<11> .X..........X........................... 2 sram_d<10> X...........X........................... 2 sram_d<9> .......X....X........................... 2 sram_d<8> ......X.....X........................... 2 sram_d<7> .....X......X........................... 2 trigcond_I/tlen_cnt<0> ........XXXX.XXXXXXXXXXX................ 15 trigcond_I/tlen_cnt<1> ........XXXX.XXXXXXXXXXX................ 15 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** $OpTx$$OpTx$FX_DC$187_INV$520 <= (epp_I/adr(1) AND NOT epp_I/adr(0)); $OpTx$trigcond_I/int_vtrig_comp(2)/trigcond_I/int_vtrig_comp(2)_D2_INV$526 <= ((channel(2) AND mask_reg(2) AND NOT value_reg(2)) OR (NOT channel(2) AND mask_reg(2) AND value_reg(2))); $OpTx$trigcond_I/int_vtrig_comp(3)/trigcond_I/int_vtrig_comp(3)_D2_INV$527 <= ((channel(3) AND mask_reg(3) AND NOT value_reg(3)) OR (NOT channel(3) AND mask_reg(3) AND value_reg(3))); $OpTx$trigcond_I/int_vtrig_comp(4)/trigcond_I/int_vtrig_comp(4)_D2_INV$528 <= ((channel(4) AND mask_reg(4) AND NOT value_reg(4)) OR (NOT channel(4) AND mask_reg(4) AND value_reg(4))); $OpTx$trigcond_I/int_vtrig_comp(5)/trigcond_I/int_vtrig_comp(5)_D2_INV$529 <= ((channel(5) AND mask_reg(5) AND NOT value_reg(5)) OR (NOT channel(5) AND mask_reg(5) AND value_reg(5))); $OpTx$trigcond_I/int_vtrig_comp(6)/trigcond_I/int_vtrig_comp(6)_D2_INV$530 <= ((channel(6) AND mask_reg(6) AND NOT value_reg(6)) OR (NOT channel(6) AND mask_reg(6) AND value_reg(6))); $OpTx$trigcond_I/int_vtrig_comp(8)/trigcond_I/int_vtrig_comp(8)_D2_INV$531 <= ((channel(8) AND mask_reg(8) AND NOT value_reg(8)) OR (NOT channel(8) AND mask_reg(8) AND value_reg(8))); $OpTx$trigcond_I/int_vtrig_comp(9)/trigcond_I/int_vtrig_comp(9)_D2_INV$532 <= ((channel(9) AND mask_reg(9) AND NOT value_reg(9)) OR (NOT channel(9) AND mask_reg(9) AND value_reg(9))); $OpTx$trigcond_I/int_vtrig_comp(10)/trigcond_I/int_vtrig_comp(10)_D2_INV$521 <= ((channel(10) AND mask_reg(10) AND NOT value_reg(10)) OR (NOT channel(10) AND mask_reg(10) AND value_reg(10))); $OpTx$trigcond_I/int_vtrig_comp(11)/trigcond_I/int_vtrig_comp(11)_D2_INV$522 <= ((channel(11) AND mask_reg(11) AND NOT value_reg(11)) OR (NOT channel(11) AND mask_reg(11) AND value_reg(11))); $OpTx$trigcond_I/int_vtrig_comp(12)/trigcond_I/int_vtrig_comp(12)_D2_INV$523 <= ((channel(12) AND mask_reg(12) AND NOT value_reg(12)) OR (NOT channel(12) AND mask_reg(12) AND value_reg(12))); $OpTx$trigcond_I/int_vtrig_comp(14)/trigcond_I/int_vtrig_comp(14)_D2_INV$524 <= ((channel(14) AND mask_reg(14) AND NOT value_reg(14)) OR (NOT channel(14) AND mask_reg(14) AND value_reg(14))); $OpTx$trigcond_I/int_vtrig_comp(15)/trigcond_I/int_vtrig_comp(15)_D2_INV$525 <= ((channel(15) AND mask_reg(15) AND NOT value_reg(15)) OR (NOT channel(15) AND mask_reg(15) AND value_reg(15))); FDCPE_adr_cnt_en: FDCPE port map (adr_cnt_en,adr_cnt_en_D,clk_ob,clr,'0'); adr_cnt_en_D <= (NOT state_FFd3 AND NOT state_FFd2 AND NOT state_FFd1); FDCPE_clk_falling_edge: FDCPE port map (clk_falling_edge,dd(5).PIN,NOT clk_in,'0','0',clk_falling_edge_CE); clk_falling_edge_CE <= (epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); clk_o <= NOT (((EXP41_.EXP) OR (st_0.EXP) OR (NOT timebase_I/clk_2 AND NOT tsel_reg(1) AND tsel_reg(4)) OR (NOT timebase_I/clk_2 AND tsel_reg(2) AND NOT tsel_reg(4)) OR (NOT timebase_I/clk_2 AND NOT tsel_reg(2) AND tsel_reg(4)) OR (NOT timebase_I/clk_2 AND NOT tsel_reg(3) AND tsel_reg(4)) OR (NOT timebase_I/clk_2 AND NOT tsel_reg(4) AND tsel_reg(0)))); clk_ob <= ((EXP38_.EXP) OR (EXP39_.EXP) OR (timebase_I/clk_2 AND NOT tsel_reg(2) AND tsel_reg(3) AND NOT clk_falling_edge AND NOT timebase_I/sw_read_clk_f AND NOT timebase_I/sw_read_clk_r) OR (timebase_I/clk_2 AND NOT tsel_reg(4) AND tsel_reg(0) AND NOT clk_falling_edge AND NOT timebase_I/sw_read_clk_f AND NOT timebase_I/sw_read_clk_r) OR (NOT timebase_I/clk_2 AND NOT tsel_reg(2) AND tsel_reg(3) AND clk_falling_edge AND NOT timebase_I/sw_read_clk_f AND NOT timebase_I/sw_read_clk_r) OR (NOT timebase_I/clk_2 AND NOT tsel_reg(4) AND tsel_reg(0) AND clk_falling_edge AND NOT timebase_I/sw_read_clk_f AND NOT timebase_I/sw_read_clk_r) OR (tsel_reg(1) AND tsel_reg(2) AND tsel_reg(3) AND tsel_reg(4) AND NOT tsel_reg(0) AND clk_falling_edge AND NOT timebase_I/sw_read_clk_f AND NOT timebase_I/sw_read_clk_r AND NOT eclk)); FDCPE_clk_rd: FDCPE port map (clk_rd,clk_rd_D,clk_in,'0','0',clk_rd_CE); clk_rd_D <= ((dd(5).PIN AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i) OR (epp_I/bytesel(0) AND epp_I/bytesel(1) AND epp_I/auto_inc AND epp_I/ALE_l_i AND epp_I/d_rd_i_d) OR (epp_I/bytesel(0) AND epp_I/bytesel(1) AND epp_I/auto_inc AND epp_I/RD_l_i AND epp_I/WR_l_i AND epp_I/d_rd_i_d) OR (epp_I/bytesel(0) AND epp_I/bytesel(1) AND epp_I/auto_inc AND NOT epp_I/RD_l_i AND NOT epp_I/WR_l_i AND epp_I/d_rd_i_d)); clk_rd_CE <= (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3)); FDCPE_clr: FDCPE port map (clr,dd(6).PIN,clk_in,'0','0',clr_CE); clr_CE <= (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); dd_I(0) <= NOT (((sram_I/sample_cnt_int(7).EXP) OR (epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i) OR (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND epp_I/bytesel(0) AND epp_I/bytesel(1) AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i AND NOT sram_d(24).PIN) OR (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND epp_I/bytesel(0) AND NOT epp_I/bytesel(1) AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i AND NOT sram_d(8).PIN) OR (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/bytesel(0) AND NOT epp_I/bytesel(1) AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i AND NOT sram_d(0).PIN))); dd(0) <= dd_I(0) when dd_OE(0) = '1' else 'Z'; dd_OE(0) <= (NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i AND NOT $OpTx$$OpTx$FX_DC$187_INV$520); dd_I(1) <= NOT (((sram_I/sample_cnt_int(16).EXP) OR (epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i) OR (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND epp_I/bytesel(0) AND epp_I/bytesel(1) AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i AND NOT sram_d(25).PIN) OR (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND epp_I/bytesel(0) AND NOT epp_I/bytesel(1) AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i AND NOT sram_d(9).PIN) OR (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/bytesel(0) AND NOT epp_I/bytesel(1) AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i AND NOT sram_d(1).PIN))); dd(1) <= dd_I(1) when dd_OE(1) = '1' else 'Z'; dd_OE(1) <= (NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i AND NOT $OpTx$$OpTx$FX_DC$187_INV$520); dd_I(2) <= NOT (((sram_I/sample_cnt_int(15).EXP) OR (epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i) OR (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND epp_I/bytesel(0) AND epp_I/bytesel(1) AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i AND NOT sram_d(26).PIN) OR (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND epp_I/bytesel(0) AND NOT epp_I/bytesel(1) AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i AND NOT sram_d(10).PIN) OR (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/bytesel(0) AND NOT epp_I/bytesel(1) AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i AND NOT sram_d(2).PIN))); dd(2) <= dd_I(2) when dd_OE(2) = '1' else 'Z'; dd_OE(2) <= (NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i AND NOT $OpTx$$OpTx$FX_DC$187_INV$520); dd_I(3) <= ((epp_I/adr(2)) OR (epp_I/ALE_l_i) OR (epp_I/RD_l_i) OR (NOT epp_I/WR_l_i) OR (sram_I/sample_cnt_int(12).EXP) OR (sram_I/sample_cnt_int(11).EXP)); dd(3) <= dd_I(3) when dd_OE(3) = '1' else 'Z'; dd_OE(3) <= (NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i AND NOT $OpTx$$OpTx$FX_DC$187_INV$520); dd_I(4) <= NOT (((EXP47_.EXP) OR (dd_out(5).EXP) OR (trigcond_I/trig_cnt(0) AND epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT tcnt_reg(0) AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i) OR (NOT trigcond_I/trig_cnt(0) AND epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND tcnt_reg(0) AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i) OR (trigcond_I/trig_cnt(1) AND epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT tcnt_reg(1) AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i) OR (NOT trigcond_I/trig_cnt(1) AND epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND tcnt_reg(1) AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i))); dd(4) <= dd_I(4) when dd_OE(4) = '1' else 'Z'; dd_OE(4) <= (NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i AND NOT $OpTx$$OpTx$FX_DC$187_INV$520); dd_I(5) <= NOT (((mask_reg(0).EXP) OR (NOT clr AND epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i) OR (NOT epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i) OR (NOT epp_I/adr(1) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND epp_I/bytesel(0) AND NOT epp_I/bytesel(1) AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i AND NOT sram_d(13).PIN))); dd(5) <= dd_I(5) when dd_OE(5) = '1' else 'Z'; dd_OE(5) <= (NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i AND NOT $OpTx$$OpTx$FX_DC$187_INV$520); dd_I(6) <= NOT (((dd_out(7).EXP) OR (NOT epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i) OR (epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT run AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i) OR (NOT epp_I/adr(1) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND epp_I/bytesel(0) AND NOT epp_I/bytesel(1) AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i AND NOT sram_d(14).PIN) OR (NOT epp_I/adr(1) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/bytesel(0) AND NOT epp_I/bytesel(1) AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i AND NOT sram_d(6).PIN))); dd(6) <= dd_I(6) when dd_OE(6) = '1' else 'Z'; dd_OE(6) <= (NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i AND NOT $OpTx$$OpTx$FX_DC$187_INV$520); dd_I(7) <= NOT (((extrig_val.EXP) OR (epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT done AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i) OR (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND epp_I/bytesel(0) AND NOT epp_I/bytesel(1) AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i AND NOT sram_d(15).PIN))); dd(7) <= dd_I(7) when dd_OE(7) = '1' else 'Z'; dd_OE(7) <= (NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i AND NOT $OpTx$$OpTx$FX_DC$187_INV$520); FDCPE_done: FDCPE port map (done,done_D,clk_ob,clr,'0'); done_D <= (state_FFd3 AND state_FFd1); FDCPE_edge_reg0: FDCPE port map (edge_reg(0),edge_reg(1).EXP,NOT clk_in,'0','0',edge_reg_CE(0)); edge_reg_CE(0) <= (epp_I/adr(1) AND epp_I/adr(0) AND epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_edge_reg1: FDCPE port map (edge_reg(1),dd(1).PIN,NOT clk_in,'0','0',edge_reg_CE(1)); edge_reg_CE(1) <= (epp_I/adr(1) AND epp_I/adr(0) AND epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_edge_reg2: FDCPE port map (edge_reg(2),dd(2).PIN,NOT clk_in,'0','0',edge_reg_CE(2)); edge_reg_CE(2) <= (epp_I/adr(1) AND epp_I/adr(0) AND epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_edge_reg3: FDCPE port map (edge_reg(3),dd(3).PIN,NOT clk_in,'0','0',edge_reg_CE(3)); edge_reg_CE(3) <= (epp_I/adr(1) AND epp_I/adr(0) AND epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_edge_reg4: FDCPE port map (edge_reg(4),dd(4).PIN,NOT clk_in,'0','0',edge_reg_CE(4)); edge_reg_CE(4) <= (epp_I/adr(1) AND epp_I/adr(0) AND epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_edge_reg5: FDCPE port map (edge_reg(5),dd(5).PIN,NOT clk_in,'0','0',edge_reg_CE(5)); edge_reg_CE(5) <= (epp_I/adr(1) AND epp_I/adr(0) AND epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_edge_reg6: FDCPE port map (edge_reg(6),dd(6).PIN,NOT clk_in,'0','0',edge_reg_CE(6)); edge_reg_CE(6) <= (epp_I/adr(1) AND epp_I/adr(0) AND epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_edge_reg7: FDCPE port map (edge_reg(7),dd(7).PIN,NOT clk_in,'0','0',edge_reg_CE(7)); edge_reg_CE(7) <= (epp_I/adr(1) AND epp_I/adr(0) AND epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_edge_reg8: FDCPE port map (edge_reg(8),dd(0).PIN,NOT clk_in,'0','0',edge_reg_CE(8)); edge_reg_CE(8) <= (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_edge_reg9: FDCPE port map (edge_reg(9),dd(1).PIN,NOT clk_in,'0','0',edge_reg_CE(9)); edge_reg_CE(9) <= (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_edge_reg10: FDCPE port map (edge_reg(10),dd(2).PIN,NOT clk_in,'0','0',edge_reg_CE(10)); edge_reg_CE(10) <= (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_edge_reg11: FDCPE port map (edge_reg(11),dd(3).PIN,NOT clk_in,'0','0',edge_reg_CE(11)); edge_reg_CE(11) <= (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_edge_reg12: FDCPE port map (edge_reg(12),dd(4).PIN,NOT clk_in,'0','0',edge_reg_CE(12)); edge_reg_CE(12) <= (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_edge_reg13: FDCPE port map (edge_reg(13),dd(5).PIN,NOT clk_in,'0','0',edge_reg_CE(13)); edge_reg_CE(13) <= (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_edge_reg14: FDCPE port map (edge_reg(14),dd(6).PIN,NOT clk_in,'0','0',edge_reg_CE(14)); edge_reg_CE(14) <= (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_edge_reg15: FDCPE port map (edge_reg(15),dd(7).PIN,NOT clk_in,'0','0',edge_reg_CE(15)); edge_reg_CE(15) <= (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_epp_I/ALE_l_i: FDCPE port map (epp_I/ALE_l_i,dale_l,clk_in,'0','0'); FDCPE_epp_I/RD_l_i: FDCPE port map (epp_I/RD_l_i,drd_l,clk_in,'0','0'); FDCPE_epp_I/WR_l_i: FDCPE port map (epp_I/WR_l_i,dwr_l,clk_in,'0','0'); FDCPE_epp_I/adr0: FDCPE port map (epp_I/adr(0),dd(0).PIN,clk_in,'0','0',epp_I/adr_CE(0)); epp_I/adr_CE(0) <= (epp_I/ALE_l_i AND epp_I/RD_l_i AND epp_I/WR_l_i); FDCPE_epp_I/adr1: FDCPE port map (epp_I/adr(1),dd(1).PIN,clk_in,'0','0',epp_I/adr_CE(1)); epp_I/adr_CE(1) <= (epp_I/ALE_l_i AND epp_I/RD_l_i AND epp_I/WR_l_i); FDCPE_epp_I/adr2: FDCPE port map (epp_I/adr(2),dd(2).PIN,clk_in,'0','0',epp_I/adr_CE(2)); epp_I/adr_CE(2) <= (epp_I/ALE_l_i AND epp_I/RD_l_i AND epp_I/WR_l_i); FDCPE_epp_I/adr3: FDCPE port map (epp_I/adr(3),dd(3).PIN,clk_in,'0','0',epp_I/adr_CE(3)); epp_I/adr_CE(3) <= (epp_I/ALE_l_i AND epp_I/RD_l_i AND epp_I/WR_l_i); FDCPE_epp_I/auto_inc: FDCPE port map (epp_I/auto_inc,dd(4).PIN,clk_in,'0','0',epp_I/auto_inc_CE); epp_I/auto_inc_CE <= (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FTCPE_epp_I/bytesel0: FTCPE port map (epp_I/bytesel(0),epp_I/bytesel_T(0),clk_in,'0','0'); epp_I/bytesel_T(0) <= ((epp_I/bytesel(1).EXP) OR (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND epp_I/ALE_l_i AND epp_I/d_rd_i_d)); FTCPE_epp_I/bytesel1: FTCPE port map (epp_I/bytesel(1),epp_I/bytesel_T(1),clk_in,'0','0'); epp_I/bytesel_T(1) <= ((edge_reg(0).EXP) OR (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND epp_I/bytesel(0) AND epp_I/ALE_l_i AND epp_I/d_rd_i_d)); FDCPE_epp_I/d_rd_i_d: FDCPE port map (epp_I/d_rd_i_d,epp_I/d_rd_i_d_D,clk_in,'0','0'); epp_I/d_rd_i_d_D <= (NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i); FDCPE_extrig_en: FDCPE port map (extrig_en,dd(1).PIN,NOT clk_in,'0','0',extrig_en_CE); extrig_en_CE <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND epp_I/adr(2) AND epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_extrig_val: FDCPE port map (extrig_val,dd(0).PIN,NOT clk_in,'0','0',extrig_val_CE); extrig_val_CE <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND epp_I/adr(2) AND epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_inv_trig: FDCPE port map (inv_trig,dd(7).PIN,NOT clk_in,'0','0',inv_trig_CE); inv_trig_CE <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND epp_I/adr(2) AND epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_mask_reg0: FDCPE port map (mask_reg(0),dd(0).PIN,NOT clk_in,'0','0',mask_reg_CE(0)); mask_reg_CE(0) <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_mask_reg1: FDCPE port map (mask_reg(1),dd(1).PIN,NOT clk_in,'0','0',mask_reg_CE(1)); mask_reg_CE(1) <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_mask_reg2: FDCPE port map (mask_reg(2),dd(2).PIN,NOT clk_in,'0','0',mask_reg_CE(2)); mask_reg_CE(2) <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_mask_reg3: FDCPE port map (mask_reg(3),dd(3).PIN,NOT clk_in,'0','0',mask_reg_CE(3)); mask_reg_CE(3) <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_mask_reg4: FDCPE port map (mask_reg(4),dd(4).PIN,NOT clk_in,'0','0',mask_reg_CE(4)); mask_reg_CE(4) <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_mask_reg5: FDCPE port map (mask_reg(5),dd(5).PIN,NOT clk_in,'0','0',mask_reg_CE(5)); mask_reg_CE(5) <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_mask_reg6: FDCPE port map (mask_reg(6),dd(6).PIN,NOT clk_in,'0','0',mask_reg_CE(6)); mask_reg_CE(6) <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_mask_reg7: FDCPE port map (mask_reg(7),dd(7).PIN,NOT clk_in,'0','0',mask_reg_CE(7)); mask_reg_CE(7) <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_mask_reg8: FDCPE port map (mask_reg(8),dd(0).PIN,NOT clk_in,'0','0',mask_reg_CE(8)); mask_reg_CE(8) <= (epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_mask_reg9: FDCPE port map (mask_reg(9),dd(1).PIN,NOT clk_in,'0','0',mask_reg_CE(9)); mask_reg_CE(9) <= (epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_mask_reg10: FDCPE port map (mask_reg(10),dd(2).PIN,NOT clk_in,'0','0',mask_reg_CE(10)); mask_reg_CE(10) <= (epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_mask_reg11: FDCPE port map (mask_reg(11),dd(3).PIN,NOT clk_in,'0','0',mask_reg_CE(11)); mask_reg_CE(11) <= (epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_mask_reg12: FDCPE port map (mask_reg(12),dd(4).PIN,NOT clk_in,'0','0',mask_reg_CE(12)); mask_reg_CE(12) <= (epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_mask_reg13: FDCPE port map (mask_reg(13),dd(5).PIN,NOT clk_in,'0','0',mask_reg_CE(13)); mask_reg_CE(13) <= (epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_mask_reg14: FDCPE port map (mask_reg(14),dd(6).PIN,NOT clk_in,'0','0',mask_reg_CE(14)); mask_reg_CE(14) <= (epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_mask_reg15: FDCPE port map (mask_reg(15),dd(7).PIN,NOT clk_in,'0','0',mask_reg_CE(15)); mask_reg_CE(15) <= (epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_pretrig_off: FDCPE port map (pretrig_off,dd(4).PIN,NOT clk_in,'0','0',pretrig_off_CE); pretrig_off_CE <= (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_psize_reg0: FDCPE port map (psize_reg(0),dd(0).PIN,NOT clk_in,'0','0',psize_reg_CE(0)); psize_reg_CE(0) <= (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_psize_reg1: FDCPE port map (psize_reg(1),dd(1).PIN,NOT clk_in,'0','0',psize_reg_CE(1)); psize_reg_CE(1) <= (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_psize_reg2: FDCPE port map (psize_reg(2),dd(2).PIN,NOT clk_in,'0','0',psize_reg_CE(2)); psize_reg_CE(2) <= (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_psize_reg3: FDCPE port map (psize_reg(3),dd(3).PIN,NOT clk_in,'0','0',psize_reg_CE(3)); psize_reg_CE(3) <= (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_run: FDCPE port map (run,dd(7).PIN,clk_in,'0','0',run_CE); run_CE <= (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_sample_cnt_en: FDCPE port map (sample_cnt_en,state_FFd2,clk_ob,clr,'0'); FDCPE_sample_cnt_wm: FDCPE port map (sample_cnt_wm,sample_cnt_wm_D,clk_ob,'0','0'); sample_cnt_wm_D <= ((sram_I/sample_cnt_int(8).EXP) OR (EXP54_.EXP) OR (sram_I/sample_cnt_int(0) AND sram_I/sample_cnt_int(11) AND NOT sram_I/sample_cnt_int(1) AND sram_I/sample_cnt_int(10) AND sram_I/sample_cnt_int(12) AND sram_I/sample_cnt_int(13) AND sram_I/sample_cnt_int(14) AND sram_I/sample_cnt_int(15) AND sram_I/sample_cnt_int(2) AND sram_I/sample_cnt_int(3) AND sram_I/sample_cnt_int(4) AND sram_I/sample_cnt_int(5) AND sram_I/sample_cnt_int(6) AND sram_I/sample_cnt_int(7) AND sram_I/sample_cnt_int(8) AND sram_I/sample_cnt_int(9) AND sram_I/sample_cnt_int(16) AND psize_reg(0) AND psize_reg(1) AND psize_reg(2) AND psize_reg(3)) OR (sram_I/sample_cnt_int(0) AND sram_I/sample_cnt_int(11) AND NOT sram_I/sample_cnt_int(1) AND sram_I/sample_cnt_int(10) AND sram_I/sample_cnt_int(12) AND sram_I/sample_cnt_int(13) AND sram_I/sample_cnt_int(14) AND sram_I/sample_cnt_int(15) AND sram_I/sample_cnt_int(2) AND sram_I/sample_cnt_int(3) AND sram_I/sample_cnt_int(4) AND sram_I/sample_cnt_int(5) AND sram_I/sample_cnt_int(6) AND sram_I/sample_cnt_int(7) AND sram_I/sample_cnt_int(8) AND sram_I/sample_cnt_int(9) AND NOT sram_I/sample_cnt_int(16) AND psize_reg(0) AND psize_reg(1) AND psize_reg(2) AND NOT psize_reg(3)) OR (sram_I/sample_cnt_int(0) AND sram_I/sample_cnt_int(11) AND NOT sram_I/sample_cnt_int(1) AND sram_I/sample_cnt_int(10) AND sram_I/sample_cnt_int(12) AND sram_I/sample_cnt_int(13) AND NOT sram_I/sample_cnt_int(14) AND sram_I/sample_cnt_int(15) AND sram_I/sample_cnt_int(2) AND sram_I/sample_cnt_int(3) AND sram_I/sample_cnt_int(4) AND sram_I/sample_cnt_int(5) AND sram_I/sample_cnt_int(6) AND sram_I/sample_cnt_int(7) AND sram_I/sample_cnt_int(8) AND sram_I/sample_cnt_int(9) AND sram_I/sample_cnt_int(16) AND psize_reg(0) AND NOT psize_reg(1) AND psize_reg(2) AND psize_reg(3)) OR (sram_I/sample_cnt_int(0) AND sram_I/sample_cnt_int(11) AND NOT sram_I/sample_cnt_int(1) AND sram_I/sample_cnt_int(10) AND sram_I/sample_cnt_int(12) AND NOT sram_I/sample_cnt_int(13) AND sram_I/sample_cnt_int(14) AND sram_I/sample_cnt_int(15) AND sram_I/sample_cnt_int(2) AND sram_I/sample_cnt_int(3) AND sram_I/sample_cnt_int(4) AND sram_I/sample_cnt_int(5) AND sram_I/sample_cnt_int(6) AND sram_I/sample_cnt_int(7) AND sram_I/sample_cnt_int(8) AND sram_I/sample_cnt_int(9) AND sram_I/sample_cnt_int(16) AND NOT psize_reg(0) AND psize_reg(1) AND psize_reg(2) AND psize_reg(3)) OR (sram_I/sample_cnt_int(0) AND sram_I/sample_cnt_int(11) AND NOT sram_I/sample_cnt_int(1) AND sram_I/sample_cnt_int(10) AND sram_I/sample_cnt_int(12) AND NOT sram_I/sample_cnt_int(13) AND sram_I/sample_cnt_int(14) AND sram_I/sample_cnt_int(15) AND sram_I/sample_cnt_int(2) AND sram_I/sample_cnt_int(3) AND sram_I/sample_cnt_int(4) AND sram_I/sample_cnt_int(5) AND sram_I/sample_cnt_int(6) AND sram_I/sample_cnt_int(7) AND sram_I/sample_cnt_int(8) AND sram_I/sample_cnt_int(9) AND NOT sram_I/sample_cnt_int(16) AND NOT psize_reg(0) AND psize_reg(1) AND psize_reg(2) AND NOT psize_reg(3))); FTCPE_sram_I/sample_cnt_int0: FTCPE port map (sram_I/sample_cnt_int(0),sram_I/sample_cnt_int_T(0),clk_ob,clr,'0'); sram_I/sample_cnt_int_T(0) <= ((NOT sample_cnt_en) OR (NOT sram_I/sample_cnt_int(0) AND sram_I/sample_cnt_int(11) AND sram_I/sample_cnt_int(1) AND sram_I/sample_cnt_int(10) AND sram_I/sample_cnt_int(12) AND sram_I/sample_cnt_int(13) AND sram_I/sample_cnt_int(14) AND sram_I/sample_cnt_int(15) AND NOT sram_I/sample_cnt_int(2) AND sram_I/sample_cnt_int(3) AND sram_I/sample_cnt_int(4) AND sram_I/sample_cnt_int(5) AND sram_I/sample_cnt_int(6) AND sram_I/sample_cnt_int(7) AND sram_I/sample_cnt_int(8) AND sram_I/sample_cnt_int(9) AND sram_I/sample_cnt_int(16))); FTCPE_sram_I/sample_cnt_int1: FTCPE port map (sram_I/sample_cnt_int(1),sram_I/sample_cnt_int_T(1),clk_ob,clr,'0'); sram_I/sample_cnt_int_T(1) <= (sram_I/sample_cnt_int(0) AND sample_cnt_en); FTCPE_sram_I/sample_cnt_int2: FTCPE port map (sram_I/sample_cnt_int(2),sram_I/sample_cnt_int_T(2),clk_ob,clr,'0'); sram_I/sample_cnt_int_T(2) <= (sram_I/sample_cnt_int(0) AND sram_I/sample_cnt_int(1) AND sample_cnt_en); FTCPE_sram_I/sample_cnt_int3: FTCPE port map (sram_I/sample_cnt_int(3),sram_I/sample_cnt_int_T(3),clk_ob,clr,'0'); sram_I/sample_cnt_int_T(3) <= (sram_I/sample_cnt_int(0) AND sram_I/sample_cnt_int(1) AND sram_I/sample_cnt_int(2) AND sample_cnt_en); FTCPE_sram_I/sample_cnt_int4: FTCPE port map (sram_I/sample_cnt_int(4),sram_I/sample_cnt_int_T(4),clk_ob,clr,'0'); sram_I/sample_cnt_int_T(4) <= (sram_I/sample_cnt_int(0) AND sram_I/sample_cnt_int(1) AND sram_I/sample_cnt_int(2) AND sram_I/sample_cnt_int(3) AND sample_cnt_en); FTCPE_sram_I/sample_cnt_int5: FTCPE port map (sram_I/sample_cnt_int(5),sram_I/sample_cnt_int_T(5),clk_ob,clr,'0'); sram_I/sample_cnt_int_T(5) <= (sram_I/sample_cnt_int(0) AND sram_I/sample_cnt_int(1) AND sram_I/sample_cnt_int(2) AND sram_I/sample_cnt_int(3) AND sram_I/sample_cnt_int(4) AND sample_cnt_en); FTCPE_sram_I/sample_cnt_int6: FTCPE port map (sram_I/sample_cnt_int(6),sram_I/sample_cnt_int_T(6),clk_ob,clr,'0'); sram_I/sample_cnt_int_T(6) <= (sram_I/sample_cnt_int(0) AND sram_I/sample_cnt_int(1) AND sram_I/sample_cnt_int(2) AND sram_I/sample_cnt_int(3) AND sram_I/sample_cnt_int(4) AND sram_I/sample_cnt_int(5) AND sample_cnt_en); FTCPE_sram_I/sample_cnt_int7: FTCPE port map (sram_I/sample_cnt_int(7),sram_I/sample_cnt_int_T(7),clk_ob,clr,'0'); sram_I/sample_cnt_int_T(7) <= (sram_I/sample_cnt_int(0) AND sram_I/sample_cnt_int(1) AND sram_I/sample_cnt_int(2) AND sram_I/sample_cnt_int(3) AND sram_I/sample_cnt_int(4) AND sram_I/sample_cnt_int(5) AND sram_I/sample_cnt_int(6) AND sample_cnt_en); FTCPE_sram_I/sample_cnt_int8: FTCPE port map (sram_I/sample_cnt_int(8),sram_I/sample_cnt_int_T(8),clk_ob,clr,'0'); sram_I/sample_cnt_int_T(8) <= (sram_I/sample_cnt_int(0) AND sram_I/sample_cnt_int(1) AND sram_I/sample_cnt_int(2) AND sram_I/sample_cnt_int(3) AND sram_I/sample_cnt_int(4) AND sram_I/sample_cnt_int(5) AND sram_I/sample_cnt_int(6) AND sram_I/sample_cnt_int(7) AND sample_cnt_en); FTCPE_sram_I/sample_cnt_int9: FTCPE port map (sram_I/sample_cnt_int(9),sram_I/sample_cnt_int_T(9),clk_ob,clr,'0'); sram_I/sample_cnt_int_T(9) <= (sram_I/sample_cnt_int(0) AND sram_I/sample_cnt_int(1) AND sram_I/sample_cnt_int(2) AND sram_I/sample_cnt_int(3) AND sram_I/sample_cnt_int(4) AND sram_I/sample_cnt_int(5) AND sram_I/sample_cnt_int(6) AND sram_I/sample_cnt_int(7) AND sram_I/sample_cnt_int(8) AND sample_cnt_en); FTCPE_sram_I/sample_cnt_int10: FTCPE port map (sram_I/sample_cnt_int(10),sram_I/sample_cnt_int_T(10),clk_ob,clr,'0'); sram_I/sample_cnt_int_T(10) <= (sram_I/sample_cnt_int(0) AND sram_I/sample_cnt_int(1) AND sram_I/sample_cnt_int(2) AND sram_I/sample_cnt_int(3) AND sram_I/sample_cnt_int(4) AND sram_I/sample_cnt_int(5) AND sram_I/sample_cnt_int(6) AND sram_I/sample_cnt_int(7) AND sram_I/sample_cnt_int(8) AND sram_I/sample_cnt_int(9) AND sample_cnt_en); FTCPE_sram_I/sample_cnt_int11: FTCPE port map (sram_I/sample_cnt_int(11),sram_I/sample_cnt_int(10).EXP,clk_ob,clr,'0'); FTCPE_sram_I/sample_cnt_int12: FTCPE port map (sram_I/sample_cnt_int(12),sram_I/sample_cnt_int_T(12),clk_ob,clr,'0'); sram_I/sample_cnt_int_T(12) <= (sram_I/sample_cnt_int(0) AND sram_I/sample_cnt_int(11) AND sram_I/sample_cnt_int(1) AND sram_I/sample_cnt_int(10) AND sram_I/sample_cnt_int(2) AND sram_I/sample_cnt_int(3) AND sram_I/sample_cnt_int(4) AND sram_I/sample_cnt_int(5) AND sram_I/sample_cnt_int(6) AND sram_I/sample_cnt_int(7) AND sram_I/sample_cnt_int(8) AND sram_I/sample_cnt_int(9) AND sample_cnt_en); FTCPE_sram_I/sample_cnt_int13: FTCPE port map (sram_I/sample_cnt_int(13),sram_I/sample_cnt_int_T(13),clk_ob,clr,'0'); sram_I/sample_cnt_int_T(13) <= (sram_I/sample_cnt_int(0) AND sram_I/sample_cnt_int(11) AND sram_I/sample_cnt_int(1) AND sram_I/sample_cnt_int(10) AND sram_I/sample_cnt_int(12) AND sram_I/sample_cnt_int(2) AND sram_I/sample_cnt_int(3) AND sram_I/sample_cnt_int(4) AND sram_I/sample_cnt_int(5) AND sram_I/sample_cnt_int(6) AND sram_I/sample_cnt_int(7) AND sram_I/sample_cnt_int(8) AND sram_I/sample_cnt_int(9) AND sample_cnt_en); FTCPE_sram_I/sample_cnt_int14: FTCPE port map (sram_I/sample_cnt_int(14),sram_I/sample_cnt_int_T(14),clk_ob,clr,'0'); sram_I/sample_cnt_int_T(14) <= (sram_I/sample_cnt_int(0) AND sram_I/sample_cnt_int(11) AND sram_I/sample_cnt_int(1) AND sram_I/sample_cnt_int(10) AND sram_I/sample_cnt_int(12) AND sram_I/sample_cnt_int(13) AND sram_I/sample_cnt_int(2) AND sram_I/sample_cnt_int(3) AND sram_I/sample_cnt_int(4) AND sram_I/sample_cnt_int(5) AND sram_I/sample_cnt_int(6) AND sram_I/sample_cnt_int(7) AND sram_I/sample_cnt_int(8) AND sram_I/sample_cnt_int(9) AND sample_cnt_en); FTCPE_sram_I/sample_cnt_int15: FTCPE port map (sram_I/sample_cnt_int(15),sram_I/sample_cnt_int_T(15),clk_ob,clr,'0'); sram_I/sample_cnt_int_T(15) <= (sram_I/sample_cnt_int(0) AND sram_I/sample_cnt_int(11) AND sram_I/sample_cnt_int(1) AND sram_I/sample_cnt_int(10) AND sram_I/sample_cnt_int(12) AND sram_I/sample_cnt_int(13) AND sram_I/sample_cnt_int(14) AND sram_I/sample_cnt_int(2) AND sram_I/sample_cnt_int(3) AND sram_I/sample_cnt_int(4) AND sram_I/sample_cnt_int(5) AND sram_I/sample_cnt_int(6) AND sram_I/sample_cnt_int(7) AND sram_I/sample_cnt_int(8) AND sram_I/sample_cnt_int(9) AND sample_cnt_en); FTCPE_sram_I/sample_cnt_int16: FTCPE port map (sram_I/sample_cnt_int(16),sram_I/sample_cnt_int_T(16),clk_ob,clr,'0'); sram_I/sample_cnt_int_T(16) <= (sram_I/sample_cnt_int(0) AND sram_I/sample_cnt_int(11) AND sram_I/sample_cnt_int(1) AND sram_I/sample_cnt_int(10) AND sram_I/sample_cnt_int(12) AND sram_I/sample_cnt_int(13) AND sram_I/sample_cnt_int(14) AND sram_I/sample_cnt_int(15) AND sram_I/sample_cnt_int(2) AND sram_I/sample_cnt_int(3) AND sram_I/sample_cnt_int(4) AND sram_I/sample_cnt_int(5) AND sram_I/sample_cnt_int(6) AND sram_I/sample_cnt_int(7) AND sram_I/sample_cnt_int(8) AND sram_I/sample_cnt_int(9) AND sample_cnt_en); FTCPE_sram_adr0: FTCPE port map (sram_adr(0),'1',clk_ob,'0','0',adr_cnt_en); FTCPE_sram_adr1: FTCPE port map (sram_adr(1),sram_adr(0),clk_ob,'0','0',adr_cnt_en); FTCPE_sram_adr2: FTCPE port map (sram_adr(2),sram_adr_T(2),clk_ob,'0','0',adr_cnt_en); sram_adr_T(2) <= (sram_adr(0) AND sram_adr(1)); FTCPE_sram_adr3: FTCPE port map (sram_adr(3),sram_adr_T(3),clk_ob,'0','0',adr_cnt_en); sram_adr_T(3) <= (sram_adr(0) AND sram_adr(1) AND sram_adr(2)); FTCPE_sram_adr4: FTCPE port map (sram_adr(4),sram_adr_T(4),clk_ob,'0','0',adr_cnt_en); sram_adr_T(4) <= (sram_adr(0) AND sram_adr(1) AND sram_adr(2) AND sram_adr(3)); FTCPE_sram_adr5: FTCPE port map (sram_adr(5),sram_adr_T(5),clk_ob,'0','0',adr_cnt_en); sram_adr_T(5) <= (sram_adr(0) AND sram_adr(1) AND sram_adr(2) AND sram_adr(3) AND sram_adr(4)); FTCPE_sram_adr6: FTCPE port map (sram_adr(6),sram_adr_T(6),clk_ob,'0','0',adr_cnt_en); sram_adr_T(6) <= (sram_adr(0) AND sram_adr(1) AND sram_adr(2) AND sram_adr(3) AND sram_adr(4) AND sram_adr(5)); FTCPE_sram_adr7: FTCPE port map (sram_adr(7),sram_adr_T(7),clk_ob,'0','0',adr_cnt_en); sram_adr_T(7) <= (sram_adr(0) AND sram_adr(1) AND sram_adr(2) AND sram_adr(3) AND sram_adr(4) AND sram_adr(5) AND sram_adr(6)); FTCPE_sram_adr8: FTCPE port map (sram_adr(8),sram_adr_T(8),clk_ob,'0','0',adr_cnt_en); sram_adr_T(8) <= (sram_adr(0) AND sram_adr(1) AND sram_adr(2) AND sram_adr(3) AND sram_adr(4) AND sram_adr(5) AND sram_adr(6) AND sram_adr(7)); FTCPE_sram_adr9: FTCPE port map (sram_adr(9),sram_adr_T(9),clk_ob,'0','0',adr_cnt_en); sram_adr_T(9) <= (sram_adr(0) AND sram_adr(1) AND sram_adr(2) AND sram_adr(3) AND sram_adr(4) AND sram_adr(5) AND sram_adr(6) AND sram_adr(7) AND sram_adr(8)); FTCPE_sram_adr10: FTCPE port map (sram_adr(10),sram_adr_T(10),clk_ob,'0','0',adr_cnt_en); sram_adr_T(10) <= (sram_adr(0) AND sram_adr(1) AND sram_adr(2) AND sram_adr(3) AND sram_adr(4) AND sram_adr(5) AND sram_adr(6) AND sram_adr(7) AND sram_adr(8) AND sram_adr(9)); FTCPE_sram_adr11: FTCPE port map (sram_adr(11),sram_adr_T(11),clk_ob,'0','0',adr_cnt_en); sram_adr_T(11) <= (sram_adr(0) AND sram_adr(10) AND sram_adr(1) AND sram_adr(2) AND sram_adr(3) AND sram_adr(4) AND sram_adr(5) AND sram_adr(6) AND sram_adr(7) AND sram_adr(8) AND sram_adr(9)); FTCPE_sram_adr12: FTCPE port map (sram_adr(12),sram_adr_T(12),clk_ob,'0','0',adr_cnt_en); sram_adr_T(12) <= (sram_adr(0) AND sram_adr(10) AND sram_adr(11) AND sram_adr(1) AND sram_adr(2) AND sram_adr(3) AND sram_adr(4) AND sram_adr(5) AND sram_adr(6) AND sram_adr(7) AND sram_adr(8) AND sram_adr(9)); FTCPE_sram_adr13: FTCPE port map (sram_adr(13),sram_adr_T(13),clk_ob,'0','0',adr_cnt_en); sram_adr_T(13) <= (sram_adr(0) AND sram_adr(10) AND sram_adr(11) AND sram_adr(12) AND sram_adr(1) AND sram_adr(2) AND sram_adr(3) AND sram_adr(4) AND sram_adr(5) AND sram_adr(6) AND sram_adr(7) AND sram_adr(8) AND sram_adr(9)); FTCPE_sram_adr14: FTCPE port map (sram_adr(14),sram_adr_T(14),clk_ob,'0','0',adr_cnt_en); sram_adr_T(14) <= (sram_adr(0) AND sram_adr(10) AND sram_adr(11) AND sram_adr(12) AND sram_adr(13) AND sram_adr(1) AND sram_adr(2) AND sram_adr(3) AND sram_adr(4) AND sram_adr(5) AND sram_adr(6) AND sram_adr(7) AND sram_adr(8) AND sram_adr(9)); FTCPE_sram_adr15: FTCPE port map (sram_adr(15),sram_adr_T(15),clk_ob,'0','0',adr_cnt_en); sram_adr_T(15) <= (sram_adr(0) AND sram_adr(10) AND sram_adr(11) AND sram_adr(12) AND sram_adr(13) AND sram_adr(14) AND sram_adr(1) AND sram_adr(2) AND sram_adr(3) AND sram_adr(4) AND sram_adr(5) AND sram_adr(6) AND sram_adr(7) AND sram_adr(8) AND sram_adr(9)); FTCPE_sram_adr16: FTCPE port map (sram_adr(16),sram_adr_T(16),clk_ob,'0','0',adr_cnt_en); sram_adr_T(16) <= (sram_adr(0) AND sram_adr(10) AND sram_adr(11) AND sram_adr(12) AND sram_adr(13) AND sram_adr(14) AND sram_adr(15) AND sram_adr(1) AND sram_adr(2) AND sram_adr(3) AND sram_adr(4) AND sram_adr(5) AND sram_adr(6) AND sram_adr(7) AND sram_adr(8) AND sram_adr(9)); sram_adsc_l <= sram_oe_l_OBUF$BUF0.EXP; sram_ce_l <= timebase_I/clk_cnt(8).EXP; sram_clk <= ((EXP58_.EXP) OR (EXP59_.EXP) OR (timebase_I/clk_2 AND NOT tsel_reg(2) AND tsel_reg(3) AND NOT clk_falling_edge AND NOT timebase_I/sw_read_clk_f AND NOT timebase_I/sw_read_clk_r) OR (timebase_I/clk_2 AND NOT tsel_reg(4) AND tsel_reg(0) AND NOT clk_falling_edge AND NOT timebase_I/sw_read_clk_f AND NOT timebase_I/sw_read_clk_r) OR (NOT timebase_I/clk_2 AND NOT tsel_reg(2) AND tsel_reg(3) AND clk_falling_edge AND NOT timebase_I/sw_read_clk_f AND NOT timebase_I/sw_read_clk_r) OR (NOT timebase_I/clk_2 AND NOT tsel_reg(4) AND tsel_reg(0) AND clk_falling_edge AND NOT timebase_I/sw_read_clk_f AND NOT timebase_I/sw_read_clk_r) OR (tsel_reg(1) AND tsel_reg(2) AND tsel_reg(3) AND tsel_reg(4) AND NOT tsel_reg(0) AND clk_falling_edge AND NOT timebase_I/sw_read_clk_f AND NOT timebase_I/sw_read_clk_r AND NOT eclk)); FDCPE_sram_d0: FDCPE port map (sram_d_I(0),channel(0),clk_ob,'0','0'); sram_d(0) <= sram_d_I(0) when sram_d_OE(0) = '1' else 'Z'; sram_d_OE(0) <= st(3); FDCPE_sram_d1: FDCPE port map (sram_d_I(1),channel(1),clk_ob,'0','0'); sram_d(1) <= sram_d_I(1) when sram_d_OE(1) = '1' else 'Z'; sram_d_OE(1) <= st(3); FDCPE_sram_d2: FDCPE port map (sram_d_I(2),channel(2),clk_ob,'0','0'); sram_d(2) <= sram_d_I(2) when sram_d_OE(2) = '1' else 'Z'; sram_d_OE(2) <= st(3); FDCPE_sram_d3: FDCPE port map (sram_d_I(3),channel(3),clk_ob,'0','0'); sram_d(3) <= sram_d_I(3) when sram_d_OE(3) = '1' else 'Z'; sram_d_OE(3) <= st(3); FDCPE_sram_d4: FDCPE port map (sram_d_I(4),channel(4),clk_ob,'0','0'); sram_d(4) <= sram_d_I(4) when sram_d_OE(4) = '1' else 'Z'; sram_d_OE(4) <= st(3); FDCPE_sram_d5: FDCPE port map (sram_d_I(5),channel(5),clk_ob,'0','0'); sram_d(5) <= sram_d_I(5) when sram_d_OE(5) = '1' else 'Z'; sram_d_OE(5) <= st(3); FDCPE_sram_d6: FDCPE port map (sram_d_I(6),channel(6),clk_ob,'0','0'); sram_d(6) <= sram_d_I(6) when sram_d_OE(6) = '1' else 'Z'; sram_d_OE(6) <= st(3); FDCPE_sram_d7: FDCPE port map (sram_d_I(7),channel(7),clk_ob,'0','0'); sram_d(7) <= sram_d_I(7) when sram_d_OE(7) = '1' else 'Z'; sram_d_OE(7) <= st(3); FDCPE_sram_d8: FDCPE port map (sram_d_I(8),channel(8),clk_ob,'0','0'); sram_d(8) <= sram_d_I(8) when sram_d_OE(8) = '1' else 'Z'; sram_d_OE(8) <= st(3); FDCPE_sram_d9: FDCPE port map (sram_d_I(9),channel(9),clk_ob,'0','0'); sram_d(9) <= sram_d_I(9) when sram_d_OE(9) = '1' else 'Z'; sram_d_OE(9) <= st(3); FDCPE_sram_d10: FDCPE port map (sram_d_I(10),channel(10),clk_ob,'0','0'); sram_d(10) <= sram_d_I(10) when sram_d_OE(10) = '1' else 'Z'; sram_d_OE(10) <= st(3); FDCPE_sram_d11: FDCPE port map (sram_d_I(11),channel(11),clk_ob,'0','0'); sram_d(11) <= sram_d_I(11) when sram_d_OE(11) = '1' else 'Z'; sram_d_OE(11) <= st(3); FDCPE_sram_d12: FDCPE port map (sram_d_I(12),channel(12),clk_ob,'0','0'); sram_d(12) <= sram_d_I(12) when sram_d_OE(12) = '1' else 'Z'; sram_d_OE(12) <= st(3); FDCPE_sram_d13: FDCPE port map (sram_d_I(13),channel(13),clk_ob,'0','0'); sram_d(13) <= sram_d_I(13) when sram_d_OE(13) = '1' else 'Z'; sram_d_OE(13) <= st(3); FDCPE_sram_d14: FDCPE port map (sram_d_I(14),channel(14),clk_ob,'0','0'); sram_d(14) <= sram_d_I(14) when sram_d_OE(14) = '1' else 'Z'; sram_d_OE(14) <= st(3); FDCPE_sram_d15: FDCPE port map (sram_d_I(15),channel(15),clk_ob,'0','0'); sram_d(15) <= sram_d_I(15) when sram_d_OE(15) = '1' else 'Z'; sram_d_OE(15) <= st(3); FDCPE_sram_d16: FDCPE port map (sram_d_I(16),channel(16),clk_ob,'0','0'); sram_d(16) <= sram_d_I(16) when sram_d_OE(16) = '1' else 'Z'; sram_d_OE(16) <= st(3); FDCPE_sram_d17: FDCPE port map (sram_d_I(17),channel(17),clk_ob,'0','0'); sram_d(17) <= sram_d_I(17) when sram_d_OE(17) = '1' else 'Z'; sram_d_OE(17) <= st(3); FDCPE_sram_d18: FDCPE port map (sram_d_I(18),channel(18),clk_ob,'0','0'); sram_d(18) <= sram_d_I(18) when sram_d_OE(18) = '1' else 'Z'; sram_d_OE(18) <= st(3); FDCPE_sram_d19: FDCPE port map (sram_d_I(19),channel(19),clk_ob,'0','0'); sram_d(19) <= sram_d_I(19) when sram_d_OE(19) = '1' else 'Z'; sram_d_OE(19) <= st(3); FDCPE_sram_d20: FDCPE port map (sram_d_I(20),channel(20),clk_ob,'0','0'); sram_d(20) <= sram_d_I(20) when sram_d_OE(20) = '1' else 'Z'; sram_d_OE(20) <= st(3); FDCPE_sram_d21: FDCPE port map (sram_d_I(21),channel(21),clk_ob,'0','0'); sram_d(21) <= sram_d_I(21) when sram_d_OE(21) = '1' else 'Z'; sram_d_OE(21) <= st(3); FDCPE_sram_d22: FDCPE port map (sram_d_I(22),channel(22),clk_ob,'0','0'); sram_d(22) <= sram_d_I(22) when sram_d_OE(22) = '1' else 'Z'; sram_d_OE(22) <= st(3); FDCPE_sram_d23: FDCPE port map (sram_d_I(23),channel(23),clk_ob,'0','0'); sram_d(23) <= sram_d_I(23) when sram_d_OE(23) = '1' else 'Z'; sram_d_OE(23) <= st(3); FDCPE_sram_d24: FDCPE port map (sram_d_I(24),channel(24),clk_ob,'0','0'); sram_d(24) <= sram_d_I(24) when sram_d_OE(24) = '1' else 'Z'; sram_d_OE(24) <= st(3); FDCPE_sram_d25: FDCPE port map (sram_d_I(25),channel(25),clk_ob,'0','0'); sram_d(25) <= sram_d_I(25) when sram_d_OE(25) = '1' else 'Z'; sram_d_OE(25) <= st(3); FDCPE_sram_d26: FDCPE port map (sram_d_I(26),channel(26),clk_ob,'0','0'); sram_d(26) <= sram_d_I(26) when sram_d_OE(26) = '1' else 'Z'; sram_d_OE(26) <= st(3); FDCPE_sram_d27: FDCPE port map (sram_d_I(27),channel(27),clk_ob,'0','0'); sram_d(27) <= sram_d_I(27) when sram_d_OE(27) = '1' else 'Z'; sram_d_OE(27) <= st(3); FDCPE_sram_d28: FDCPE port map (sram_d_I(28),channel(28),clk_ob,'0','0'); sram_d(28) <= sram_d_I(28) when sram_d_OE(28) = '1' else 'Z'; sram_d_OE(28) <= st(3); FDCPE_sram_d29: FDCPE port map (sram_d_I(29),channel(29),clk_ob,'0','0'); sram_d(29) <= sram_d_I(29) when sram_d_OE(29) = '1' else 'Z'; sram_d_OE(29) <= st(3); FDCPE_sram_d30: FDCPE port map (sram_d_I(30),channel(30),clk_ob,'0','0'); sram_d(30) <= sram_d_I(30) when sram_d_OE(30) = '1' else 'Z'; sram_d_OE(30) <= st(3); FDCPE_sram_d31: FDCPE port map (sram_d_I(31),channel(31),clk_ob,'0','0'); sram_d(31) <= sram_d_I(31) when sram_d_OE(31) = '1' else 'Z'; sram_d_OE(31) <= st(3); FDCPE_sram_oe_l: FDCPE port map (sram_oe_l,sram_oe_l_D,clk_ob,'0',clr); sram_oe_l_D <= ((state_FFd3 AND state_FFd2 AND state_FFd1) OR (NOT state_FFd3 AND state_FFd2 AND NOT state_FFd1)); FDCPE_sram_we_l: FDCPE port map (sram_we_l,sram_we_l_D,clk_ob,clr,'0'); sram_we_l_D <= ((state_FFd3 AND state_FFd2 AND state_FFd1) OR (NOT state_FFd3 AND state_FFd2 AND NOT state_FFd1)); FDCPE_st1: FDCPE port map (st(1),st_D(1),clk_ob,'0',clr); st_D(1) <= ((NOT state_FFd2) OR (NOT state_FFd3 AND NOT state_FFd1)); FDCPE_st2: FDCPE port map (st(2),st_D(2),clk_ob,'0',clr); st_D(2) <= ((NOT state_FFd3 AND NOT state_FFd2) OR (state_FFd2 AND NOT state_FFd1)); FDCPE_st3: FDCPE port map (st(3),st_D(3),clk_ob,'0',clr); st_D(3) <= ((state_FFd3 AND state_FFd2 AND state_FFd1) OR (NOT state_FFd3 AND state_FFd2 AND NOT state_FFd1)); FDCPE_state_FFd1: FDCPE port map (state_FFd1,state_FFd1_D,clk_ob,clr,'0'); state_FFd1_D <= ((EXP46_.EXP) OR (sram_adr_5_OBUF.EXP) OR (state_FFd3 AND state_FFd2 AND NOT state_FFd1) OR (state_FFd3 AND NOT state_FFd1 AND stop) OR (NOT state_FFd3 AND NOT state_FFd2 AND NOT state_FFd1) OR (NOT state_FFd3 AND state_FFd1 AND stop)); FDCPE_state_FFd2: FDCPE port map (state_FFd2,state_FFd2_D,clk_ob,clr,'0'); state_FFd2_D <= ((epp_I/bytesel(0).EXP) OR (edge_reg(9).EXP) OR (NOT state_FFd3 AND NOT state_FFd2 AND NOT state_FFd1 AND NOT run) OR (NOT state_FFd3 AND NOT state_FFd2 AND NOT state_FFd1 AND pretrig_off) OR (state_FFd3 AND state_FFd2 AND NOT state_FFd1 AND NOT stop AND sample_cnt_wm) OR (NOT trigcond_I/trig_cnt(0) AND state_FFd3 AND NOT state_FFd2 AND NOT state_FFd1 AND NOT stop AND tcnt_reg(0))); FTCPE_state_FFd3: FTCPE port map (state_FFd3,state_FFd3_T,clk_ob,clr,'0'); state_FFd3_T <= ((EXP49_.EXP) OR (state_FFd3 AND state_FFd1) OR (state_FFd2 AND state_FFd1)); FDCPE_stop: FDCPE port map (stop,dd(3).PIN,clk_in,'0','0',stop_CE); stop_CE <= (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_tcnt_reg0: FDCPE port map (tcnt_reg(0),dd(0).PIN,NOT clk_in,'0','0',tcnt_reg_CE(0)); tcnt_reg_CE(0) <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_tcnt_reg1: FDCPE port map (tcnt_reg(1),dd(1).PIN,NOT clk_in,'0','0',tcnt_reg_CE(1)); tcnt_reg_CE(1) <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_tcnt_reg2: FDCPE port map (tcnt_reg(2),dd(2).PIN,NOT clk_in,'0','0',tcnt_reg_CE(2)); tcnt_reg_CE(2) <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_tcnt_reg3: FDCPE port map (tcnt_reg(3),dd(3).PIN,NOT clk_in,'0','0',tcnt_reg_CE(3)); tcnt_reg_CE(3) <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FTCPE_timebase_I/clk_2: FTCPE port map (timebase_I/clk_2,'1',clk_in,clr,'0',timebase_I/clk_2_CE); timebase_I/clk_2_CE <= (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND NOT timebase_I/clk_cnt(18)); FTCPE_timebase_I/clk_5f0: FTCPE port map (timebase_I/clk_5f(0),timebase_I/clk_5f_T(0),NOT clk_in,clr,'0'); timebase_I/clk_5f_T(0) <= (NOT timebase_I/clk_5f(0) AND NOT timebase_I/clk_5f(1) AND NOT timebase_I/clk_5f(2)); FDCPE_timebase_I/clk_5f1: FDCPE port map (timebase_I/clk_5f(1),timebase_I/clk_5f_D(1),NOT clk_in,clr,'0'); timebase_I/clk_5f_D(1) <= ((timebase_I/clk_5f(0) AND timebase_I/clk_5f(1)) OR (NOT timebase_I/clk_5f(0) AND NOT timebase_I/clk_5f(1) AND timebase_I/clk_5f(2))); FTCPE_timebase_I/clk_5f2: FTCPE port map (timebase_I/clk_5f(2),timebase_I/clk_5f_T(2),NOT clk_in,clr,'0'); timebase_I/clk_5f_T(2) <= (NOT timebase_I/clk_5f(0) AND NOT timebase_I/clk_5f(1)); FTCPE_timebase_I/clk_cnt0: FTCPE port map (timebase_I/clk_cnt(0),timebase_I/clk_cnt_T(0),clk_in,clr,'0'); timebase_I/clk_cnt_T(0) <= ((trig_o_OBUF.EXP) OR (tsel_reg(2) AND tsel_reg(4) AND NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND NOT timebase_I/clk_cnt(18)) OR (tsel_reg(3) AND tsel_reg(4) AND NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND NOT timebase_I/clk_cnt(18)) OR (tsel_reg(1) AND tsel_reg(4) AND tsel_reg(0) AND NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND NOT timebase_I/clk_cnt(18)) OR (NOT tsel_reg(2) AND NOT tsel_reg(3) AND NOT tsel_reg(4) AND NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND NOT timebase_I/clk_cnt(18))); FTCPE_timebase_I/clk_cnt1: FTCPE port map (timebase_I/clk_cnt(1),timebase_I/clk_cnt_T(1),clk_in,clr,'0'); timebase_I/clk_cnt_T(1) <= ((EXP51_.EXP) OR (NOT tsel_reg(1) AND NOT tsel_reg(3) AND NOT tsel_reg(4) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND NOT timebase_I/clk_cnt(18)) OR (NOT tsel_reg(2) AND NOT tsel_reg(3) AND NOT tsel_reg(4) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND NOT timebase_I/clk_cnt(18)) OR (NOT tsel_reg(3) AND NOT tsel_reg(4) AND NOT tsel_reg(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND NOT timebase_I/clk_cnt(18)) OR (NOT tsel_reg(1) AND NOT tsel_reg(2) AND NOT tsel_reg(4) AND NOT tsel_reg(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND NOT timebase_I/clk_cnt(18))); FTCPE_timebase_I/clk_cnt2: FTCPE port map (timebase_I/clk_cnt(2),timebase_I/clk_cnt_T(2),clk_in,clr,'0'); timebase_I/clk_cnt_T(2) <= ((timebase_I/clk_cnt(0)) OR (timebase_I/clk_cnt(1)) OR (channel_reg(6).EXP) OR (tsel_reg(2) AND NOT tsel_reg(3) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND NOT timebase_I/clk_cnt(18)) OR (tsel_reg(3) AND tsel_reg(4) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND NOT timebase_I/clk_cnt(18))); FTCPE_timebase_I/clk_cnt3: FTCPE port map (timebase_I/clk_cnt(3),timebase_I/clk_cnt_T(3),clk_in,clr,'0'); timebase_I/clk_cnt_T(3) <= ((timebase_I/clk_cnt(0)) OR (timebase_I/clk_cnt(1)) OR (timebase_I/clk_cnt(2)) OR (EXP42_.EXP) OR (timebase_I/clk_cnt(6).EXP) OR (NOT tsel_reg(2) AND NOT tsel_reg(3) AND NOT tsel_reg(4) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND NOT timebase_I/clk_cnt(18))); FTCPE_timebase_I/clk_cnt4: FTCPE port map (timebase_I/clk_cnt(4),timebase_I/clk_cnt_T(4),clk_in,clr,'0'); timebase_I/clk_cnt_T(4) <= ((sram_adsc_l_OBUF$BUF0.EXP) OR (sram_adr_8_OBUF.EXP) OR (tsel_reg(1) AND tsel_reg(3) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND NOT timebase_I/clk_cnt(18)) OR (tsel_reg(4) AND tsel_reg(0) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND NOT timebase_I/clk_cnt(18)) OR (NOT tsel_reg(1) AND tsel_reg(2) AND NOT tsel_reg(0) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND NOT timebase_I/clk_cnt(18)) OR (NOT tsel_reg(2) AND NOT tsel_reg(3) AND NOT tsel_reg(4) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND NOT timebase_I/clk_cnt(18))); FTCPE_timebase_I/clk_cnt5: FTCPE port map (timebase_I/clk_cnt(5),timebase_I/clk_cnt_T(5),clk_in,clr,'0'); timebase_I/clk_cnt_T(5) <= ((timebase_I/clk_cnt(0)) OR (timebase_I/clk_cnt(1)) OR (timebase_I/clk_cnt(2)) OR (timebase_I/clk_cnt(3)) OR (EXP52_.EXP) OR (sram_adr_2_OBUF.EXP)); FTCPE_timebase_I/clk_cnt6: FTCPE port map (timebase_I/clk_cnt(6),timebase_I/clk_cnt_T(6),clk_in,clr,'0'); timebase_I/clk_cnt_T(6) <= ((timebase_I/clk_cnt(0)) OR (timebase_I/clk_cnt(1)) OR (EXP32_.EXP)); FTCPE_timebase_I/clk_cnt7: FTCPE port map (timebase_I/clk_cnt(7),timebase_I/clk_cnt_T(7),clk_in,clr,'0'); timebase_I/clk_cnt_T(7) <= ((timebase_I/clk_cnt(0)) OR (timebase_I/clk_cnt(1)) OR (timebase_I/clk_cnt(10).EXP) OR (EXP36_.EXP) OR (tsel_reg(1) AND tsel_reg(4) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND NOT timebase_I/clk_cnt(18)) OR (tsel_reg(2) AND tsel_reg(4) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND NOT timebase_I/clk_cnt(18))); FTCPE_timebase_I/clk_cnt8: FTCPE port map (timebase_I/clk_cnt(8),timebase_I/clk_cnt_T(8),clk_in,clr,'0'); timebase_I/clk_cnt_T(8) <= ((timebase_I/clk_cnt(0)) OR (EXP55_.EXP) OR (tsel_reg(2) AND tsel_reg(4) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND NOT timebase_I/clk_cnt(18)) OR (tsel_reg(4) AND tsel_reg(0) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND NOT timebase_I/clk_cnt(18))); FTCPE_timebase_I/clk_cnt9: FTCPE port map (timebase_I/clk_cnt(9),timebase_I/clk_cnt_T(9),clk_in,clr,'0'); timebase_I/clk_cnt_T(9) <= ((sram_adsc_l_OBUF.EXP) OR (EXP61_.EXP) OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8)) OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8)) OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8)) OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND timebase_I/clk_cnt(18))); FTCPE_timebase_I/clk_cnt10: FTCPE port map (timebase_I/clk_cnt(10),timebase_I/clk_cnt_T(10),clk_in,clr,'0'); timebase_I/clk_cnt_T(10) <= ((EXP35_.EXP) OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9))); FTCPE_timebase_I/clk_cnt11: FTCPE port map (timebase_I/clk_cnt(11),timebase_I/clk_cnt_T(11),clk_in,clr,'0'); timebase_I/clk_cnt_T(11) <= ((timebase_I/clk_cnt(14).EXP) OR (sram_adr_7_OBUF.EXP) OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9)) OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9)) OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9)) OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND timebase_I/clk_cnt(18))); FTCPE_timebase_I/clk_cnt12: FTCPE port map (timebase_I/clk_cnt(12),timebase_I/clk_cnt_T(12),clk_in,clr,'0'); timebase_I/clk_cnt_T(12) <= ((EXP53_.EXP) OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9)) OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9)) OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9)) OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND timebase_I/clk_cnt(18))); FTCPE_timebase_I/clk_cnt13: FTCPE port map (timebase_I/clk_cnt(13),timebase_I/clk_cnt_T(13),clk_in,clr,'0'); timebase_I/clk_cnt_T(13) <= ((sram_adr_0_OBUF.EXP) OR (sram_adr_6_OBUF.EXP) OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9)) OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9)) OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9)) OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND timebase_I/clk_cnt(18))); FTCPE_timebase_I/clk_cnt14: FTCPE port map (timebase_I/clk_cnt(14),timebase_I/clk_cnt_T(14),clk_in,clr,'0'); timebase_I/clk_cnt_T(14) <= ((EXP50_.EXP) OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9)) OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND timebase_I/clk_cnt(18))); FTCPE_timebase_I/clk_cnt15: FTCPE port map (timebase_I/clk_cnt(15),timebase_I/clk_cnt_T(15),clk_in,clr,'0'); timebase_I/clk_cnt_T(15) <= ((timebase_I/clk_2.EXP) OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9)) OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9)) OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND timebase_I/clk_cnt(18)) OR (NOT tsel_reg(1) AND NOT tsel_reg(2) AND NOT tsel_reg(3) AND tsel_reg(4) AND NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9))); FTCPE_timebase_I/clk_cnt16: FTCPE port map (timebase_I/clk_cnt(16),timebase_I/clk_cnt_T(16),clk_in,clr,'0'); timebase_I/clk_cnt_T(16) <= ((channel_reg(5).EXP) OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9)) OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND timebase_I/clk_cnt(18)) OR (NOT tsel_reg(1) AND NOT tsel_reg(2) AND NOT tsel_reg(3) AND tsel_reg(4) AND NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9)) OR (NOT tsel_reg(2) AND NOT tsel_reg(3) AND tsel_reg(4) AND NOT tsel_reg(0) AND NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9))); FTCPE_timebase_I/clk_cnt17: FTCPE port map (timebase_I/clk_cnt(17),timebase_I/clk_cnt_T(17),clk_in,clr,'0'); timebase_I/clk_cnt_T(17) <= ((NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(16) AND timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9)) OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND timebase_I/clk_cnt(18)) OR (tsel_reg(1) AND NOT tsel_reg(2) AND NOT tsel_reg(3) AND tsel_reg(4) AND NOT tsel_reg(0) AND NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9)) OR (NOT tsel_reg(1) AND NOT tsel_reg(2) AND NOT tsel_reg(3) AND tsel_reg(4) AND tsel_reg(0) AND NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9))); FTCPE_timebase_I/clk_cnt18: FTCPE port map (timebase_I/clk_cnt(18),timebase_I/clk_cnt_T(18),clk_in,clr,'0'); timebase_I/clk_cnt_T(18) <= ((NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND timebase_I/clk_cnt(18)) OR (tsel_reg(1) AND NOT tsel_reg(2) AND NOT tsel_reg(3) AND tsel_reg(4) AND NOT tsel_reg(0) AND NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9))); FDCPE_timebase_I/sw_read_clk_f: FDCPE port map (timebase_I/sw_read_clk_f,done,NOT clk_o,clr,'0'); FDCPE_timebase_I/sw_read_clk_r: FDCPE port map (timebase_I/sw_read_clk_r,done,clk_o,clr,'0'); FDCPE_tlen_reg0: FDCPE port map (tlen_reg(0),dd(0).PIN,NOT clk_in,'0','0',tlen_reg_CE(0)); tlen_reg_CE(0) <= (epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_tlen_reg1: FDCPE port map (tlen_reg(1),dd(1).PIN,NOT clk_in,'0','0',tlen_reg_CE(1)); tlen_reg_CE(1) <= (epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_tlen_reg2: FDCPE port map (tlen_reg(2),dd(2).PIN,NOT clk_in,'0','0',tlen_reg_CE(2)); tlen_reg_CE(2) <= (epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_tlen_reg3: FDCPE port map (tlen_reg(3),dd(3).PIN,NOT clk_in,'0','0',tlen_reg_CE(3)); tlen_reg_CE(3) <= (epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); trig_o <= NOT (((EXP24_.EXP) OR (trigcond_I/trig_cnt(0) AND NOT tcnt_reg(0)) OR (NOT trigcond_I/trig_cnt(0) AND tcnt_reg(0)) OR (trigcond_I/trig_cnt(1) AND NOT tcnt_reg(1)) OR (NOT trigcond_I/trig_cnt(1) AND tcnt_reg(1)))); FDCPE_trig_on: FDCPE port map (trig_on,trig_on_D,clk_ob,clr,'0'); trig_on_D <= (state_FFd3 AND NOT state_FFd2); FDCPE_trigcond_I/extrig_int: FDCPE port map (trigcond_I/extrig_int,trigcond_I/trig_on_d.EXP,clk_ob,'0','0'); FDCPE_trigcond_I/int_etrig_hit_reg: FDCPE port map (trigcond_I/int_etrig_hit_reg,trigcond_I/int_etrig_hit_reg_D,clk_ob,clr,'0'); trigcond_I/int_etrig_hit_reg_D <= ((EXP44_.EXP) OR (EXP45_.EXP) OR (edge_reg(2) AND NOT $OpTx$trigcond_I/int_vtrig_comp(2)/trigcond_I/int_vtrig_comp(2)_D2_INV$526) OR (edge_reg(3) AND NOT $OpTx$trigcond_I/int_vtrig_comp(3)/trigcond_I/int_vtrig_comp(3)_D2_INV$527) OR (edge_reg(4) AND NOT $OpTx$trigcond_I/int_vtrig_comp(4)/trigcond_I/int_vtrig_comp(4)_D2_INV$528) OR (edge_reg(5) AND NOT $OpTx$trigcond_I/int_vtrig_comp(5)/trigcond_I/int_vtrig_comp(5)_D2_INV$529)); FDCPE_trigcond_I/int_trig_hit_reg: FDCPE port map (trigcond_I/int_trig_hit_reg,trigcond_I/int_trig_hit_reg_D,clk_ob,clr,'0'); trigcond_I/int_trig_hit_reg_D <= (( $OpTx$trigcond_I/int_vtrig_comp(2)/trigcond_I/int_vtrig_comp(2)_D2_INV$526) OR ( $OpTx$trigcond_I/int_vtrig_comp(5)/trigcond_I/int_vtrig_comp(5)_D2_INV$529) OR ( $OpTx$trigcond_I/int_vtrig_comp(3)/trigcond_I/int_vtrig_comp(3)_D2_INV$527) OR ( $OpTx$trigcond_I/int_vtrig_comp(6)/trigcond_I/int_vtrig_comp(6)_D2_INV$530) OR (EXP63_.EXP) OR (EXP64_.EXP)); FDCPE_trigcond_I/tlen_cnt0: FDCPE port map (trigcond_I/tlen_cnt(0),trigcond_I/tlen_cnt_D(0),clk_ob,clr,'0'); trigcond_I/tlen_cnt_D(0) <= ((EXP67_.EXP) OR (EXP68_.EXP) OR (NOT trigcond_I/tlen_cnt(1) AND trigcond_I/tlen_cnt(2) AND trigcond_I/tlen_cnt(3) AND NOT tlen_reg(0) AND NOT tlen_reg(1) AND tlen_reg(2) AND tlen_reg(3)) OR (NOT trigcond_I/tlen_cnt(1) AND trigcond_I/tlen_cnt(2) AND NOT trigcond_I/tlen_cnt(3) AND NOT tlen_reg(0) AND NOT tlen_reg(1) AND tlen_reg(2) AND NOT tlen_reg(3)) OR (NOT trigcond_I/tlen_cnt(1) AND NOT trigcond_I/tlen_cnt(2) AND trigcond_I/tlen_cnt(3) AND NOT tlen_reg(0) AND NOT tlen_reg(1) AND NOT tlen_reg(2) AND tlen_reg(3)) OR (NOT trigcond_I/tlen_cnt(1) AND NOT trigcond_I/tlen_cnt(2) AND NOT trigcond_I/tlen_cnt(3) AND NOT tlen_reg(0) AND NOT tlen_reg(1) AND NOT tlen_reg(2) AND NOT tlen_reg(3))); FDCPE_trigcond_I/tlen_cnt1: FDCPE port map (trigcond_I/tlen_cnt(1),trigcond_I/tlen_cnt_D(1),clk_ob,clr,'0'); trigcond_I/tlen_cnt_D(1) <= ((EXP65_.EXP) OR (EXP69_.EXP) OR (trigcond_I/tlen_cnt(0) AND trigcond_I/tlen_cnt(2) AND trigcond_I/tlen_cnt(3) AND tlen_reg(0) AND NOT tlen_reg(1) AND tlen_reg(2) AND tlen_reg(3)) OR (trigcond_I/tlen_cnt(0) AND trigcond_I/tlen_cnt(2) AND NOT trigcond_I/tlen_cnt(3) AND tlen_reg(0) AND NOT tlen_reg(1) AND tlen_reg(2) AND NOT tlen_reg(3)) OR (trigcond_I/tlen_cnt(0) AND NOT trigcond_I/tlen_cnt(2) AND trigcond_I/tlen_cnt(3) AND tlen_reg(0) AND NOT tlen_reg(1) AND NOT tlen_reg(2) AND tlen_reg(3)) OR (trigcond_I/tlen_cnt(0) AND NOT trigcond_I/tlen_cnt(2) AND NOT trigcond_I/tlen_cnt(3) AND tlen_reg(0) AND NOT tlen_reg(1) AND NOT tlen_reg(2) AND NOT tlen_reg(3))); FDCPE_trigcond_I/tlen_cnt2: FDCPE port map (trigcond_I/tlen_cnt(2),trigcond_I/tlen_cnt_D(2),clk_ob,clr,'0'); trigcond_I/tlen_cnt_D(2) <= ((NOT trigcond_I/trig_on_d) OR (EXP30_.EXP) OR (trigcond_I/trig_cnt(1).EXP) OR (trigcond_I/tlen_cnt(0) AND trigcond_I/tlen_cnt(1) AND trigcond_I/tlen_cnt(2) AND NOT tlen_reg(2)) OR (NOT trigcond_I/tlen_cnt(2) AND trigcond_I/tlen_cnt(3) AND tlen_reg(0) AND tlen_reg(1) AND NOT tlen_reg(2) AND tlen_reg(3)) OR (NOT trigcond_I/tlen_cnt(2) AND NOT trigcond_I/tlen_cnt(3) AND tlen_reg(0) AND tlen_reg(1) AND NOT tlen_reg(2) AND NOT tlen_reg(3))); FDCPE_trigcond_I/tlen_cnt3: FDCPE port map (trigcond_I/tlen_cnt(3),trigcond_I/tlen_cnt_D(3),clk_ob,clr,'0'); trigcond_I/tlen_cnt_D(3) <= ((NOT trigcond_I/trig_on_d) OR (EXP29_.EXP) OR (trigcond_I/tlen_cnt(0) AND trigcond_I/tlen_cnt(1) AND trigcond_I/tlen_cnt(2) AND tlen_reg(0) AND tlen_reg(1) AND tlen_reg(2) AND NOT tlen_reg(3))); FDCPE_trigcond_I/tlen_top_d: FDCPE port map (trigcond_I/tlen_top_d,trigcond_I/tlen_top_d_D,clk_ob,clr,'0'); trigcond_I/tlen_top_d_D <= ((sram_adr_4_OBUF.EXP) OR (sram_adr_3_OBUF.EXP) OR (trigcond_I/tlen_cnt(2) AND NOT tlen_reg(2)) OR (NOT trigcond_I/tlen_cnt(2) AND tlen_reg(2)) OR (trigcond_I/tlen_cnt(3) AND NOT tlen_reg(3)) OR (NOT trigcond_I/tlen_cnt(3) AND tlen_reg(3))); FTCPE_trigcond_I/trig_cnt0: FTCPE port map (trigcond_I/trig_cnt(0),trigcond_I/trig_cnt_T(0),clk_ob,clr,'0'); trigcond_I/trig_cnt_T(0) <= ((trigcond_I/tlen_top_d) OR (EXP23_.EXP) OR (NOT trigcond_I/tlen_cnt(2) AND tlen_reg(2)) OR (trigcond_I/tlen_cnt(3) AND NOT tlen_reg(3)) OR (NOT trigcond_I/tlen_cnt(3) AND tlen_reg(3))); FTCPE_trigcond_I/trig_cnt1: FTCPE port map (trigcond_I/trig_cnt(1),trigcond_I/trig_cnt_T(1),clk_ob,clr,'0'); trigcond_I/trig_cnt_T(1) <= ((EXP31_.EXP) OR (trigcond_I/tlen_cnt(0) AND NOT tlen_reg(0))); FTCPE_trigcond_I/trig_cnt2: FTCPE port map (trigcond_I/trig_cnt(2),trigcond_I/trig_cnt_T(2),clk_ob,clr,'0'); trigcond_I/trig_cnt_T(2) <= ((EXP26_.EXP) OR (trigcond_I/tlen_cnt(0) AND NOT tlen_reg(0))); FTCPE_trigcond_I/trig_cnt3: FTCPE port map (trigcond_I/trig_cnt(3),trigcond_I/trig_cnt_T(3),clk_ob,clr,'0'); trigcond_I/trig_cnt_T(3) <= ((trigcond_I/trig_cnt(2).EXP) OR (EXP27_.EXP) OR (trigcond_I/tlen_cnt(0) AND NOT tlen_reg(0)) OR (NOT trigcond_I/tlen_cnt(0) AND tlen_reg(0)) OR (trigcond_I/tlen_cnt(1) AND NOT tlen_reg(1)) OR (NOT trigcond_I/tlen_cnt(1) AND tlen_reg(1))); FDCPE_trigcond_I/trig_on_d: FDCPE port map (trigcond_I/trig_on_d,trig_on,clk_ob,clr,'0'); FDCPE_tsel_reg0: FDCPE port map (tsel_reg(0),dd(0).PIN,NOT clk_in,'0','0',tsel_reg_CE(0)); tsel_reg_CE(0) <= (epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_tsel_reg1: FDCPE port map (tsel_reg(1),dd(1).PIN,NOT clk_in,'0','0',tsel_reg_CE(1)); tsel_reg_CE(1) <= (epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_tsel_reg2: FDCPE port map (tsel_reg(2),dd(2).PIN,NOT clk_in,'0','0',tsel_reg_CE(2)); tsel_reg_CE(2) <= (epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_tsel_reg3: FDCPE port map (tsel_reg(3),dd(3).PIN,NOT clk_in,'0','0',tsel_reg_CE(3)); tsel_reg_CE(3) <= (epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_tsel_reg4: FDCPE port map (tsel_reg(4),dd(4).PIN,NOT clk_in,'0','0',tsel_reg_CE(4)); tsel_reg_CE(4) <= (epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_value_reg0: FDCPE port map (value_reg(0),dd(0).PIN,NOT clk_in,'0','0',value_reg_CE(0)); value_reg_CE(0) <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_value_reg1: FDCPE port map (value_reg(1),dd(1).PIN,NOT clk_in,'0','0',value_reg_CE(1)); value_reg_CE(1) <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_value_reg2: FDCPE port map (value_reg(2),dd(2).PIN,NOT clk_in,'0','0',value_reg_CE(2)); value_reg_CE(2) <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_value_reg3: FDCPE port map (value_reg(3),dd(3).PIN,NOT clk_in,'0','0',value_reg_CE(3)); value_reg_CE(3) <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_value_reg4: FDCPE port map (value_reg(4),dd(4).PIN,NOT clk_in,'0','0',value_reg_CE(4)); value_reg_CE(4) <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_value_reg5: FDCPE port map (value_reg(5),dd(5).PIN,NOT clk_in,'0','0',value_reg_CE(5)); value_reg_CE(5) <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_value_reg6: FDCPE port map (value_reg(6),dd(6).PIN,NOT clk_in,'0','0',value_reg_CE(6)); value_reg_CE(6) <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_value_reg7: FDCPE port map (value_reg(7),dd(7).PIN,NOT clk_in,'0','0',value_reg_CE(7)); value_reg_CE(7) <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_value_reg8: FDCPE port map (value_reg(8),dd(0).PIN,NOT clk_in,'0','0',value_reg_CE(8)); value_reg_CE(8) <= (epp_I/adr(1) AND NOT epp_I/adr(0) AND epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_value_reg9: FDCPE port map (value_reg(9),dd(1).PIN,NOT clk_in,'0','0',value_reg_CE(9)); value_reg_CE(9) <= (epp_I/adr(1) AND NOT epp_I/adr(0) AND epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_value_reg10: FDCPE port map (value_reg(10),dd(2).PIN,NOT clk_in,'0','0',value_reg_CE(10)); value_reg_CE(10) <= (epp_I/adr(1) AND NOT epp_I/adr(0) AND epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_value_reg11: FDCPE port map (value_reg(11),dd(3).PIN,NOT clk_in,'0','0',value_reg_CE(11)); value_reg_CE(11) <= (epp_I/adr(1) AND NOT epp_I/adr(0) AND epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_value_reg12: FDCPE port map (value_reg(12),dd(4).PIN,NOT clk_in,'0','0',value_reg_CE(12)); value_reg_CE(12) <= (epp_I/adr(1) AND NOT epp_I/adr(0) AND epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_value_reg13: FDCPE port map (value_reg(13),dd(5).PIN,NOT clk_in,'0','0',value_reg_CE(13)); value_reg_CE(13) <= (epp_I/adr(1) AND NOT epp_I/adr(0) AND epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_value_reg14: FDCPE port map (value_reg(14),dd(6).PIN,NOT clk_in,'0','0',value_reg_CE(14)); value_reg_CE(14) <= (epp_I/adr(1) AND NOT epp_I/adr(0) AND epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); FDCPE_value_reg15: FDCPE port map (value_reg(15),dd(7).PIN,NOT clk_in,'0','0',value_reg_CE(15)); value_reg_CE(15) <= (epp_I/adr(1) AND NOT epp_I/adr(0) AND epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i); Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC95288XL-6-TQ144 Pin Signal Pin Signal No. Name No. Name 1 VCC 73 VCC 2 channel<7> 74 sram_clk 3 channel<23> 75 sram_we_l 4 channel<6> 76 sram_oe_l 5 channel<22> 77 sram_adsc_l 6 channel<5> 78 sram_adr<8> 7 channel<21> 79 sram_adr<9> 8 VCC 80 sram_adr<10> 9 channel<4> 81 sram_adr<11> 10 channel<20> 82 sram_adr<12> 11 channel<3> 83 sram_adr<13> 12 channel<19> 84 VCC 13 channel<2> 85 sram_adr<14> 14 channel<18> 86 sram_adr<15> 15 channel<1> 87 sram_adr<16> 16 channel<17> 88 sram_d<15> 17 channel<0> 89 GND 18 GND 90 GND 19 channel<16> 91 sram_d<14> 20 trig_o 92 sram_d<13> 21 KPR 93 sram_d<12> 22 KPR 94 sram_d<11> 23 KPR 95 sram_d<10> 24 etrg 96 sram_d<9> 25 KPR 97 sram_d<8> 26 KPR 98 sram_d<7> 27 KPR 99 GND 28 eclk 100 sram_d<6> 29 GND 101 sram_d<5> 30 clk_ob 102 sram_d<4> 31 KPR 103 sram_d<3> 32 clk_o 104 sram_d<2> 33 st<1> 105 sram_d<1> 34 st<2> 106 sram_d<0> 35 st<3> 107 dwr_l 36 GND 108 GND 37 VCC 109 VCC 38 clk_in 110 drd_l 39 KPR 111 dd<0> 40 sram_d<31> 112 dd<1> 41 sram_d<30> 113 dd<2> 42 VCC 114 GND 43 sram_d<29> 115 dale_l 44 sram_d<28> 116 dd<3> 45 sram_d<27> 117 dd<4> 46 sram_d<26> 118 dd<5> 47 GND 119 dd<6> 48 sram_d<25> 120 dd<7> 49 sram_d<24> 121 KPR 50 sram_d<23> 122 TDO 51 sram_d<22> 123 GND 52 sram_d<21> 124 KPR 53 sram_d<20> 125 KPR 54 sram_d<19> 126 channel<31> 55 VCC 127 VCC 56 sram_d<18> 128 channel<15> 57 sram_d<17> 129 channel<30> 58 sram_d<16> 130 channel<14> 59 sram_adr<5> 131 channel<29> 60 sram_adr<4> 132 channel<13> 61 sram_adr<3> 133 channel<28> 62 GND 134 channel<12> 63 TDI 135 channel<27> 64 sram_adr<2> 136 channel<11> 65 TMS 137 channel<26> 66 sram_adr<1> 138 channel<10> 67 TCK 139 channel<25> 68 sram_adr<0> 140 channel<9> 69 sram_adr<6> 141 VCC 70 sram_adr<7> 142 channel<24> 71 sram_ce_l 143 channel<8> 72 GND 144 GND Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal KPR = Unused I/O with weak keeper (leave unconnected) VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc95288xl-6-TQ144 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : ON Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Ground on Unused IOs : OFF Set I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 54 Pterm Limit : 25