Equations

********** Mapped Logic **********
$OpTx$$OpTx$FX_DC$187_INV$520 <= (epp_I/adr(1) AND NOT epp_I/adr(0));
$OpTx$trigcond_I/int_vtrig_comp(2)/trigcond_I/int_vtrig_comp(2)_D2_INV$526 <= ((channel(2) AND mask_reg(2) AND NOT value_reg(2))
      OR (NOT channel(2) AND mask_reg(2) AND value_reg(2)));
$OpTx$trigcond_I/int_vtrig_comp(3)/trigcond_I/int_vtrig_comp(3)_D2_INV$527 <= ((channel(3) AND mask_reg(3) AND NOT value_reg(3))
      OR (NOT channel(3) AND mask_reg(3) AND value_reg(3)));
$OpTx$trigcond_I/int_vtrig_comp(4)/trigcond_I/int_vtrig_comp(4)_D2_INV$528 <= ((channel(4) AND mask_reg(4) AND NOT value_reg(4))
      OR (NOT channel(4) AND mask_reg(4) AND value_reg(4)));
$OpTx$trigcond_I/int_vtrig_comp(5)/trigcond_I/int_vtrig_comp(5)_D2_INV$529 <= ((channel(5) AND mask_reg(5) AND NOT value_reg(5))
      OR (NOT channel(5) AND mask_reg(5) AND value_reg(5)));
$OpTx$trigcond_I/int_vtrig_comp(6)/trigcond_I/int_vtrig_comp(6)_D2_INV$530 <= ((channel(6) AND mask_reg(6) AND NOT value_reg(6))
      OR (NOT channel(6) AND mask_reg(6) AND value_reg(6)));
$OpTx$trigcond_I/int_vtrig_comp(8)/trigcond_I/int_vtrig_comp(8)_D2_INV$531 <= ((channel(8) AND mask_reg(8) AND NOT value_reg(8))
      OR (NOT channel(8) AND mask_reg(8) AND value_reg(8)));
$OpTx$trigcond_I/int_vtrig_comp(9)/trigcond_I/int_vtrig_comp(9)_D2_INV$532 <= ((channel(9) AND mask_reg(9) AND NOT value_reg(9))
      OR (NOT channel(9) AND mask_reg(9) AND value_reg(9)));
$OpTx$trigcond_I/int_vtrig_comp(10)/trigcond_I/int_vtrig_comp(10)_D2_INV$521 <= ((channel(10) AND mask_reg(10) AND NOT value_reg(10))
      OR (NOT channel(10) AND mask_reg(10) AND value_reg(10)));
$OpTx$trigcond_I/int_vtrig_comp(11)/trigcond_I/int_vtrig_comp(11)_D2_INV$522 <= ((channel(11) AND mask_reg(11) AND NOT value_reg(11))
      OR (NOT channel(11) AND mask_reg(11) AND value_reg(11)));
$OpTx$trigcond_I/int_vtrig_comp(12)/trigcond_I/int_vtrig_comp(12)_D2_INV$523 <= ((channel(12) AND mask_reg(12) AND NOT value_reg(12))
      OR (NOT channel(12) AND mask_reg(12) AND value_reg(12)));
$OpTx$trigcond_I/int_vtrig_comp(14)/trigcond_I/int_vtrig_comp(14)_D2_INV$524 <= ((channel(14) AND mask_reg(14) AND NOT value_reg(14))
      OR (NOT channel(14) AND mask_reg(14) AND value_reg(14)));
$OpTx$trigcond_I/int_vtrig_comp(15)/trigcond_I/int_vtrig_comp(15)_D2_INV$525 <= ((channel(15) AND mask_reg(15) AND NOT value_reg(15))
      OR (NOT channel(15) AND mask_reg(15) AND value_reg(15)));
FDCPE_adr_cnt_en: FDCPE port map (adr_cnt_en,adr_cnt_en_D,clk_ob,clr,'0');
     adr_cnt_en_D <= (NOT state_FFd3 AND NOT state_FFd2 AND NOT state_FFd1);
FDCPE_clk_falling_edge: FDCPE port map (clk_falling_edge,dd(5).PIN,NOT clk_in,'0','0',clk_falling_edge_CE);
     clk_falling_edge_CE <= (epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
clk_o <= NOT (((EXP41_.EXP)
      OR (st_0.EXP)
      OR (NOT timebase_I/clk_2 AND NOT tsel_reg(1) AND tsel_reg(4))
      OR (NOT timebase_I/clk_2 AND tsel_reg(2) AND NOT tsel_reg(4))
      OR (NOT timebase_I/clk_2 AND NOT tsel_reg(2) AND tsel_reg(4))
      OR (NOT timebase_I/clk_2 AND NOT tsel_reg(3) AND tsel_reg(4))
      OR (NOT timebase_I/clk_2 AND NOT tsel_reg(4) AND tsel_reg(0))));
clk_ob <= ((EXP38_.EXP)
      OR (EXP39_.EXP)
      OR (timebase_I/clk_2 AND NOT tsel_reg(2) AND tsel_reg(3) AND
      NOT clk_falling_edge AND NOT timebase_I/sw_read_clk_f AND
      NOT timebase_I/sw_read_clk_r)
      OR (timebase_I/clk_2 AND NOT tsel_reg(4) AND tsel_reg(0) AND
      NOT clk_falling_edge AND NOT timebase_I/sw_read_clk_f AND
      NOT timebase_I/sw_read_clk_r)
      OR (NOT timebase_I/clk_2 AND NOT tsel_reg(2) AND tsel_reg(3) AND
      clk_falling_edge AND NOT timebase_I/sw_read_clk_f AND
      NOT timebase_I/sw_read_clk_r)
      OR (NOT timebase_I/clk_2 AND NOT tsel_reg(4) AND tsel_reg(0) AND
      clk_falling_edge AND NOT timebase_I/sw_read_clk_f AND
      NOT timebase_I/sw_read_clk_r)
      OR (tsel_reg(1) AND tsel_reg(2) AND tsel_reg(3) AND
      tsel_reg(4) AND NOT tsel_reg(0) AND clk_falling_edge AND
      NOT timebase_I/sw_read_clk_f AND NOT timebase_I/sw_read_clk_r AND NOT eclk));
FDCPE_clk_rd: FDCPE port map (clk_rd,clk_rd_D,clk_in,'0','0',clk_rd_CE);
     clk_rd_D <= ((dd(5).PIN AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND
      NOT epp_I/WR_l_i)
      OR (epp_I/bytesel(0) AND epp_I/bytesel(1) AND
      epp_I/auto_inc AND epp_I/ALE_l_i AND epp_I/d_rd_i_d)
      OR (epp_I/bytesel(0) AND epp_I/bytesel(1) AND
      epp_I/auto_inc AND epp_I/RD_l_i AND epp_I/WR_l_i AND epp_I/d_rd_i_d)
      OR (epp_I/bytesel(0) AND epp_I/bytesel(1) AND
      epp_I/auto_inc AND NOT epp_I/RD_l_i AND NOT epp_I/WR_l_i AND epp_I/d_rd_i_d));
     clk_rd_CE <= (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND
      NOT epp_I/adr(3));
FDCPE_clr: FDCPE port map (clr,dd(6).PIN,clk_in,'0','0',clr_CE);
     clr_CE <= (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
dd_I(0) <= NOT (((sram_I/sample_cnt_int(7).EXP)
      OR (epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i)
      OR (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND
      NOT epp_I/adr(3) AND epp_I/bytesel(0) AND epp_I/bytesel(1) AND
      NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i AND NOT sram_d(24).PIN)
      OR (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND
      NOT epp_I/adr(3) AND epp_I/bytesel(0) AND NOT epp_I/bytesel(1) AND
      NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i AND NOT sram_d(8).PIN)
      OR (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/bytesel(0) AND NOT epp_I/bytesel(1) AND
      NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i AND NOT sram_d(0).PIN)));
     dd(0) <= dd_I(0) when dd_OE(0) = '1' else 'Z';
     dd_OE(0) <= (NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND
      NOT epp_I/RD_l_i AND epp_I/WR_l_i AND NOT $OpTx$$OpTx$FX_DC$187_INV$520);
dd_I(1) <= NOT (((sram_I/sample_cnt_int(16).EXP)
      OR (epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i)
      OR (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND
      NOT epp_I/adr(3) AND epp_I/bytesel(0) AND epp_I/bytesel(1) AND
      NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i AND NOT sram_d(25).PIN)
      OR (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND
      NOT epp_I/adr(3) AND epp_I/bytesel(0) AND NOT epp_I/bytesel(1) AND
      NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i AND NOT sram_d(9).PIN)
      OR (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/bytesel(0) AND NOT epp_I/bytesel(1) AND
      NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i AND NOT sram_d(1).PIN)));
     dd(1) <= dd_I(1) when dd_OE(1) = '1' else 'Z';
     dd_OE(1) <= (NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND
      NOT epp_I/RD_l_i AND epp_I/WR_l_i AND NOT $OpTx$$OpTx$FX_DC$187_INV$520);
dd_I(2) <= NOT (((sram_I/sample_cnt_int(15).EXP)
      OR (epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i)
      OR (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND
      NOT epp_I/adr(3) AND epp_I/bytesel(0) AND epp_I/bytesel(1) AND
      NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i AND NOT sram_d(26).PIN)
      OR (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND
      NOT epp_I/adr(3) AND epp_I/bytesel(0) AND NOT epp_I/bytesel(1) AND
      NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i AND NOT sram_d(10).PIN)
      OR (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/bytesel(0) AND NOT epp_I/bytesel(1) AND
      NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i AND NOT sram_d(2).PIN)));
     dd(2) <= dd_I(2) when dd_OE(2) = '1' else 'Z';
     dd_OE(2) <= (NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND
      NOT epp_I/RD_l_i AND epp_I/WR_l_i AND NOT $OpTx$$OpTx$FX_DC$187_INV$520);
dd_I(3) <= ((epp_I/adr(2))
      OR (epp_I/ALE_l_i)
      OR (epp_I/RD_l_i)
      OR (NOT epp_I/WR_l_i)
      OR (sram_I/sample_cnt_int(12).EXP)
      OR (sram_I/sample_cnt_int(11).EXP));
     dd(3) <= dd_I(3) when dd_OE(3) = '1' else 'Z';
     dd_OE(3) <= (NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND
      NOT epp_I/RD_l_i AND epp_I/WR_l_i AND NOT $OpTx$$OpTx$FX_DC$187_INV$520);
dd_I(4) <= NOT (((EXP47_.EXP)
      OR (dd_out(5).EXP)
      OR (trigcond_I/trig_cnt(0) AND epp_I/adr(1) AND
      epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT tcnt_reg(0) AND
      NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i)
      OR (NOT trigcond_I/trig_cnt(0) AND epp_I/adr(1) AND
      epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND tcnt_reg(0) AND
      NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i)
      OR (trigcond_I/trig_cnt(1) AND epp_I/adr(1) AND
      epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT tcnt_reg(1) AND
      NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i)
      OR (NOT trigcond_I/trig_cnt(1) AND epp_I/adr(1) AND
      epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND tcnt_reg(1) AND
      NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i)));
     dd(4) <= dd_I(4) when dd_OE(4) = '1' else 'Z';
     dd_OE(4) <= (NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND
      NOT epp_I/RD_l_i AND epp_I/WR_l_i AND NOT $OpTx$$OpTx$FX_DC$187_INV$520);
dd_I(5) <= NOT (((mask_reg(0).EXP)
      OR (NOT clr AND epp_I/adr(0) AND NOT epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i)
      OR (NOT epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i)
      OR (NOT epp_I/adr(1) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND
      epp_I/bytesel(0) AND NOT epp_I/bytesel(1) AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND
      epp_I/WR_l_i AND NOT sram_d(13).PIN)));
     dd(5) <= dd_I(5) when dd_OE(5) = '1' else 'Z';
     dd_OE(5) <= (NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND
      NOT epp_I/RD_l_i AND epp_I/WR_l_i AND NOT $OpTx$$OpTx$FX_DC$187_INV$520);
dd_I(6) <= NOT (((dd_out(7).EXP)
      OR (NOT epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i)
      OR (epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND
      NOT run AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i)
      OR (NOT epp_I/adr(1) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND
      epp_I/bytesel(0) AND NOT epp_I/bytesel(1) AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND
      epp_I/WR_l_i AND NOT sram_d(14).PIN)
      OR (NOT epp_I/adr(1) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND
      NOT epp_I/bytesel(0) AND NOT epp_I/bytesel(1) AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND
      epp_I/WR_l_i AND NOT sram_d(6).PIN)));
     dd(6) <= dd_I(6) when dd_OE(6) = '1' else 'Z';
     dd_OE(6) <= (NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND
      NOT epp_I/RD_l_i AND epp_I/WR_l_i AND NOT $OpTx$$OpTx$FX_DC$187_INV$520);
dd_I(7) <= NOT (((extrig_val.EXP)
      OR (epp_I/adr(0) AND NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND
      NOT done AND NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i)
      OR (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND
      NOT epp_I/adr(3) AND epp_I/bytesel(0) AND NOT epp_I/bytesel(1) AND
      NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i AND NOT sram_d(15).PIN)));
     dd(7) <= dd_I(7) when dd_OE(7) = '1' else 'Z';
     dd_OE(7) <= (NOT epp_I/adr(2) AND NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND
      NOT epp_I/RD_l_i AND epp_I/WR_l_i AND NOT $OpTx$$OpTx$FX_DC$187_INV$520);
FDCPE_done: FDCPE port map (done,done_D,clk_ob,clr,'0');
     done_D <= (state_FFd3 AND state_FFd1);
FDCPE_edge_reg0: FDCPE port map (edge_reg(0),edge_reg(1).EXP,NOT clk_in,'0','0',edge_reg_CE(0));
     edge_reg_CE(0) <= (epp_I/adr(1) AND epp_I/adr(0) AND epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_edge_reg1: FDCPE port map (edge_reg(1),dd(1).PIN,NOT clk_in,'0','0',edge_reg_CE(1));
     edge_reg_CE(1) <= (epp_I/adr(1) AND epp_I/adr(0) AND epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_edge_reg2: FDCPE port map (edge_reg(2),dd(2).PIN,NOT clk_in,'0','0',edge_reg_CE(2));
     edge_reg_CE(2) <= (epp_I/adr(1) AND epp_I/adr(0) AND epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_edge_reg3: FDCPE port map (edge_reg(3),dd(3).PIN,NOT clk_in,'0','0',edge_reg_CE(3));
     edge_reg_CE(3) <= (epp_I/adr(1) AND epp_I/adr(0) AND epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_edge_reg4: FDCPE port map (edge_reg(4),dd(4).PIN,NOT clk_in,'0','0',edge_reg_CE(4));
     edge_reg_CE(4) <= (epp_I/adr(1) AND epp_I/adr(0) AND epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_edge_reg5: FDCPE port map (edge_reg(5),dd(5).PIN,NOT clk_in,'0','0',edge_reg_CE(5));
     edge_reg_CE(5) <= (epp_I/adr(1) AND epp_I/adr(0) AND epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_edge_reg6: FDCPE port map (edge_reg(6),dd(6).PIN,NOT clk_in,'0','0',edge_reg_CE(6));
     edge_reg_CE(6) <= (epp_I/adr(1) AND epp_I/adr(0) AND epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_edge_reg7: FDCPE port map (edge_reg(7),dd(7).PIN,NOT clk_in,'0','0',edge_reg_CE(7));
     edge_reg_CE(7) <= (epp_I/adr(1) AND epp_I/adr(0) AND epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_edge_reg8: FDCPE port map (edge_reg(8),dd(0).PIN,NOT clk_in,'0','0',edge_reg_CE(8));
     edge_reg_CE(8) <= (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND
      epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_edge_reg9: FDCPE port map (edge_reg(9),dd(1).PIN,NOT clk_in,'0','0',edge_reg_CE(9));
     edge_reg_CE(9) <= (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND
      epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_edge_reg10: FDCPE port map (edge_reg(10),dd(2).PIN,NOT clk_in,'0','0',edge_reg_CE(10));
     edge_reg_CE(10) <= (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND
      epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_edge_reg11: FDCPE port map (edge_reg(11),dd(3).PIN,NOT clk_in,'0','0',edge_reg_CE(11));
     edge_reg_CE(11) <= (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND
      epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_edge_reg12: FDCPE port map (edge_reg(12),dd(4).PIN,NOT clk_in,'0','0',edge_reg_CE(12));
     edge_reg_CE(12) <= (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND
      epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_edge_reg13: FDCPE port map (edge_reg(13),dd(5).PIN,NOT clk_in,'0','0',edge_reg_CE(13));
     edge_reg_CE(13) <= (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND
      epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_edge_reg14: FDCPE port map (edge_reg(14),dd(6).PIN,NOT clk_in,'0','0',edge_reg_CE(14));
     edge_reg_CE(14) <= (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND
      epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_edge_reg15: FDCPE port map (edge_reg(15),dd(7).PIN,NOT clk_in,'0','0',edge_reg_CE(15));
     edge_reg_CE(15) <= (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND
      epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_epp_I/ALE_l_i: FDCPE port map (epp_I/ALE_l_i,dale_l,clk_in,'0','0');
FDCPE_epp_I/RD_l_i: FDCPE port map (epp_I/RD_l_i,drd_l,clk_in,'0','0');
FDCPE_epp_I/WR_l_i: FDCPE port map (epp_I/WR_l_i,dwr_l,clk_in,'0','0');
FDCPE_epp_I/adr0: FDCPE port map (epp_I/adr(0),dd(0).PIN,clk_in,'0','0',epp_I/adr_CE(0));
     epp_I/adr_CE(0) <= (epp_I/ALE_l_i AND epp_I/RD_l_i AND epp_I/WR_l_i);
FDCPE_epp_I/adr1: FDCPE port map (epp_I/adr(1),dd(1).PIN,clk_in,'0','0',epp_I/adr_CE(1));
     epp_I/adr_CE(1) <= (epp_I/ALE_l_i AND epp_I/RD_l_i AND epp_I/WR_l_i);
FDCPE_epp_I/adr2: FDCPE port map (epp_I/adr(2),dd(2).PIN,clk_in,'0','0',epp_I/adr_CE(2));
     epp_I/adr_CE(2) <= (epp_I/ALE_l_i AND epp_I/RD_l_i AND epp_I/WR_l_i);
FDCPE_epp_I/adr3: FDCPE port map (epp_I/adr(3),dd(3).PIN,clk_in,'0','0',epp_I/adr_CE(3));
     epp_I/adr_CE(3) <= (epp_I/ALE_l_i AND epp_I/RD_l_i AND epp_I/WR_l_i);
FDCPE_epp_I/auto_inc: FDCPE port map (epp_I/auto_inc,dd(4).PIN,clk_in,'0','0',epp_I/auto_inc_CE);
     epp_I/auto_inc_CE <= (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FTCPE_epp_I/bytesel0: FTCPE port map (epp_I/bytesel(0),epp_I/bytesel_T(0),clk_in,'0','0');
     epp_I/bytesel_T(0) <= ((epp_I/bytesel(1).EXP)
      OR (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND
      NOT epp_I/adr(3) AND epp_I/ALE_l_i AND epp_I/d_rd_i_d));
FTCPE_epp_I/bytesel1: FTCPE port map (epp_I/bytesel(1),epp_I/bytesel_T(1),clk_in,'0','0');
     epp_I/bytesel_T(1) <= ((edge_reg(0).EXP)
      OR (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND
      NOT epp_I/adr(3) AND epp_I/bytesel(0) AND epp_I/ALE_l_i AND
      epp_I/d_rd_i_d));
FDCPE_epp_I/d_rd_i_d: FDCPE port map (epp_I/d_rd_i_d,epp_I/d_rd_i_d_D,clk_in,'0','0');
     epp_I/d_rd_i_d_D <= (NOT epp_I/ALE_l_i AND NOT epp_I/RD_l_i AND epp_I/WR_l_i);
FDCPE_extrig_en: FDCPE port map (extrig_en,dd(1).PIN,NOT clk_in,'0','0',extrig_en_CE);
     extrig_en_CE <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND epp_I/adr(2) AND
      epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_extrig_val: FDCPE port map (extrig_val,dd(0).PIN,NOT clk_in,'0','0',extrig_val_CE);
     extrig_val_CE <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND epp_I/adr(2) AND
      epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_inv_trig: FDCPE port map (inv_trig,dd(7).PIN,NOT clk_in,'0','0',inv_trig_CE);
     inv_trig_CE <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND epp_I/adr(2) AND
      epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_mask_reg0: FDCPE port map (mask_reg(0),dd(0).PIN,NOT clk_in,'0','0',mask_reg_CE(0));
     mask_reg_CE(0) <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND
      epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_mask_reg1: FDCPE port map (mask_reg(1),dd(1).PIN,NOT clk_in,'0','0',mask_reg_CE(1));
     mask_reg_CE(1) <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND
      epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_mask_reg2: FDCPE port map (mask_reg(2),dd(2).PIN,NOT clk_in,'0','0',mask_reg_CE(2));
     mask_reg_CE(2) <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND
      epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_mask_reg3: FDCPE port map (mask_reg(3),dd(3).PIN,NOT clk_in,'0','0',mask_reg_CE(3));
     mask_reg_CE(3) <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND
      epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_mask_reg4: FDCPE port map (mask_reg(4),dd(4).PIN,NOT clk_in,'0','0',mask_reg_CE(4));
     mask_reg_CE(4) <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND
      epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_mask_reg5: FDCPE port map (mask_reg(5),dd(5).PIN,NOT clk_in,'0','0',mask_reg_CE(5));
     mask_reg_CE(5) <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND
      epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_mask_reg6: FDCPE port map (mask_reg(6),dd(6).PIN,NOT clk_in,'0','0',mask_reg_CE(6));
     mask_reg_CE(6) <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND
      epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_mask_reg7: FDCPE port map (mask_reg(7),dd(7).PIN,NOT clk_in,'0','0',mask_reg_CE(7));
     mask_reg_CE(7) <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND
      epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_mask_reg8: FDCPE port map (mask_reg(8),dd(0).PIN,NOT clk_in,'0','0',mask_reg_CE(8));
     mask_reg_CE(8) <= (epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND
      epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_mask_reg9: FDCPE port map (mask_reg(9),dd(1).PIN,NOT clk_in,'0','0',mask_reg_CE(9));
     mask_reg_CE(9) <= (epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND
      epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_mask_reg10: FDCPE port map (mask_reg(10),dd(2).PIN,NOT clk_in,'0','0',mask_reg_CE(10));
     mask_reg_CE(10) <= (epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND
      epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_mask_reg11: FDCPE port map (mask_reg(11),dd(3).PIN,NOT clk_in,'0','0',mask_reg_CE(11));
     mask_reg_CE(11) <= (epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND
      epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_mask_reg12: FDCPE port map (mask_reg(12),dd(4).PIN,NOT clk_in,'0','0',mask_reg_CE(12));
     mask_reg_CE(12) <= (epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND
      epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_mask_reg13: FDCPE port map (mask_reg(13),dd(5).PIN,NOT clk_in,'0','0',mask_reg_CE(13));
     mask_reg_CE(13) <= (epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND
      epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_mask_reg14: FDCPE port map (mask_reg(14),dd(6).PIN,NOT clk_in,'0','0',mask_reg_CE(14));
     mask_reg_CE(14) <= (epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND
      epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_mask_reg15: FDCPE port map (mask_reg(15),dd(7).PIN,NOT clk_in,'0','0',mask_reg_CE(15));
     mask_reg_CE(15) <= (epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND
      epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_pretrig_off: FDCPE port map (pretrig_off,dd(4).PIN,NOT clk_in,'0','0',pretrig_off_CE);
     pretrig_off_CE <= (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_psize_reg0: FDCPE port map (psize_reg(0),dd(0).PIN,NOT clk_in,'0','0',psize_reg_CE(0));
     psize_reg_CE(0) <= (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_psize_reg1: FDCPE port map (psize_reg(1),dd(1).PIN,NOT clk_in,'0','0',psize_reg_CE(1));
     psize_reg_CE(1) <= (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_psize_reg2: FDCPE port map (psize_reg(2),dd(2).PIN,NOT clk_in,'0','0',psize_reg_CE(2));
     psize_reg_CE(2) <= (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_psize_reg3: FDCPE port map (psize_reg(3),dd(3).PIN,NOT clk_in,'0','0',psize_reg_CE(3));
     psize_reg_CE(3) <= (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_run: FDCPE port map (run,dd(7).PIN,clk_in,'0','0',run_CE);
     run_CE <= (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_sample_cnt_en: FDCPE port map (sample_cnt_en,state_FFd2,clk_ob,clr,'0');
FDCPE_sample_cnt_wm: FDCPE port map (sample_cnt_wm,sample_cnt_wm_D,clk_ob,'0','0');
     sample_cnt_wm_D <= ((sram_I/sample_cnt_int(8).EXP)
      OR (EXP54_.EXP)
      OR (sram_I/sample_cnt_int(0) AND
      sram_I/sample_cnt_int(11) AND NOT sram_I/sample_cnt_int(1) AND
      sram_I/sample_cnt_int(10) AND sram_I/sample_cnt_int(12) AND
      sram_I/sample_cnt_int(13) AND sram_I/sample_cnt_int(14) AND
      sram_I/sample_cnt_int(15) AND sram_I/sample_cnt_int(2) AND
      sram_I/sample_cnt_int(3) AND sram_I/sample_cnt_int(4) AND
      sram_I/sample_cnt_int(5) AND sram_I/sample_cnt_int(6) AND
      sram_I/sample_cnt_int(7) AND sram_I/sample_cnt_int(8) AND
      sram_I/sample_cnt_int(9) AND sram_I/sample_cnt_int(16) AND psize_reg(0) AND
      psize_reg(1) AND psize_reg(2) AND psize_reg(3))
      OR (sram_I/sample_cnt_int(0) AND
      sram_I/sample_cnt_int(11) AND NOT sram_I/sample_cnt_int(1) AND
      sram_I/sample_cnt_int(10) AND sram_I/sample_cnt_int(12) AND
      sram_I/sample_cnt_int(13) AND sram_I/sample_cnt_int(14) AND
      sram_I/sample_cnt_int(15) AND sram_I/sample_cnt_int(2) AND
      sram_I/sample_cnt_int(3) AND sram_I/sample_cnt_int(4) AND
      sram_I/sample_cnt_int(5) AND sram_I/sample_cnt_int(6) AND
      sram_I/sample_cnt_int(7) AND sram_I/sample_cnt_int(8) AND
      sram_I/sample_cnt_int(9) AND NOT sram_I/sample_cnt_int(16) AND psize_reg(0) AND
      psize_reg(1) AND psize_reg(2) AND NOT psize_reg(3))
      OR (sram_I/sample_cnt_int(0) AND
      sram_I/sample_cnt_int(11) AND NOT sram_I/sample_cnt_int(1) AND
      sram_I/sample_cnt_int(10) AND sram_I/sample_cnt_int(12) AND
      sram_I/sample_cnt_int(13) AND NOT sram_I/sample_cnt_int(14) AND
      sram_I/sample_cnt_int(15) AND sram_I/sample_cnt_int(2) AND
      sram_I/sample_cnt_int(3) AND sram_I/sample_cnt_int(4) AND
      sram_I/sample_cnt_int(5) AND sram_I/sample_cnt_int(6) AND
      sram_I/sample_cnt_int(7) AND sram_I/sample_cnt_int(8) AND
      sram_I/sample_cnt_int(9) AND sram_I/sample_cnt_int(16) AND psize_reg(0) AND
      NOT psize_reg(1) AND psize_reg(2) AND psize_reg(3))
      OR (sram_I/sample_cnt_int(0) AND
      sram_I/sample_cnt_int(11) AND NOT sram_I/sample_cnt_int(1) AND
      sram_I/sample_cnt_int(10) AND sram_I/sample_cnt_int(12) AND
      NOT sram_I/sample_cnt_int(13) AND sram_I/sample_cnt_int(14) AND
      sram_I/sample_cnt_int(15) AND sram_I/sample_cnt_int(2) AND
      sram_I/sample_cnt_int(3) AND sram_I/sample_cnt_int(4) AND
      sram_I/sample_cnt_int(5) AND sram_I/sample_cnt_int(6) AND
      sram_I/sample_cnt_int(7) AND sram_I/sample_cnt_int(8) AND
      sram_I/sample_cnt_int(9) AND sram_I/sample_cnt_int(16) AND NOT psize_reg(0) AND
      psize_reg(1) AND psize_reg(2) AND psize_reg(3))
      OR (sram_I/sample_cnt_int(0) AND
      sram_I/sample_cnt_int(11) AND NOT sram_I/sample_cnt_int(1) AND
      sram_I/sample_cnt_int(10) AND sram_I/sample_cnt_int(12) AND
      NOT sram_I/sample_cnt_int(13) AND sram_I/sample_cnt_int(14) AND
      sram_I/sample_cnt_int(15) AND sram_I/sample_cnt_int(2) AND
      sram_I/sample_cnt_int(3) AND sram_I/sample_cnt_int(4) AND
      sram_I/sample_cnt_int(5) AND sram_I/sample_cnt_int(6) AND
      sram_I/sample_cnt_int(7) AND sram_I/sample_cnt_int(8) AND
      sram_I/sample_cnt_int(9) AND NOT sram_I/sample_cnt_int(16) AND NOT psize_reg(0) AND
      psize_reg(1) AND psize_reg(2) AND NOT psize_reg(3)));
FTCPE_sram_I/sample_cnt_int0: FTCPE port map (sram_I/sample_cnt_int(0),sram_I/sample_cnt_int_T(0),clk_ob,clr,'0');
     sram_I/sample_cnt_int_T(0) <= ((NOT sample_cnt_en)
      OR (NOT sram_I/sample_cnt_int(0) AND
      sram_I/sample_cnt_int(11) AND sram_I/sample_cnt_int(1) AND
      sram_I/sample_cnt_int(10) AND sram_I/sample_cnt_int(12) AND
      sram_I/sample_cnt_int(13) AND sram_I/sample_cnt_int(14) AND
      sram_I/sample_cnt_int(15) AND NOT sram_I/sample_cnt_int(2) AND
      sram_I/sample_cnt_int(3) AND sram_I/sample_cnt_int(4) AND
      sram_I/sample_cnt_int(5) AND sram_I/sample_cnt_int(6) AND
      sram_I/sample_cnt_int(7) AND sram_I/sample_cnt_int(8) AND
      sram_I/sample_cnt_int(9) AND sram_I/sample_cnt_int(16)));
FTCPE_sram_I/sample_cnt_int1: FTCPE port map (sram_I/sample_cnt_int(1),sram_I/sample_cnt_int_T(1),clk_ob,clr,'0');
     sram_I/sample_cnt_int_T(1) <= (sram_I/sample_cnt_int(0) AND sample_cnt_en);
FTCPE_sram_I/sample_cnt_int2: FTCPE port map (sram_I/sample_cnt_int(2),sram_I/sample_cnt_int_T(2),clk_ob,clr,'0');
     sram_I/sample_cnt_int_T(2) <= (sram_I/sample_cnt_int(0) AND
      sram_I/sample_cnt_int(1) AND sample_cnt_en);
FTCPE_sram_I/sample_cnt_int3: FTCPE port map (sram_I/sample_cnt_int(3),sram_I/sample_cnt_int_T(3),clk_ob,clr,'0');
     sram_I/sample_cnt_int_T(3) <= (sram_I/sample_cnt_int(0) AND
      sram_I/sample_cnt_int(1) AND sram_I/sample_cnt_int(2) AND sample_cnt_en);
FTCPE_sram_I/sample_cnt_int4: FTCPE port map (sram_I/sample_cnt_int(4),sram_I/sample_cnt_int_T(4),clk_ob,clr,'0');
     sram_I/sample_cnt_int_T(4) <= (sram_I/sample_cnt_int(0) AND
      sram_I/sample_cnt_int(1) AND sram_I/sample_cnt_int(2) AND
      sram_I/sample_cnt_int(3) AND sample_cnt_en);
FTCPE_sram_I/sample_cnt_int5: FTCPE port map (sram_I/sample_cnt_int(5),sram_I/sample_cnt_int_T(5),clk_ob,clr,'0');
     sram_I/sample_cnt_int_T(5) <= (sram_I/sample_cnt_int(0) AND
      sram_I/sample_cnt_int(1) AND sram_I/sample_cnt_int(2) AND
      sram_I/sample_cnt_int(3) AND sram_I/sample_cnt_int(4) AND sample_cnt_en);
FTCPE_sram_I/sample_cnt_int6: FTCPE port map (sram_I/sample_cnt_int(6),sram_I/sample_cnt_int_T(6),clk_ob,clr,'0');
     sram_I/sample_cnt_int_T(6) <= (sram_I/sample_cnt_int(0) AND
      sram_I/sample_cnt_int(1) AND sram_I/sample_cnt_int(2) AND
      sram_I/sample_cnt_int(3) AND sram_I/sample_cnt_int(4) AND
      sram_I/sample_cnt_int(5) AND sample_cnt_en);
FTCPE_sram_I/sample_cnt_int7: FTCPE port map (sram_I/sample_cnt_int(7),sram_I/sample_cnt_int_T(7),clk_ob,clr,'0');
     sram_I/sample_cnt_int_T(7) <= (sram_I/sample_cnt_int(0) AND
      sram_I/sample_cnt_int(1) AND sram_I/sample_cnt_int(2) AND
      sram_I/sample_cnt_int(3) AND sram_I/sample_cnt_int(4) AND
      sram_I/sample_cnt_int(5) AND sram_I/sample_cnt_int(6) AND sample_cnt_en);
FTCPE_sram_I/sample_cnt_int8: FTCPE port map (sram_I/sample_cnt_int(8),sram_I/sample_cnt_int_T(8),clk_ob,clr,'0');
     sram_I/sample_cnt_int_T(8) <= (sram_I/sample_cnt_int(0) AND
      sram_I/sample_cnt_int(1) AND sram_I/sample_cnt_int(2) AND
      sram_I/sample_cnt_int(3) AND sram_I/sample_cnt_int(4) AND
      sram_I/sample_cnt_int(5) AND sram_I/sample_cnt_int(6) AND
      sram_I/sample_cnt_int(7) AND sample_cnt_en);
FTCPE_sram_I/sample_cnt_int9: FTCPE port map (sram_I/sample_cnt_int(9),sram_I/sample_cnt_int_T(9),clk_ob,clr,'0');
     sram_I/sample_cnt_int_T(9) <= (sram_I/sample_cnt_int(0) AND
      sram_I/sample_cnt_int(1) AND sram_I/sample_cnt_int(2) AND
      sram_I/sample_cnt_int(3) AND sram_I/sample_cnt_int(4) AND
      sram_I/sample_cnt_int(5) AND sram_I/sample_cnt_int(6) AND
      sram_I/sample_cnt_int(7) AND sram_I/sample_cnt_int(8) AND sample_cnt_en);
FTCPE_sram_I/sample_cnt_int10: FTCPE port map (sram_I/sample_cnt_int(10),sram_I/sample_cnt_int_T(10),clk_ob,clr,'0');
     sram_I/sample_cnt_int_T(10) <= (sram_I/sample_cnt_int(0) AND
      sram_I/sample_cnt_int(1) AND sram_I/sample_cnt_int(2) AND
      sram_I/sample_cnt_int(3) AND sram_I/sample_cnt_int(4) AND
      sram_I/sample_cnt_int(5) AND sram_I/sample_cnt_int(6) AND
      sram_I/sample_cnt_int(7) AND sram_I/sample_cnt_int(8) AND
      sram_I/sample_cnt_int(9) AND sample_cnt_en);
FTCPE_sram_I/sample_cnt_int11: FTCPE port map (sram_I/sample_cnt_int(11),sram_I/sample_cnt_int(10).EXP,clk_ob,clr,'0');
FTCPE_sram_I/sample_cnt_int12: FTCPE port map (sram_I/sample_cnt_int(12),sram_I/sample_cnt_int_T(12),clk_ob,clr,'0');
     sram_I/sample_cnt_int_T(12) <= (sram_I/sample_cnt_int(0) AND
      sram_I/sample_cnt_int(11) AND sram_I/sample_cnt_int(1) AND
      sram_I/sample_cnt_int(10) AND sram_I/sample_cnt_int(2) AND
      sram_I/sample_cnt_int(3) AND sram_I/sample_cnt_int(4) AND
      sram_I/sample_cnt_int(5) AND sram_I/sample_cnt_int(6) AND
      sram_I/sample_cnt_int(7) AND sram_I/sample_cnt_int(8) AND
      sram_I/sample_cnt_int(9) AND sample_cnt_en);
FTCPE_sram_I/sample_cnt_int13: FTCPE port map (sram_I/sample_cnt_int(13),sram_I/sample_cnt_int_T(13),clk_ob,clr,'0');
     sram_I/sample_cnt_int_T(13) <= (sram_I/sample_cnt_int(0) AND
      sram_I/sample_cnt_int(11) AND sram_I/sample_cnt_int(1) AND
      sram_I/sample_cnt_int(10) AND sram_I/sample_cnt_int(12) AND
      sram_I/sample_cnt_int(2) AND sram_I/sample_cnt_int(3) AND
      sram_I/sample_cnt_int(4) AND sram_I/sample_cnt_int(5) AND
      sram_I/sample_cnt_int(6) AND sram_I/sample_cnt_int(7) AND
      sram_I/sample_cnt_int(8) AND sram_I/sample_cnt_int(9) AND sample_cnt_en);
FTCPE_sram_I/sample_cnt_int14: FTCPE port map (sram_I/sample_cnt_int(14),sram_I/sample_cnt_int_T(14),clk_ob,clr,'0');
     sram_I/sample_cnt_int_T(14) <= (sram_I/sample_cnt_int(0) AND
      sram_I/sample_cnt_int(11) AND sram_I/sample_cnt_int(1) AND
      sram_I/sample_cnt_int(10) AND sram_I/sample_cnt_int(12) AND
      sram_I/sample_cnt_int(13) AND sram_I/sample_cnt_int(2) AND
      sram_I/sample_cnt_int(3) AND sram_I/sample_cnt_int(4) AND
      sram_I/sample_cnt_int(5) AND sram_I/sample_cnt_int(6) AND
      sram_I/sample_cnt_int(7) AND sram_I/sample_cnt_int(8) AND
      sram_I/sample_cnt_int(9) AND sample_cnt_en);
FTCPE_sram_I/sample_cnt_int15: FTCPE port map (sram_I/sample_cnt_int(15),sram_I/sample_cnt_int_T(15),clk_ob,clr,'0');
     sram_I/sample_cnt_int_T(15) <= (sram_I/sample_cnt_int(0) AND
      sram_I/sample_cnt_int(11) AND sram_I/sample_cnt_int(1) AND
      sram_I/sample_cnt_int(10) AND sram_I/sample_cnt_int(12) AND
      sram_I/sample_cnt_int(13) AND sram_I/sample_cnt_int(14) AND
      sram_I/sample_cnt_int(2) AND sram_I/sample_cnt_int(3) AND
      sram_I/sample_cnt_int(4) AND sram_I/sample_cnt_int(5) AND
      sram_I/sample_cnt_int(6) AND sram_I/sample_cnt_int(7) AND
      sram_I/sample_cnt_int(8) AND sram_I/sample_cnt_int(9) AND sample_cnt_en);
FTCPE_sram_I/sample_cnt_int16: FTCPE port map (sram_I/sample_cnt_int(16),sram_I/sample_cnt_int_T(16),clk_ob,clr,'0');
     sram_I/sample_cnt_int_T(16) <= (sram_I/sample_cnt_int(0) AND
      sram_I/sample_cnt_int(11) AND sram_I/sample_cnt_int(1) AND
      sram_I/sample_cnt_int(10) AND sram_I/sample_cnt_int(12) AND
      sram_I/sample_cnt_int(13) AND sram_I/sample_cnt_int(14) AND
      sram_I/sample_cnt_int(15) AND sram_I/sample_cnt_int(2) AND
      sram_I/sample_cnt_int(3) AND sram_I/sample_cnt_int(4) AND
      sram_I/sample_cnt_int(5) AND sram_I/sample_cnt_int(6) AND
      sram_I/sample_cnt_int(7) AND sram_I/sample_cnt_int(8) AND
      sram_I/sample_cnt_int(9) AND sample_cnt_en);
FTCPE_sram_adr0: FTCPE port map (sram_adr(0),'1',clk_ob,'0','0',adr_cnt_en);
FTCPE_sram_adr1: FTCPE port map (sram_adr(1),sram_adr(0),clk_ob,'0','0',adr_cnt_en);
FTCPE_sram_adr2: FTCPE port map (sram_adr(2),sram_adr_T(2),clk_ob,'0','0',adr_cnt_en);
     sram_adr_T(2) <= (sram_adr(0) AND sram_adr(1));
FTCPE_sram_adr3: FTCPE port map (sram_adr(3),sram_adr_T(3),clk_ob,'0','0',adr_cnt_en);
     sram_adr_T(3) <= (sram_adr(0) AND sram_adr(1) AND sram_adr(2));
FTCPE_sram_adr4: FTCPE port map (sram_adr(4),sram_adr_T(4),clk_ob,'0','0',adr_cnt_en);
     sram_adr_T(4) <= (sram_adr(0) AND sram_adr(1) AND sram_adr(2) AND
      sram_adr(3));
FTCPE_sram_adr5: FTCPE port map (sram_adr(5),sram_adr_T(5),clk_ob,'0','0',adr_cnt_en);
     sram_adr_T(5) <= (sram_adr(0) AND sram_adr(1) AND sram_adr(2) AND
      sram_adr(3) AND sram_adr(4));
FTCPE_sram_adr6: FTCPE port map (sram_adr(6),sram_adr_T(6),clk_ob,'0','0',adr_cnt_en);
     sram_adr_T(6) <= (sram_adr(0) AND sram_adr(1) AND sram_adr(2) AND
      sram_adr(3) AND sram_adr(4) AND sram_adr(5));
FTCPE_sram_adr7: FTCPE port map (sram_adr(7),sram_adr_T(7),clk_ob,'0','0',adr_cnt_en);
     sram_adr_T(7) <= (sram_adr(0) AND sram_adr(1) AND sram_adr(2) AND
      sram_adr(3) AND sram_adr(4) AND sram_adr(5) AND sram_adr(6));
FTCPE_sram_adr8: FTCPE port map (sram_adr(8),sram_adr_T(8),clk_ob,'0','0',adr_cnt_en);
     sram_adr_T(8) <= (sram_adr(0) AND sram_adr(1) AND sram_adr(2) AND
      sram_adr(3) AND sram_adr(4) AND sram_adr(5) AND sram_adr(6) AND
      sram_adr(7));
FTCPE_sram_adr9: FTCPE port map (sram_adr(9),sram_adr_T(9),clk_ob,'0','0',adr_cnt_en);
     sram_adr_T(9) <= (sram_adr(0) AND sram_adr(1) AND sram_adr(2) AND
      sram_adr(3) AND sram_adr(4) AND sram_adr(5) AND sram_adr(6) AND
      sram_adr(7) AND sram_adr(8));
FTCPE_sram_adr10: FTCPE port map (sram_adr(10),sram_adr_T(10),clk_ob,'0','0',adr_cnt_en);
     sram_adr_T(10) <= (sram_adr(0) AND sram_adr(1) AND sram_adr(2) AND
      sram_adr(3) AND sram_adr(4) AND sram_adr(5) AND sram_adr(6) AND
      sram_adr(7) AND sram_adr(8) AND sram_adr(9));
FTCPE_sram_adr11: FTCPE port map (sram_adr(11),sram_adr_T(11),clk_ob,'0','0',adr_cnt_en);
     sram_adr_T(11) <= (sram_adr(0) AND sram_adr(10) AND sram_adr(1) AND
      sram_adr(2) AND sram_adr(3) AND sram_adr(4) AND sram_adr(5) AND
      sram_adr(6) AND sram_adr(7) AND sram_adr(8) AND sram_adr(9));
FTCPE_sram_adr12: FTCPE port map (sram_adr(12),sram_adr_T(12),clk_ob,'0','0',adr_cnt_en);
     sram_adr_T(12) <= (sram_adr(0) AND sram_adr(10) AND sram_adr(11) AND
      sram_adr(1) AND sram_adr(2) AND sram_adr(3) AND sram_adr(4) AND
      sram_adr(5) AND sram_adr(6) AND sram_adr(7) AND sram_adr(8) AND
      sram_adr(9));
FTCPE_sram_adr13: FTCPE port map (sram_adr(13),sram_adr_T(13),clk_ob,'0','0',adr_cnt_en);
     sram_adr_T(13) <= (sram_adr(0) AND sram_adr(10) AND sram_adr(11) AND
      sram_adr(12) AND sram_adr(1) AND sram_adr(2) AND sram_adr(3) AND
      sram_adr(4) AND sram_adr(5) AND sram_adr(6) AND sram_adr(7) AND
      sram_adr(8) AND sram_adr(9));
FTCPE_sram_adr14: FTCPE port map (sram_adr(14),sram_adr_T(14),clk_ob,'0','0',adr_cnt_en);
     sram_adr_T(14) <= (sram_adr(0) AND sram_adr(10) AND sram_adr(11) AND
      sram_adr(12) AND sram_adr(13) AND sram_adr(1) AND sram_adr(2) AND
      sram_adr(3) AND sram_adr(4) AND sram_adr(5) AND sram_adr(6) AND
      sram_adr(7) AND sram_adr(8) AND sram_adr(9));
FTCPE_sram_adr15: FTCPE port map (sram_adr(15),sram_adr_T(15),clk_ob,'0','0',adr_cnt_en);
     sram_adr_T(15) <= (sram_adr(0) AND sram_adr(10) AND sram_adr(11) AND
      sram_adr(12) AND sram_adr(13) AND sram_adr(14) AND sram_adr(1) AND
      sram_adr(2) AND sram_adr(3) AND sram_adr(4) AND sram_adr(5) AND
      sram_adr(6) AND sram_adr(7) AND sram_adr(8) AND sram_adr(9));
FTCPE_sram_adr16: FTCPE port map (sram_adr(16),sram_adr_T(16),clk_ob,'0','0',adr_cnt_en);
     sram_adr_T(16) <= (sram_adr(0) AND sram_adr(10) AND sram_adr(11) AND
      sram_adr(12) AND sram_adr(13) AND sram_adr(14) AND sram_adr(15) AND
      sram_adr(1) AND sram_adr(2) AND sram_adr(3) AND sram_adr(4) AND
      sram_adr(5) AND sram_adr(6) AND sram_adr(7) AND sram_adr(8) AND
      sram_adr(9));
sram_adsc_l <= sram_oe_l_OBUF$BUF0.EXP;
sram_ce_l <= timebase_I/clk_cnt(8).EXP;
sram_clk <= ((EXP58_.EXP)
      OR (EXP59_.EXP)
      OR (timebase_I/clk_2 AND NOT tsel_reg(2) AND tsel_reg(3) AND
      NOT clk_falling_edge AND NOT timebase_I/sw_read_clk_f AND
      NOT timebase_I/sw_read_clk_r)
      OR (timebase_I/clk_2 AND NOT tsel_reg(4) AND tsel_reg(0) AND
      NOT clk_falling_edge AND NOT timebase_I/sw_read_clk_f AND
      NOT timebase_I/sw_read_clk_r)
      OR (NOT timebase_I/clk_2 AND NOT tsel_reg(2) AND tsel_reg(3) AND
      clk_falling_edge AND NOT timebase_I/sw_read_clk_f AND
      NOT timebase_I/sw_read_clk_r)
      OR (NOT timebase_I/clk_2 AND NOT tsel_reg(4) AND tsel_reg(0) AND
      clk_falling_edge AND NOT timebase_I/sw_read_clk_f AND
      NOT timebase_I/sw_read_clk_r)
      OR (tsel_reg(1) AND tsel_reg(2) AND tsel_reg(3) AND
      tsel_reg(4) AND NOT tsel_reg(0) AND clk_falling_edge AND
      NOT timebase_I/sw_read_clk_f AND NOT timebase_I/sw_read_clk_r AND NOT eclk));
FDCPE_sram_d0: FDCPE port map (sram_d_I(0),channel(0),clk_ob,'0','0');
     sram_d(0) <= sram_d_I(0) when sram_d_OE(0) = '1' else 'Z';
     sram_d_OE(0) <= st(3);
FDCPE_sram_d1: FDCPE port map (sram_d_I(1),channel(1),clk_ob,'0','0');
     sram_d(1) <= sram_d_I(1) when sram_d_OE(1) = '1' else 'Z';
     sram_d_OE(1) <= st(3);
FDCPE_sram_d2: FDCPE port map (sram_d_I(2),channel(2),clk_ob,'0','0');
     sram_d(2) <= sram_d_I(2) when sram_d_OE(2) = '1' else 'Z';
     sram_d_OE(2) <= st(3);
FDCPE_sram_d3: FDCPE port map (sram_d_I(3),channel(3),clk_ob,'0','0');
     sram_d(3) <= sram_d_I(3) when sram_d_OE(3) = '1' else 'Z';
     sram_d_OE(3) <= st(3);
FDCPE_sram_d4: FDCPE port map (sram_d_I(4),channel(4),clk_ob,'0','0');
     sram_d(4) <= sram_d_I(4) when sram_d_OE(4) = '1' else 'Z';
     sram_d_OE(4) <= st(3);
FDCPE_sram_d5: FDCPE port map (sram_d_I(5),channel(5),clk_ob,'0','0');
     sram_d(5) <= sram_d_I(5) when sram_d_OE(5) = '1' else 'Z';
     sram_d_OE(5) <= st(3);
FDCPE_sram_d6: FDCPE port map (sram_d_I(6),channel(6),clk_ob,'0','0');
     sram_d(6) <= sram_d_I(6) when sram_d_OE(6) = '1' else 'Z';
     sram_d_OE(6) <= st(3);
FDCPE_sram_d7: FDCPE port map (sram_d_I(7),channel(7),clk_ob,'0','0');
     sram_d(7) <= sram_d_I(7) when sram_d_OE(7) = '1' else 'Z';
     sram_d_OE(7) <= st(3);
FDCPE_sram_d8: FDCPE port map (sram_d_I(8),channel(8),clk_ob,'0','0');
     sram_d(8) <= sram_d_I(8) when sram_d_OE(8) = '1' else 'Z';
     sram_d_OE(8) <= st(3);
FDCPE_sram_d9: FDCPE port map (sram_d_I(9),channel(9),clk_ob,'0','0');
     sram_d(9) <= sram_d_I(9) when sram_d_OE(9) = '1' else 'Z';
     sram_d_OE(9) <= st(3);
FDCPE_sram_d10: FDCPE port map (sram_d_I(10),channel(10),clk_ob,'0','0');
     sram_d(10) <= sram_d_I(10) when sram_d_OE(10) = '1' else 'Z';
     sram_d_OE(10) <= st(3);
FDCPE_sram_d11: FDCPE port map (sram_d_I(11),channel(11),clk_ob,'0','0');
     sram_d(11) <= sram_d_I(11) when sram_d_OE(11) = '1' else 'Z';
     sram_d_OE(11) <= st(3);
FDCPE_sram_d12: FDCPE port map (sram_d_I(12),channel(12),clk_ob,'0','0');
     sram_d(12) <= sram_d_I(12) when sram_d_OE(12) = '1' else 'Z';
     sram_d_OE(12) <= st(3);
FDCPE_sram_d13: FDCPE port map (sram_d_I(13),channel(13),clk_ob,'0','0');
     sram_d(13) <= sram_d_I(13) when sram_d_OE(13) = '1' else 'Z';
     sram_d_OE(13) <= st(3);
FDCPE_sram_d14: FDCPE port map (sram_d_I(14),channel(14),clk_ob,'0','0');
     sram_d(14) <= sram_d_I(14) when sram_d_OE(14) = '1' else 'Z';
     sram_d_OE(14) <= st(3);
FDCPE_sram_d15: FDCPE port map (sram_d_I(15),channel(15),clk_ob,'0','0');
     sram_d(15) <= sram_d_I(15) when sram_d_OE(15) = '1' else 'Z';
     sram_d_OE(15) <= st(3);
FDCPE_sram_d16: FDCPE port map (sram_d_I(16),channel(16),clk_ob,'0','0');
     sram_d(16) <= sram_d_I(16) when sram_d_OE(16) = '1' else 'Z';
     sram_d_OE(16) <= st(3);
FDCPE_sram_d17: FDCPE port map (sram_d_I(17),channel(17),clk_ob,'0','0');
     sram_d(17) <= sram_d_I(17) when sram_d_OE(17) = '1' else 'Z';
     sram_d_OE(17) <= st(3);
FDCPE_sram_d18: FDCPE port map (sram_d_I(18),channel(18),clk_ob,'0','0');
     sram_d(18) <= sram_d_I(18) when sram_d_OE(18) = '1' else 'Z';
     sram_d_OE(18) <= st(3);
FDCPE_sram_d19: FDCPE port map (sram_d_I(19),channel(19),clk_ob,'0','0');
     sram_d(19) <= sram_d_I(19) when sram_d_OE(19) = '1' else 'Z';
     sram_d_OE(19) <= st(3);
FDCPE_sram_d20: FDCPE port map (sram_d_I(20),channel(20),clk_ob,'0','0');
     sram_d(20) <= sram_d_I(20) when sram_d_OE(20) = '1' else 'Z';
     sram_d_OE(20) <= st(3);
FDCPE_sram_d21: FDCPE port map (sram_d_I(21),channel(21),clk_ob,'0','0');
     sram_d(21) <= sram_d_I(21) when sram_d_OE(21) = '1' else 'Z';
     sram_d_OE(21) <= st(3);
FDCPE_sram_d22: FDCPE port map (sram_d_I(22),channel(22),clk_ob,'0','0');
     sram_d(22) <= sram_d_I(22) when sram_d_OE(22) = '1' else 'Z';
     sram_d_OE(22) <= st(3);
FDCPE_sram_d23: FDCPE port map (sram_d_I(23),channel(23),clk_ob,'0','0');
     sram_d(23) <= sram_d_I(23) when sram_d_OE(23) = '1' else 'Z';
     sram_d_OE(23) <= st(3);
FDCPE_sram_d24: FDCPE port map (sram_d_I(24),channel(24),clk_ob,'0','0');
     sram_d(24) <= sram_d_I(24) when sram_d_OE(24) = '1' else 'Z';
     sram_d_OE(24) <= st(3);
FDCPE_sram_d25: FDCPE port map (sram_d_I(25),channel(25),clk_ob,'0','0');
     sram_d(25) <= sram_d_I(25) when sram_d_OE(25) = '1' else 'Z';
     sram_d_OE(25) <= st(3);
FDCPE_sram_d26: FDCPE port map (sram_d_I(26),channel(26),clk_ob,'0','0');
     sram_d(26) <= sram_d_I(26) when sram_d_OE(26) = '1' else 'Z';
     sram_d_OE(26) <= st(3);
FDCPE_sram_d27: FDCPE port map (sram_d_I(27),channel(27),clk_ob,'0','0');
     sram_d(27) <= sram_d_I(27) when sram_d_OE(27) = '1' else 'Z';
     sram_d_OE(27) <= st(3);
FDCPE_sram_d28: FDCPE port map (sram_d_I(28),channel(28),clk_ob,'0','0');
     sram_d(28) <= sram_d_I(28) when sram_d_OE(28) = '1' else 'Z';
     sram_d_OE(28) <= st(3);
FDCPE_sram_d29: FDCPE port map (sram_d_I(29),channel(29),clk_ob,'0','0');
     sram_d(29) <= sram_d_I(29) when sram_d_OE(29) = '1' else 'Z';
     sram_d_OE(29) <= st(3);
FDCPE_sram_d30: FDCPE port map (sram_d_I(30),channel(30),clk_ob,'0','0');
     sram_d(30) <= sram_d_I(30) when sram_d_OE(30) = '1' else 'Z';
     sram_d_OE(30) <= st(3);
FDCPE_sram_d31: FDCPE port map (sram_d_I(31),channel(31),clk_ob,'0','0');
     sram_d(31) <= sram_d_I(31) when sram_d_OE(31) = '1' else 'Z';
     sram_d_OE(31) <= st(3);
FDCPE_sram_oe_l: FDCPE port map (sram_oe_l,sram_oe_l_D,clk_ob,'0',clr);
     sram_oe_l_D <= ((state_FFd3 AND state_FFd2 AND state_FFd1)
      OR (NOT state_FFd3 AND state_FFd2 AND NOT state_FFd1));
FDCPE_sram_we_l: FDCPE port map (sram_we_l,sram_we_l_D,clk_ob,clr,'0');
     sram_we_l_D <= ((state_FFd3 AND state_FFd2 AND state_FFd1)
      OR (NOT state_FFd3 AND state_FFd2 AND NOT state_FFd1));
FDCPE_st1: FDCPE port map (st(1),st_D(1),clk_ob,'0',clr);
     st_D(1) <= ((NOT state_FFd2)
      OR (NOT state_FFd3 AND NOT state_FFd1));
FDCPE_st2: FDCPE port map (st(2),st_D(2),clk_ob,'0',clr);
     st_D(2) <= ((NOT state_FFd3 AND NOT state_FFd2)
      OR (state_FFd2 AND NOT state_FFd1));
FDCPE_st3: FDCPE port map (st(3),st_D(3),clk_ob,'0',clr);
     st_D(3) <= ((state_FFd3 AND state_FFd2 AND state_FFd1)
      OR (NOT state_FFd3 AND state_FFd2 AND NOT state_FFd1));
FDCPE_state_FFd1: FDCPE port map (state_FFd1,state_FFd1_D,clk_ob,clr,'0');
     state_FFd1_D <= ((EXP46_.EXP)
      OR (sram_adr_5_OBUF.EXP)
      OR (state_FFd3 AND state_FFd2 AND NOT state_FFd1)
      OR (state_FFd3 AND NOT state_FFd1 AND stop)
      OR (NOT state_FFd3 AND NOT state_FFd2 AND NOT state_FFd1)
      OR (NOT state_FFd3 AND state_FFd1 AND stop));
FDCPE_state_FFd2: FDCPE port map (state_FFd2,state_FFd2_D,clk_ob,clr,'0');
     state_FFd2_D <= ((epp_I/bytesel(0).EXP)
      OR (edge_reg(9).EXP)
      OR (NOT state_FFd3 AND NOT state_FFd2 AND NOT state_FFd1 AND NOT run)
      OR (NOT state_FFd3 AND NOT state_FFd2 AND NOT state_FFd1 AND
      pretrig_off)
      OR (state_FFd3 AND state_FFd2 AND NOT state_FFd1 AND NOT stop AND
      sample_cnt_wm)
      OR (NOT trigcond_I/trig_cnt(0) AND state_FFd3 AND NOT state_FFd2 AND
      NOT state_FFd1 AND NOT stop AND tcnt_reg(0)));
FTCPE_state_FFd3: FTCPE port map (state_FFd3,state_FFd3_T,clk_ob,clr,'0');
     state_FFd3_T <= ((EXP49_.EXP)
      OR (state_FFd3 AND state_FFd1)
      OR (state_FFd2 AND state_FFd1));
FDCPE_stop: FDCPE port map (stop,dd(3).PIN,clk_in,'0','0',stop_CE);
     stop_CE <= (NOT epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_tcnt_reg0: FDCPE port map (tcnt_reg(0),dd(0).PIN,NOT clk_in,'0','0',tcnt_reg_CE(0));
     tcnt_reg_CE(0) <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_tcnt_reg1: FDCPE port map (tcnt_reg(1),dd(1).PIN,NOT clk_in,'0','0',tcnt_reg_CE(1));
     tcnt_reg_CE(1) <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_tcnt_reg2: FDCPE port map (tcnt_reg(2),dd(2).PIN,NOT clk_in,'0','0',tcnt_reg_CE(2));
     tcnt_reg_CE(2) <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_tcnt_reg3: FDCPE port map (tcnt_reg(3),dd(3).PIN,NOT clk_in,'0','0',tcnt_reg_CE(3));
     tcnt_reg_CE(3) <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FTCPE_timebase_I/clk_2: FTCPE port map (timebase_I/clk_2,'1',clk_in,clr,'0',timebase_I/clk_2_CE);
     timebase_I/clk_2_CE <= (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND
      NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND
      NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND
      NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(17) AND
      NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND
      NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND
      NOT timebase_I/clk_cnt(9) AND NOT timebase_I/clk_cnt(18));
FTCPE_timebase_I/clk_5f0: FTCPE port map (timebase_I/clk_5f(0),timebase_I/clk_5f_T(0),NOT clk_in,clr,'0');
     timebase_I/clk_5f_T(0) <= (NOT timebase_I/clk_5f(0) AND NOT timebase_I/clk_5f(1) AND
      NOT timebase_I/clk_5f(2));
FDCPE_timebase_I/clk_5f1: FDCPE port map (timebase_I/clk_5f(1),timebase_I/clk_5f_D(1),NOT clk_in,clr,'0');
     timebase_I/clk_5f_D(1) <= ((timebase_I/clk_5f(0) AND timebase_I/clk_5f(1))
      OR (NOT timebase_I/clk_5f(0) AND NOT timebase_I/clk_5f(1) AND
      timebase_I/clk_5f(2)));
FTCPE_timebase_I/clk_5f2: FTCPE port map (timebase_I/clk_5f(2),timebase_I/clk_5f_T(2),NOT clk_in,clr,'0');
     timebase_I/clk_5f_T(2) <= (NOT timebase_I/clk_5f(0) AND NOT timebase_I/clk_5f(1));
FTCPE_timebase_I/clk_cnt0: FTCPE port map (timebase_I/clk_cnt(0),timebase_I/clk_cnt_T(0),clk_in,clr,'0');
     timebase_I/clk_cnt_T(0) <= ((trig_o_OBUF.EXP)
      OR (tsel_reg(2) AND tsel_reg(4) AND
      NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND
      NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND
      NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND
      NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(3) AND
      NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND
      NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND
      NOT timebase_I/clk_cnt(18))
      OR (tsel_reg(3) AND tsel_reg(4) AND
      NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND
      NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND
      NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND
      NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(3) AND
      NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND
      NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND
      NOT timebase_I/clk_cnt(18))
      OR (tsel_reg(1) AND tsel_reg(4) AND tsel_reg(0) AND
      NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND
      NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND
      NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND
      NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(3) AND
      NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND
      NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND
      NOT timebase_I/clk_cnt(18))
      OR (NOT tsel_reg(2) AND NOT tsel_reg(3) AND NOT tsel_reg(4) AND
      NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND
      NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND
      NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND
      NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(3) AND
      NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND
      NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND
      NOT timebase_I/clk_cnt(18)));
FTCPE_timebase_I/clk_cnt1: FTCPE port map (timebase_I/clk_cnt(1),timebase_I/clk_cnt_T(1),clk_in,clr,'0');
     timebase_I/clk_cnt_T(1) <= ((EXP51_.EXP)
      OR (NOT tsel_reg(1) AND NOT tsel_reg(3) AND NOT tsel_reg(4) AND
      NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND
      NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND
      NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(16) AND
      NOT timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND
      NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND
      NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND NOT timebase_I/clk_cnt(18))
      OR (NOT tsel_reg(2) AND NOT tsel_reg(3) AND NOT tsel_reg(4) AND
      NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND
      NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND
      NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(16) AND
      NOT timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND
      NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND
      NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND NOT timebase_I/clk_cnt(18))
      OR (NOT tsel_reg(3) AND NOT tsel_reg(4) AND NOT tsel_reg(0) AND
      NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND
      NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND
      NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(16) AND
      NOT timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND
      NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND
      NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND NOT timebase_I/clk_cnt(18))
      OR (NOT tsel_reg(1) AND NOT tsel_reg(2) AND NOT tsel_reg(4) AND
      NOT tsel_reg(0) AND NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND
      NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND
      NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND
      NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(3) AND
      NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND
      NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND
      NOT timebase_I/clk_cnt(18)));
FTCPE_timebase_I/clk_cnt2: FTCPE port map (timebase_I/clk_cnt(2),timebase_I/clk_cnt_T(2),clk_in,clr,'0');
     timebase_I/clk_cnt_T(2) <= ((timebase_I/clk_cnt(0))
      OR (timebase_I/clk_cnt(1))
      OR (channel_reg(6).EXP)
      OR (tsel_reg(2) AND NOT tsel_reg(3) AND
      NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND
      NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND
      NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(17) AND
      NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND
      NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND
      NOT timebase_I/clk_cnt(9) AND NOT timebase_I/clk_cnt(18))
      OR (tsel_reg(3) AND tsel_reg(4) AND
      NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND
      NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND
      NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(17) AND
      NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND
      NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND
      NOT timebase_I/clk_cnt(9) AND NOT timebase_I/clk_cnt(18)));
FTCPE_timebase_I/clk_cnt3: FTCPE port map (timebase_I/clk_cnt(3),timebase_I/clk_cnt_T(3),clk_in,clr,'0');
     timebase_I/clk_cnt_T(3) <= ((timebase_I/clk_cnt(0))
      OR (timebase_I/clk_cnt(1))
      OR (timebase_I/clk_cnt(2))
      OR (EXP42_.EXP)
      OR (timebase_I/clk_cnt(6).EXP)
      OR (NOT tsel_reg(2) AND NOT tsel_reg(3) AND NOT tsel_reg(4) AND
      NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND
      NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND
      NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(3) AND
      NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND
      NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND
      NOT timebase_I/clk_cnt(18)));
FTCPE_timebase_I/clk_cnt4: FTCPE port map (timebase_I/clk_cnt(4),timebase_I/clk_cnt_T(4),clk_in,clr,'0');
     timebase_I/clk_cnt_T(4) <= ((sram_adsc_l_OBUF$BUF0.EXP)
      OR (sram_adr_8_OBUF.EXP)
      OR (tsel_reg(1) AND tsel_reg(3) AND
      NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND
      NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND
      NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(4) AND
      NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND
      NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND NOT timebase_I/clk_cnt(18))
      OR (tsel_reg(4) AND tsel_reg(0) AND
      NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND
      NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND
      NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(4) AND
      NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND
      NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND NOT timebase_I/clk_cnt(18))
      OR (NOT tsel_reg(1) AND tsel_reg(2) AND NOT tsel_reg(0) AND
      NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND
      NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND
      NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(4) AND
      NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND
      NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND NOT timebase_I/clk_cnt(18))
      OR (NOT tsel_reg(2) AND NOT tsel_reg(3) AND NOT tsel_reg(4) AND
      NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND
      NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND
      NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(4) AND
      NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND
      NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND NOT timebase_I/clk_cnt(18)));
FTCPE_timebase_I/clk_cnt5: FTCPE port map (timebase_I/clk_cnt(5),timebase_I/clk_cnt_T(5),clk_in,clr,'0');
     timebase_I/clk_cnt_T(5) <= ((timebase_I/clk_cnt(0))
      OR (timebase_I/clk_cnt(1))
      OR (timebase_I/clk_cnt(2))
      OR (timebase_I/clk_cnt(3))
      OR (EXP52_.EXP)
      OR (sram_adr_2_OBUF.EXP));
FTCPE_timebase_I/clk_cnt6: FTCPE port map (timebase_I/clk_cnt(6),timebase_I/clk_cnt_T(6),clk_in,clr,'0');
     timebase_I/clk_cnt_T(6) <= ((timebase_I/clk_cnt(0))
      OR (timebase_I/clk_cnt(1))
      OR (EXP32_.EXP));
FTCPE_timebase_I/clk_cnt7: FTCPE port map (timebase_I/clk_cnt(7),timebase_I/clk_cnt_T(7),clk_in,clr,'0');
     timebase_I/clk_cnt_T(7) <= ((timebase_I/clk_cnt(0))
      OR (timebase_I/clk_cnt(1))
      OR (timebase_I/clk_cnt(10).EXP)
      OR (EXP36_.EXP)
      OR (tsel_reg(1) AND tsel_reg(4) AND
      NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND
      NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND
      NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(7) AND
      NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND NOT timebase_I/clk_cnt(18))
      OR (tsel_reg(2) AND tsel_reg(4) AND
      NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND
      NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND
      NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(7) AND
      NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND NOT timebase_I/clk_cnt(18)));
FTCPE_timebase_I/clk_cnt8: FTCPE port map (timebase_I/clk_cnt(8),timebase_I/clk_cnt_T(8),clk_in,clr,'0');
     timebase_I/clk_cnt_T(8) <= ((timebase_I/clk_cnt(0))
      OR (EXP55_.EXP)
      OR (tsel_reg(2) AND tsel_reg(4) AND
      NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND
      NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND
      NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(8) AND
      NOT timebase_I/clk_cnt(9) AND NOT timebase_I/clk_cnt(18))
      OR (tsel_reg(4) AND tsel_reg(0) AND
      NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND
      NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND
      NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(8) AND
      NOT timebase_I/clk_cnt(9) AND NOT timebase_I/clk_cnt(18)));
FTCPE_timebase_I/clk_cnt9: FTCPE port map (timebase_I/clk_cnt(9),timebase_I/clk_cnt_T(9),clk_in,clr,'0');
     timebase_I/clk_cnt_T(9) <= ((sram_adsc_l_OBUF.EXP)
      OR (EXP61_.EXP)
      OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND
      NOT timebase_I/clk_cnt(2) AND timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(3) AND
      NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND
      NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8))
      OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND
      NOT timebase_I/clk_cnt(2) AND timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(3) AND
      NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND
      NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8))
      OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND
      NOT timebase_I/clk_cnt(2) AND timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(3) AND
      NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND
      NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8))
      OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND
      NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND
      NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND
      NOT timebase_I/clk_cnt(8) AND timebase_I/clk_cnt(18)));
FTCPE_timebase_I/clk_cnt10: FTCPE port map (timebase_I/clk_cnt(10),timebase_I/clk_cnt_T(10),clk_in,clr,'0');
     timebase_I/clk_cnt_T(10) <= ((EXP35_.EXP)
      OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND
      NOT timebase_I/clk_cnt(2) AND timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(3) AND
      NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND
      NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9)));
FTCPE_timebase_I/clk_cnt11: FTCPE port map (timebase_I/clk_cnt(11),timebase_I/clk_cnt_T(11),clk_in,clr,'0');
     timebase_I/clk_cnt_T(11) <= ((timebase_I/clk_cnt(14).EXP)
      OR (sram_adr_7_OBUF.EXP)
      OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND
      NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND timebase_I/clk_cnt(11) AND
      NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND
      NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND
      NOT timebase_I/clk_cnt(9))
      OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND
      NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND timebase_I/clk_cnt(12) AND
      NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND
      NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND
      NOT timebase_I/clk_cnt(9))
      OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND
      NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND timebase_I/clk_cnt(17) AND
      NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND
      NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND
      NOT timebase_I/clk_cnt(9))
      OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND
      NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(3) AND
      NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND
      NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND
      timebase_I/clk_cnt(18)));
FTCPE_timebase_I/clk_cnt12: FTCPE port map (timebase_I/clk_cnt(12),timebase_I/clk_cnt_T(12),clk_in,clr,'0');
     timebase_I/clk_cnt_T(12) <= ((EXP53_.EXP)
      OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND
      NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND
      timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND
      NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND
      NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9))
      OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND
      NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND
      timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND
      NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND
      NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9))
      OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND
      NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND
      timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND
      NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND
      NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9))
      OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND
      NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND
      NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND
      NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND
      NOT timebase_I/clk_cnt(9) AND timebase_I/clk_cnt(18)));
FTCPE_timebase_I/clk_cnt13: FTCPE port map (timebase_I/clk_cnt(13),timebase_I/clk_cnt_T(13),clk_in,clr,'0');
     timebase_I/clk_cnt_T(13) <= ((sram_adr_0_OBUF.EXP)
      OR (sram_adr_6_OBUF.EXP)
      OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND
      NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND
      NOT timebase_I/clk_cnt(12) AND timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(3) AND
      NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND
      NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9))
      OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND
      NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND
      NOT timebase_I/clk_cnt(12) AND timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(3) AND
      NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND
      NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9))
      OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND
      NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND
      NOT timebase_I/clk_cnt(12) AND timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(3) AND
      NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND
      NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9))
      OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND
      NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND
      NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND
      NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND
      NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND timebase_I/clk_cnt(18)));
FTCPE_timebase_I/clk_cnt14: FTCPE port map (timebase_I/clk_cnt(14),timebase_I/clk_cnt_T(14),clk_in,clr,'0');
     timebase_I/clk_cnt_T(14) <= ((EXP50_.EXP)
      OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND
      NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND
      NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND timebase_I/clk_cnt(17) AND
      NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND
      NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND
      NOT timebase_I/clk_cnt(9))
      OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND
      NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND
      NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(3) AND
      NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND
      NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND
      timebase_I/clk_cnt(18)));
FTCPE_timebase_I/clk_cnt15: FTCPE port map (timebase_I/clk_cnt(15),timebase_I/clk_cnt_T(15),clk_in,clr,'0');
     timebase_I/clk_cnt_T(15) <= ((timebase_I/clk_2.EXP)
      OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND
      NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND
      NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND
      timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND
      NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND
      NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9))
      OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND
      NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND
      NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND
      timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND
      NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND
      NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9))
      OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND
      NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND
      NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND
      NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND
      NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND
      NOT timebase_I/clk_cnt(9) AND timebase_I/clk_cnt(18))
      OR (NOT tsel_reg(1) AND NOT tsel_reg(2) AND NOT tsel_reg(3) AND
      tsel_reg(4) AND NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND
      NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND
      NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND
      NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND
      NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND
      NOT timebase_I/clk_cnt(9)));
FTCPE_timebase_I/clk_cnt16: FTCPE port map (timebase_I/clk_cnt(16),timebase_I/clk_cnt_T(16),clk_in,clr,'0');
     timebase_I/clk_cnt_T(16) <= ((channel_reg(5).EXP)
      OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND
      NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND
      NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND
      NOT timebase_I/clk_cnt(15) AND timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(3) AND
      NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND
      NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9))
      OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND
      NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND
      NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND
      NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND
      NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND
      NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND timebase_I/clk_cnt(18))
      OR (NOT tsel_reg(1) AND NOT tsel_reg(2) AND NOT tsel_reg(3) AND
      tsel_reg(4) AND NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND
      NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND
      NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND
      NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND
      NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND
      NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9))
      OR (NOT tsel_reg(2) AND NOT tsel_reg(3) AND tsel_reg(4) AND
      NOT tsel_reg(0) AND NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND
      NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND
      NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND
      NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND
      NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND
      NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9)));
FTCPE_timebase_I/clk_cnt17: FTCPE port map (timebase_I/clk_cnt(17),timebase_I/clk_cnt_T(17),clk_in,clr,'0');
     timebase_I/clk_cnt_T(17) <= ((NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND
      NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND
      NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND
      NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(16) AND timebase_I/clk_cnt(17) AND
      NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND
      NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND
      NOT timebase_I/clk_cnt(9))
      OR (NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND
      NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND
      NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND
      NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(3) AND
      NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND
      NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9) AND
      timebase_I/clk_cnt(18))
      OR (tsel_reg(1) AND NOT tsel_reg(2) AND NOT tsel_reg(3) AND
      tsel_reg(4) AND NOT tsel_reg(0) AND NOT timebase_I/clk_cnt(0) AND
      NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND
      NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND
      NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(16) AND
      NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND
      NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND
      NOT timebase_I/clk_cnt(9))
      OR (NOT tsel_reg(1) AND NOT tsel_reg(2) AND NOT tsel_reg(3) AND
      tsel_reg(4) AND tsel_reg(0) AND NOT timebase_I/clk_cnt(0) AND
      NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND
      NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND
      NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(16) AND
      NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND
      NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND
      NOT timebase_I/clk_cnt(9)));
FTCPE_timebase_I/clk_cnt18: FTCPE port map (timebase_I/clk_cnt(18),timebase_I/clk_cnt_T(18),clk_in,clr,'0');
     timebase_I/clk_cnt_T(18) <= ((NOT timebase_I/clk_cnt(0) AND NOT timebase_I/clk_cnt(1) AND
      NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND NOT timebase_I/clk_cnt(11) AND
      NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND NOT timebase_I/clk_cnt(14) AND
      NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(16) AND NOT timebase_I/clk_cnt(17) AND
      NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND NOT timebase_I/clk_cnt(5) AND
      NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND NOT timebase_I/clk_cnt(8) AND
      NOT timebase_I/clk_cnt(9) AND timebase_I/clk_cnt(18))
      OR (tsel_reg(1) AND NOT tsel_reg(2) AND NOT tsel_reg(3) AND
      tsel_reg(4) AND NOT tsel_reg(0) AND NOT timebase_I/clk_cnt(0) AND
      NOT timebase_I/clk_cnt(1) AND NOT timebase_I/clk_cnt(2) AND NOT timebase_I/clk_cnt(10) AND
      NOT timebase_I/clk_cnt(11) AND NOT timebase_I/clk_cnt(12) AND NOT timebase_I/clk_cnt(13) AND
      NOT timebase_I/clk_cnt(14) AND NOT timebase_I/clk_cnt(15) AND NOT timebase_I/clk_cnt(16) AND
      NOT timebase_I/clk_cnt(17) AND NOT timebase_I/clk_cnt(3) AND NOT timebase_I/clk_cnt(4) AND
      NOT timebase_I/clk_cnt(5) AND NOT timebase_I/clk_cnt(6) AND NOT timebase_I/clk_cnt(7) AND
      NOT timebase_I/clk_cnt(8) AND NOT timebase_I/clk_cnt(9)));
FDCPE_timebase_I/sw_read_clk_f: FDCPE port map (timebase_I/sw_read_clk_f,done,NOT clk_o,clr,'0');
FDCPE_timebase_I/sw_read_clk_r: FDCPE port map (timebase_I/sw_read_clk_r,done,clk_o,clr,'0');
FDCPE_tlen_reg0: FDCPE port map (tlen_reg(0),dd(0).PIN,NOT clk_in,'0','0',tlen_reg_CE(0));
     tlen_reg_CE(0) <= (epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_tlen_reg1: FDCPE port map (tlen_reg(1),dd(1).PIN,NOT clk_in,'0','0',tlen_reg_CE(1));
     tlen_reg_CE(1) <= (epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_tlen_reg2: FDCPE port map (tlen_reg(2),dd(2).PIN,NOT clk_in,'0','0',tlen_reg_CE(2));
     tlen_reg_CE(2) <= (epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_tlen_reg3: FDCPE port map (tlen_reg(3),dd(3).PIN,NOT clk_in,'0','0',tlen_reg_CE(3));
     tlen_reg_CE(3) <= (epp_I/adr(1) AND NOT epp_I/adr(0) AND NOT epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
trig_o <= NOT (((EXP24_.EXP)
      OR (trigcond_I/trig_cnt(0) AND NOT tcnt_reg(0))
      OR (NOT trigcond_I/trig_cnt(0) AND tcnt_reg(0))
      OR (trigcond_I/trig_cnt(1) AND NOT tcnt_reg(1))
      OR (NOT trigcond_I/trig_cnt(1) AND tcnt_reg(1))));
FDCPE_trig_on: FDCPE port map (trig_on,trig_on_D,clk_ob,clr,'0');
     trig_on_D <= (state_FFd3 AND NOT state_FFd2);
FDCPE_trigcond_I/extrig_int: FDCPE port map (trigcond_I/extrig_int,trigcond_I/trig_on_d.EXP,clk_ob,'0','0');
FDCPE_trigcond_I/int_etrig_hit_reg: FDCPE port map (trigcond_I/int_etrig_hit_reg,trigcond_I/int_etrig_hit_reg_D,clk_ob,clr,'0');
     trigcond_I/int_etrig_hit_reg_D <= ((EXP44_.EXP)
      OR (EXP45_.EXP)
      OR (edge_reg(2) AND
      NOT $OpTx$trigcond_I/int_vtrig_comp(2)/trigcond_I/int_vtrig_comp(2)_D2_INV$526)
      OR (edge_reg(3) AND
      NOT $OpTx$trigcond_I/int_vtrig_comp(3)/trigcond_I/int_vtrig_comp(3)_D2_INV$527)
      OR (edge_reg(4) AND
      NOT $OpTx$trigcond_I/int_vtrig_comp(4)/trigcond_I/int_vtrig_comp(4)_D2_INV$528)
      OR (edge_reg(5) AND
      NOT $OpTx$trigcond_I/int_vtrig_comp(5)/trigcond_I/int_vtrig_comp(5)_D2_INV$529));
FDCPE_trigcond_I/int_trig_hit_reg: FDCPE port map (trigcond_I/int_trig_hit_reg,trigcond_I/int_trig_hit_reg_D,clk_ob,clr,'0');
     trigcond_I/int_trig_hit_reg_D <= ((
      $OpTx$trigcond_I/int_vtrig_comp(2)/trigcond_I/int_vtrig_comp(2)_D2_INV$526)
      OR (
      $OpTx$trigcond_I/int_vtrig_comp(5)/trigcond_I/int_vtrig_comp(5)_D2_INV$529)
      OR (
      $OpTx$trigcond_I/int_vtrig_comp(3)/trigcond_I/int_vtrig_comp(3)_D2_INV$527)
      OR (
      $OpTx$trigcond_I/int_vtrig_comp(6)/trigcond_I/int_vtrig_comp(6)_D2_INV$530)
      OR (EXP63_.EXP)
      OR (EXP64_.EXP));
FDCPE_trigcond_I/tlen_cnt0: FDCPE port map (trigcond_I/tlen_cnt(0),trigcond_I/tlen_cnt_D(0),clk_ob,clr,'0');
     trigcond_I/tlen_cnt_D(0) <= ((EXP67_.EXP)
      OR (EXP68_.EXP)
      OR (NOT trigcond_I/tlen_cnt(1) AND trigcond_I/tlen_cnt(2) AND
      trigcond_I/tlen_cnt(3) AND NOT tlen_reg(0) AND NOT tlen_reg(1) AND tlen_reg(2) AND
      tlen_reg(3))
      OR (NOT trigcond_I/tlen_cnt(1) AND trigcond_I/tlen_cnt(2) AND
      NOT trigcond_I/tlen_cnt(3) AND NOT tlen_reg(0) AND NOT tlen_reg(1) AND tlen_reg(2) AND
      NOT tlen_reg(3))
      OR (NOT trigcond_I/tlen_cnt(1) AND NOT trigcond_I/tlen_cnt(2) AND
      trigcond_I/tlen_cnt(3) AND NOT tlen_reg(0) AND NOT tlen_reg(1) AND NOT tlen_reg(2) AND
      tlen_reg(3))
      OR (NOT trigcond_I/tlen_cnt(1) AND NOT trigcond_I/tlen_cnt(2) AND
      NOT trigcond_I/tlen_cnt(3) AND NOT tlen_reg(0) AND NOT tlen_reg(1) AND NOT tlen_reg(2) AND
      NOT tlen_reg(3)));
FDCPE_trigcond_I/tlen_cnt1: FDCPE port map (trigcond_I/tlen_cnt(1),trigcond_I/tlen_cnt_D(1),clk_ob,clr,'0');
     trigcond_I/tlen_cnt_D(1) <= ((EXP65_.EXP)
      OR (EXP69_.EXP)
      OR (trigcond_I/tlen_cnt(0) AND trigcond_I/tlen_cnt(2) AND
      trigcond_I/tlen_cnt(3) AND tlen_reg(0) AND NOT tlen_reg(1) AND tlen_reg(2) AND
      tlen_reg(3))
      OR (trigcond_I/tlen_cnt(0) AND trigcond_I/tlen_cnt(2) AND
      NOT trigcond_I/tlen_cnt(3) AND tlen_reg(0) AND NOT tlen_reg(1) AND tlen_reg(2) AND
      NOT tlen_reg(3))
      OR (trigcond_I/tlen_cnt(0) AND NOT trigcond_I/tlen_cnt(2) AND
      trigcond_I/tlen_cnt(3) AND tlen_reg(0) AND NOT tlen_reg(1) AND NOT tlen_reg(2) AND
      tlen_reg(3))
      OR (trigcond_I/tlen_cnt(0) AND NOT trigcond_I/tlen_cnt(2) AND
      NOT trigcond_I/tlen_cnt(3) AND tlen_reg(0) AND NOT tlen_reg(1) AND NOT tlen_reg(2) AND
      NOT tlen_reg(3)));
FDCPE_trigcond_I/tlen_cnt2: FDCPE port map (trigcond_I/tlen_cnt(2),trigcond_I/tlen_cnt_D(2),clk_ob,clr,'0');
     trigcond_I/tlen_cnt_D(2) <= ((NOT trigcond_I/trig_on_d)
      OR (EXP30_.EXP)
      OR (trigcond_I/trig_cnt(1).EXP)
      OR (trigcond_I/tlen_cnt(0) AND trigcond_I/tlen_cnt(1) AND
      trigcond_I/tlen_cnt(2) AND NOT tlen_reg(2))
      OR (NOT trigcond_I/tlen_cnt(2) AND trigcond_I/tlen_cnt(3) AND
      tlen_reg(0) AND tlen_reg(1) AND NOT tlen_reg(2) AND tlen_reg(3))
      OR (NOT trigcond_I/tlen_cnt(2) AND NOT trigcond_I/tlen_cnt(3) AND
      tlen_reg(0) AND tlen_reg(1) AND NOT tlen_reg(2) AND NOT tlen_reg(3)));
FDCPE_trigcond_I/tlen_cnt3: FDCPE port map (trigcond_I/tlen_cnt(3),trigcond_I/tlen_cnt_D(3),clk_ob,clr,'0');
     trigcond_I/tlen_cnt_D(3) <= ((NOT trigcond_I/trig_on_d)
      OR (EXP29_.EXP)
      OR (trigcond_I/tlen_cnt(0) AND trigcond_I/tlen_cnt(1) AND
      trigcond_I/tlen_cnt(2) AND tlen_reg(0) AND tlen_reg(1) AND tlen_reg(2) AND
      NOT tlen_reg(3)));
FDCPE_trigcond_I/tlen_top_d: FDCPE port map (trigcond_I/tlen_top_d,trigcond_I/tlen_top_d_D,clk_ob,clr,'0');
     trigcond_I/tlen_top_d_D <= ((sram_adr_4_OBUF.EXP)
      OR (sram_adr_3_OBUF.EXP)
      OR (trigcond_I/tlen_cnt(2) AND NOT tlen_reg(2))
      OR (NOT trigcond_I/tlen_cnt(2) AND tlen_reg(2))
      OR (trigcond_I/tlen_cnt(3) AND NOT tlen_reg(3))
      OR (NOT trigcond_I/tlen_cnt(3) AND tlen_reg(3)));
FTCPE_trigcond_I/trig_cnt0: FTCPE port map (trigcond_I/trig_cnt(0),trigcond_I/trig_cnt_T(0),clk_ob,clr,'0');
     trigcond_I/trig_cnt_T(0) <= ((trigcond_I/tlen_top_d)
      OR (EXP23_.EXP)
      OR (NOT trigcond_I/tlen_cnt(2) AND tlen_reg(2))
      OR (trigcond_I/tlen_cnt(3) AND NOT tlen_reg(3))
      OR (NOT trigcond_I/tlen_cnt(3) AND tlen_reg(3)));
FTCPE_trigcond_I/trig_cnt1: FTCPE port map (trigcond_I/trig_cnt(1),trigcond_I/trig_cnt_T(1),clk_ob,clr,'0');
     trigcond_I/trig_cnt_T(1) <= ((EXP31_.EXP)
      OR (trigcond_I/tlen_cnt(0) AND NOT tlen_reg(0)));
FTCPE_trigcond_I/trig_cnt2: FTCPE port map (trigcond_I/trig_cnt(2),trigcond_I/trig_cnt_T(2),clk_ob,clr,'0');
     trigcond_I/trig_cnt_T(2) <= ((EXP26_.EXP)
      OR (trigcond_I/tlen_cnt(0) AND NOT tlen_reg(0)));
FTCPE_trigcond_I/trig_cnt3: FTCPE port map (trigcond_I/trig_cnt(3),trigcond_I/trig_cnt_T(3),clk_ob,clr,'0');
     trigcond_I/trig_cnt_T(3) <= ((trigcond_I/trig_cnt(2).EXP)
      OR (EXP27_.EXP)
      OR (trigcond_I/tlen_cnt(0) AND NOT tlen_reg(0))
      OR (NOT trigcond_I/tlen_cnt(0) AND tlen_reg(0))
      OR (trigcond_I/tlen_cnt(1) AND NOT tlen_reg(1))
      OR (NOT trigcond_I/tlen_cnt(1) AND tlen_reg(1)));
FDCPE_trigcond_I/trig_on_d: FDCPE port map (trigcond_I/trig_on_d,trig_on,clk_ob,clr,'0');
FDCPE_tsel_reg0: FDCPE port map (tsel_reg(0),dd(0).PIN,NOT clk_in,'0','0',tsel_reg_CE(0));
     tsel_reg_CE(0) <= (epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_tsel_reg1: FDCPE port map (tsel_reg(1),dd(1).PIN,NOT clk_in,'0','0',tsel_reg_CE(1));
     tsel_reg_CE(1) <= (epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_tsel_reg2: FDCPE port map (tsel_reg(2),dd(2).PIN,NOT clk_in,'0','0',tsel_reg_CE(2));
     tsel_reg_CE(2) <= (epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_tsel_reg3: FDCPE port map (tsel_reg(3),dd(3).PIN,NOT clk_in,'0','0',tsel_reg_CE(3));
     tsel_reg_CE(3) <= (epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_tsel_reg4: FDCPE port map (tsel_reg(4),dd(4).PIN,NOT clk_in,'0','0',tsel_reg_CE(4));
     tsel_reg_CE(4) <= (epp_I/adr(1) AND epp_I/adr(0) AND NOT epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_value_reg0: FDCPE port map (value_reg(0),dd(0).PIN,NOT clk_in,'0','0',value_reg_CE(0));
     value_reg_CE(0) <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_value_reg1: FDCPE port map (value_reg(1),dd(1).PIN,NOT clk_in,'0','0',value_reg_CE(1));
     value_reg_CE(1) <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_value_reg2: FDCPE port map (value_reg(2),dd(2).PIN,NOT clk_in,'0','0',value_reg_CE(2));
     value_reg_CE(2) <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_value_reg3: FDCPE port map (value_reg(3),dd(3).PIN,NOT clk_in,'0','0',value_reg_CE(3));
     value_reg_CE(3) <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_value_reg4: FDCPE port map (value_reg(4),dd(4).PIN,NOT clk_in,'0','0',value_reg_CE(4));
     value_reg_CE(4) <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_value_reg5: FDCPE port map (value_reg(5),dd(5).PIN,NOT clk_in,'0','0',value_reg_CE(5));
     value_reg_CE(5) <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_value_reg6: FDCPE port map (value_reg(6),dd(6).PIN,NOT clk_in,'0','0',value_reg_CE(6));
     value_reg_CE(6) <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_value_reg7: FDCPE port map (value_reg(7),dd(7).PIN,NOT clk_in,'0','0',value_reg_CE(7));
     value_reg_CE(7) <= (NOT epp_I/adr(1) AND epp_I/adr(0) AND epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_value_reg8: FDCPE port map (value_reg(8),dd(0).PIN,NOT clk_in,'0','0',value_reg_CE(8));
     value_reg_CE(8) <= (epp_I/adr(1) AND NOT epp_I/adr(0) AND epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_value_reg9: FDCPE port map (value_reg(9),dd(1).PIN,NOT clk_in,'0','0',value_reg_CE(9));
     value_reg_CE(9) <= (epp_I/adr(1) AND NOT epp_I/adr(0) AND epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_value_reg10: FDCPE port map (value_reg(10),dd(2).PIN,NOT clk_in,'0','0',value_reg_CE(10));
     value_reg_CE(10) <= (epp_I/adr(1) AND NOT epp_I/adr(0) AND epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_value_reg11: FDCPE port map (value_reg(11),dd(3).PIN,NOT clk_in,'0','0',value_reg_CE(11));
     value_reg_CE(11) <= (epp_I/adr(1) AND NOT epp_I/adr(0) AND epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_value_reg12: FDCPE port map (value_reg(12),dd(4).PIN,NOT clk_in,'0','0',value_reg_CE(12));
     value_reg_CE(12) <= (epp_I/adr(1) AND NOT epp_I/adr(0) AND epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_value_reg13: FDCPE port map (value_reg(13),dd(5).PIN,NOT clk_in,'0','0',value_reg_CE(13));
     value_reg_CE(13) <= (epp_I/adr(1) AND NOT epp_I/adr(0) AND epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_value_reg14: FDCPE port map (value_reg(14),dd(6).PIN,NOT clk_in,'0','0',value_reg_CE(14));
     value_reg_CE(14) <= (epp_I/adr(1) AND NOT epp_I/adr(0) AND epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
FDCPE_value_reg15: FDCPE port map (value_reg(15),dd(7).PIN,NOT clk_in,'0','0',value_reg_CE(15));
     value_reg_CE(15) <= (epp_I/adr(1) AND NOT epp_I/adr(0) AND epp_I/adr(2) AND
      NOT epp_I/adr(3) AND NOT epp_I/ALE_l_i AND epp_I/RD_l_i AND NOT epp_I/WR_l_i);
Register Legend:
      FDCPE (Q,D,C,CLR,PRE,CE);
      FTCPE (Q,D,C,CLR,PRE,CE);
      LDCP (Q,D,G,CLR,PRE);