FB1
FB2
FB3
FB4
FB5
FB6
FB7
FB8
FB9
FB10
FB11
FB12
FB13
FB14
FB15
FB16
Signal Name
Total Product Terms
Product Terms
Location
Power Mode
Pin Number
PinType
Pin Use
timebase_I/clk_cnt<15>
8
18_3
18_4
18_5
1_1
1_2
1_3
1_4
1_5
MC1
STD
(b)
(b)
timebase_I/clk_cnt<2>
8
2_1
2_2
2_3
2_4
2_5
3_3
3_4
3_5
MC2
STD
(b)
(b)
sram_d<6>
2
3_1
3_2
MC3
STD
100
I/O
I/O
timebase_I/clk_cnt<16>
6
4_1
4_2
4_3
4_4
4_5
5_3
MC4
STD
(b)
(b)
sram_d<5>
2
5_1
5_2
MC5
STD
101
I/O
I/O
sram_d<4>
2
6_1
6_2
MC6
STD
102
I/O
I/O
timebase_I/clk_cnt<17>
5
7_1
7_2
7_3
7_4
7_5
MC7
STD
(b)
(b)
sram_d<3>
2
8_1
8_2
MC8
STD
103
I/O
I/O
timebase_I/clk_cnt<18>
3
9_1
9_2
9_3
MC9
STD
(b)
(b)
sram_d<2>
2
10_1
10_2
MC10
STD
104
I/O
I/O
sram_d<1>
2
11_1
11_2
MC11
STD
105
I/O
I/O
$OpTx$trigcond_I/int_vtrig_comp<2>/trigcond_I/int_vtrig_comp<2>_D2_INV$526
2
12_1
12_2
MC12
STD
(b)
(b)
$OpTx$trigcond_I/int_vtrig_comp<3>/trigcond_I/int_vtrig_comp<3>_D2_INV$527
2
13_1
13_2
MC13
STD
(b)
(b)
sram_d<0>
2
14_1
14_2
MC14
STD
106
I/O
I/O
$OpTx$trigcond_I/int_vtrig_comp<4>/trigcond_I/int_vtrig_comp<4>_D2_INV$528
2
15_1
15_2
MC15
STD
107
I/O
I
$OpTx$trigcond_I/int_vtrig_comp<5>/trigcond_I/int_vtrig_comp<5>_D2_INV$529
2
16_1
16_2
MC16
STD
(b)
(b)
$OpTx$trigcond_I/int_vtrig_comp<6>/trigcond_I/int_vtrig_comp<6>_D2_INV$530
2
17_1
17_2
MC17
STD
(b)
(b)
timebase_I/clk_2
2
18_1
18_2
MC18
STD
(b)
(b)
Signals Used By Logic in Function Block
channel<0>
channel<1>
channel<2>
channel<3>
channel<4>
channel<5>
channel<6>
clr
mask_reg<2>
mask_reg<3>
mask_reg<4>
mask_reg<5>
mask_reg<6>
st<3>
timebase_I/clk_cnt<0>
timebase_I/clk_cnt<10>
timebase_I/clk_cnt<11>
timebase_I/clk_cnt<12>
timebase_I/clk_cnt<13>
timebase_I/clk_cnt<14>
timebase_I/clk_cnt<15>
timebase_I/clk_cnt<16>
timebase_I/clk_cnt<17>
timebase_I/clk_cnt<18>
timebase_I/clk_cnt<1>
timebase_I/clk_cnt<2>
timebase_I/clk_cnt<3>
timebase_I/clk_cnt<4>
timebase_I/clk_cnt<5>
timebase_I/clk_cnt<6>
timebase_I/clk_cnt<7>
timebase_I/clk_cnt<8>
timebase_I/clk_cnt<9>
tsel_reg<0>
tsel_reg<1>
tsel_reg<2>
tsel_reg<3>
tsel_reg<4>
value_reg<2>
value_reg<3>
value_reg<4>
value_reg<5>
value_reg<6>