Signal Name | Total Pterms | Total Inputs | Function Block | Macrocell | Power Mode | Slew Rate | Pin Number | Pin Type | Pin Use | Reg Init State |
---|---|---|---|---|---|---|---|---|---|---|
trigcond_I/trig_cnt<0> | 10 | 10 | FB1 | MC3 | STD | (b) | (b) | RESET | ||
timebase_I/clk_cnt<0> | 6 | 25 | FB1 | MC4 | STD | (b) | (b) | RESET | ||
trig_o | 8 | 8 | FB1 | MC5 | STD | FAST | 20 | I/O | O | |
trigcond_I/trig_cnt<2> | 12 | 12 | FB1 | MC9 | STD | (b) | (b) | RESET | ||
trigcond_I/trig_cnt<3> | 13 | 13 | FB1 | MC10 | STD | 23 | I/O | (b) | RESET | |
trigcond_I/tlen_cnt<3> | 13 | 15 | FB1 | MC14 | STD | 25 | I/O | (b) | RESET | |
trigcond_I/tlen_cnt<2> | 15 | 15 | FB1 | MC16 | STD | (b) | (b) | RESET | ||
trigcond_I/trig_cnt<1> | 11 | 11 | FB1 | MC17 | STD | 27 | I/O | (b) | RESET | |
dd<4> | 13 | 22 | FB10 | MC2 | STD | FAST | 117 | I/O | I/O | |
dd<5> | 7 | 15 | FB10 | MC3 | STD | FAST | 118 | I/O | I/O | |
mask_reg<0> | 2 | 8 | FB10 | MC4 | STD | (b) | (b) | RESET | ||
dd<6> | 7 | 15 | FB10 | MC5 | STD | FAST | 119 | I/O | I/O | |
dd<7> | 6 | 15 | FB10 | MC6 | STD | FAST | 120 | I/O | I/O | |
extrig_val | 2 | 8 | FB10 | MC7 | STD | (b) | (b) | RESET | ||
extrig_en | 2 | 8 | FB10 | MC8 | STD | 121 | I/O | (b) | RESET | |
edge_reg<8> | 2 | 8 | FB10 | MC9 | STD | (b) | (b) | RESET | ||
edge_reg<1> | 2 | 8 | FB10 | MC10 | STD | 124 | I/O | (b) | RESET | |
edge_reg<0> | 2 | 8 | FB10 | MC11 | STD | 125 | I/O | (b) | RESET | |
epp_I/bytesel<1> | 5 | 11 | FB10 | MC12 | STD | 126 | I/O | I | RESET | |
epp_I/bytesel<0> | 5 | 10 | FB10 | MC13 | STD | (b) | (b) | RESET | ||
state_FFd2 | 12 | 16 | FB10 | MC14 | STD | 128 | I/O | I | RESET | |
edge_reg<9> | 2 | 8 | FB10 | MC15 | STD | (b) | (b) | RESET | ||
state_FFd3 | 13 | 14 | FB10 | MC18 | STD | (b) | (b) | RESET | ||
timebase_I/clk_cnt<14> | 8 | 25 | FB11 | MC1 | STD | (b) | (b) | RESET | ||
sram_adr<4> | 2 | 5 | FB11 | MC3 | STD | FAST | 60 | I/O | O | RESET |
trigcond_I/tlen_top_d | 9 | 9 | FB11 | MC4 | STD | (b) | (b) | RESET | ||
sram_adr<3> | 2 | 4 | FB11 | MC5 | STD | FAST | 61 | I/O | O | RESET |
timebase_I/clk_cnt<1> | 9 | 25 | FB11 | MC6 | STD | (b) | (b) | RESET | ||
timebase_I/clk_cnt<5> | 10 | 25 | FB11 | MC9 | STD | (b) | (b) | RESET | ||
sram_adr<2> | 2 | 3 | FB11 | MC10 | STD | FAST | 64 | I/O | O | RESET |
sram_adr<1> | 2 | 2 | FB11 | MC11 | STD | FAST | 66 | I/O | O | RESET |
sram_adr<0> | 1 | 1 | FB11 | MC12 | STD | FAST | 68 | I/O | O | RESET |
timebase_I/clk_cnt<13> | 10 | 25 | FB11 | MC13 | STD | (b) | (b) | RESET | ||
sram_adr<6> | 2 | 7 | FB11 | MC14 | STD | FAST | 69 | I/O | O | RESET |
timebase_I/clk_cnt<12> | 10 | 25 | FB11 | MC16 | STD | (b) | (b) | RESET | ||
sram_adr<7> | 2 | 8 | FB11 | MC17 | STD | FAST | 70 | I/O | O | RESET |
timebase_I/clk_cnt<11> | 10 | 25 | FB11 | MC18 | STD | (b) | (b) | RESET | ||
sample_cnt_wm | 16 | 21 | FB12 | MC1 | STD | (b) | (b) | RESET | ||
sram_I/sample_cnt_int<8> | 2 | 10 | FB12 | MC2 | STD | 110 | I/O | I | RESET | |
dd<0> | 6 | 14 | FB12 | MC3 | STD | FAST | 111 | I/O | I/O | |
sram_I/sample_cnt_int<7> | 2 | 9 | FB12 | MC4 | STD | (b) | (b) | RESET | ||
dd<1> | 6 | 14 | FB12 | MC5 | STD | FAST | 112 | I/O | I/O | |
sram_I/sample_cnt_int<16> | 2 | 18 | FB12 | MC6 | STD | (b) | (b) | RESET | ||
sram_I/sample_cnt_int<15> | 2 | 17 | FB12 | MC7 | STD | (b) | (b) | RESET | ||
dd<2> | 6 | 14 | FB12 | MC8 | STD | FAST | 113 | I/O | I/O | |
sram_I/sample_cnt_int<14> | 2 | 16 | FB12 | MC9 | STD | (b) | (b) | RESET | ||
sram_I/sample_cnt_int<13> | 2 | 15 | FB12 | MC10 | STD | 115 | I/O | I | RESET | |
sram_I/sample_cnt_int<12> | 2 | 14 | FB12 | MC11 | STD | (b) | (b) | RESET | ||
dd<3> | 12 | 31 | FB12 | MC12 | STD | FAST | 116 | I/O | I/O | |
sram_I/sample_cnt_int<11> | 2 | 13 | FB12 | MC13 | STD | (b) | (b) | RESET | ||
sram_I/sample_cnt_int<10> | 2 | 12 | FB12 | MC14 | STD | (b) | (b) | RESET | ||
sram_I/sample_cnt_int<0> | 3 | 19 | FB12 | MC15 | STD | (b) | (b) | RESET | ||
clk_rd | 5 | 12 | FB12 | MC16 | STD | (b) | (b) | RESET | ||
sram_I/sample_cnt_int<9> | 2 | 11 | FB12 | MC17 | STD | (b) | (b) | RESET | ||
timebase_I/clk_cnt<9> | 15 | 25 | FB13 | MC1 | STD | (b) | (b) | RESET | ||
sram_ce_l | 0 | 0 | FB13 | MC2 | STD | FAST | 71 | I/O | O | |
timebase_I/clk_cnt<8> | 14 | 25 | FB13 | MC3 | STD | (b) | (b) | RESET | ||
sram_clk | 24 | 16 | FB13 | MC8 | STD | FAST | 74 | I/O | O | |
sram_we_l | 3 | 4 | FB13 | MC11 | STD | FAST | 75 | I/O | O | SET |
sram_oe_l | 3 | 4 | FB13 | MC14 | STD | FAST | 76 | I/O | O | RESET |
sram_adsc_l | 0 | 0 | FB13 | MC15 | STD | FAST | 77 | I/O | O | |
timebase_I/clk_cnt<4> | 13 | 25 | FB13 | MC16 | STD | (b) | (b) | RESET | ||
sram_adr<8> | 2 | 9 | FB13 | MC17 | STD | FAST | 78 | I/O | O | RESET |
timebase_I/clk_cnt<15> | 8 | 25 | FB14 | MC1 | STD | (b) | (b) | RESET | ||
timebase_I/clk_cnt<2> | 8 | 25 | FB14 | MC2 | STD | (b) | (b) | RESET | ||
sram_d<6> | 2 | 2 | FB14 | MC3 | STD | FAST | 100 | I/O | I/O | RESET |
timebase_I/clk_cnt<16> | 6 | 25 | FB14 | MC4 | STD | (b) | (b) | RESET | ||
sram_d<5> | 2 | 2 | FB14 | MC5 | STD | FAST | 101 | I/O | I/O | RESET |
sram_d<4> | 2 | 2 | FB14 | MC6 | STD | FAST | 102 | I/O | I/O | RESET |
timebase_I/clk_cnt<17> | 5 | 25 | FB14 | MC7 | STD | (b) | (b) | RESET | ||
sram_d<3> | 2 | 2 | FB14 | MC8 | STD | FAST | 103 | I/O | I/O | RESET |
timebase_I/clk_cnt<18> | 3 | 25 | FB14 | MC9 | STD | (b) | (b) | RESET | ||
sram_d<2> | 2 | 2 | FB14 | MC10 | STD | FAST | 104 | I/O | I/O | RESET |
sram_d<1> | 2 | 2 | FB14 | MC11 | STD | FAST | 105 | I/O | I/O | RESET |
$OpTx$trigcond_I/int_vtrig_comp<2>/trigcond_I/int_vtrig_comp<2>_D2_INV$526 | 2 | 3 | FB14 | MC12 | STD | (b) | (b) | |||
$OpTx$trigcond_I/int_vtrig_comp<3>/trigcond_I/int_vtrig_comp<3>_D2_INV$527 | 2 | 3 | FB14 | MC13 | STD | (b) | (b) | |||
sram_d<0> | 2 | 2 | FB14 | MC14 | STD | FAST | 106 | I/O | I/O | RESET |
$OpTx$trigcond_I/int_vtrig_comp<4>/trigcond_I/int_vtrig_comp<4>_D2_INV$528 | 2 | 3 | FB14 | MC15 | STD | 107 | I/O | I | ||
$OpTx$trigcond_I/int_vtrig_comp<5>/trigcond_I/int_vtrig_comp<5>_D2_INV$529 | 2 | 3 | FB14 | MC16 | STD | (b) | (b) | |||
$OpTx$trigcond_I/int_vtrig_comp<6>/trigcond_I/int_vtrig_comp<6>_D2_INV$530 | 2 | 3 | FB14 | MC17 | STD | (b) | (b) | |||
timebase_I/clk_2 | 2 | 20 | FB14 | MC18 | STD | (b) | (b) | RESET | ||
sram_adr<9> | 2 | 10 | FB15 | MC2 | STD | FAST | 79 | I/O | O | RESET |
sram_adr<10> | 2 | 11 | FB15 | MC3 | STD | FAST | 80 | I/O | O | RESET |
trigcond_I/int_trig_hit_reg | 26 | 34 | FB15 | MC6 | STD | (b) | (b) | RESET | ||
sram_adr<11> | 2 | 12 | FB15 | MC8 | STD | FAST | 81 | I/O | O | RESET |
$OpTx$trigcond_I/int_vtrig_comp<14>/trigcond_I/int_vtrig_comp<14>_D2_INV$524 | 2 | 3 | FB15 | MC9 | STD | (b) | (b) | |||
sram_adr<12> | 2 | 13 | FB15 | MC10 | STD | FAST | 82 | I/O | O | RESET |
sram_adr<13> | 2 | 14 | FB15 | MC11 | STD | FAST | 83 | I/O | O | RESET |
sram_adr<14> | 2 | 15 | FB15 | MC12 | STD | FAST | 85 | I/O | O | RESET |
$OpTx$trigcond_I/int_vtrig_comp<12>/trigcond_I/int_vtrig_comp<12>_D2_INV$523 | 2 | 3 | FB15 | MC13 | STD | (b) | (b) | |||
sram_adr<15> | 2 | 16 | FB15 | MC14 | STD | FAST | 86 | I/O | O | RESET |
sram_adr<16> | 2 | 17 | FB15 | MC15 | STD | FAST | 87 | I/O | O | RESET |
$OpTx$trigcond_I/int_vtrig_comp<11>/trigcond_I/int_vtrig_comp<11>_D2_INV$522 | 2 | 3 | FB15 | MC16 | STD | (b) | (b) | |||
sram_d<15> | 2 | 2 | FB15 | MC17 | STD | FAST | 88 | I/O | I/O | RESET |
$OpTx$trigcond_I/int_vtrig_comp<10>/trigcond_I/int_vtrig_comp<10>_D2_INV$521 | 2 | 3 | FB15 | MC18 | STD | (b) | (b) | |||
sram_d<14> | 2 | 2 | FB16 | MC2 | STD | FAST | 91 | I/O | I/O | RESET |
sram_d<13> | 2 | 2 | FB16 | MC3 | STD | FAST | 92 | I/O | I/O | RESET |
sram_d<12> | 2 | 2 | FB16 | MC5 | STD | FAST | 93 | I/O | I/O | RESET |
sram_d<11> | 2 | 2 | FB16 | MC6 | STD | FAST | 94 | I/O | I/O | RESET |
sram_d<10> | 2 | 2 | FB16 | MC8 | STD | FAST | 95 | I/O | I/O | RESET |
sram_d<9> | 2 | 2 | FB16 | MC10 | STD | FAST | 96 | I/O | I/O | RESET |
sram_d<8> | 2 | 2 | FB16 | MC11 | STD | FAST | 97 | I/O | I/O | RESET |
sram_d<7> | 2 | 2 | FB16 | MC12 | STD | FAST | 98 | I/O | I/O | RESET |
trigcond_I/tlen_cnt<0> | 20 | 15 | FB16 | MC15 | STD | (b) | (b) | RESET | ||
trigcond_I/tlen_cnt<1> | 16 | 15 | FB16 | MC18 | STD | (b) | (b) | RESET | ||
value_reg<2> | 2 | 8 | FB2 | MC1 | STD | (b) | (b) | RESET | ||
value_reg<10> | 2 | 8 | FB2 | MC2 | STD | 9 | I/O | I | RESET | |
tsel_reg<2> | 2 | 8 | FB2 | MC3 | STD | 10 | I/O | I | RESET | |
tlen_reg<3> | 2 | 8 | FB2 | MC4 | STD | (b) | (b) | RESET | ||
tlen_reg<2> | 2 | 8 | FB2 | MC5 | STD | 11 | I/O | I | RESET | |
tcnt_reg<3> | 2 | 8 | FB2 | MC6 | STD | 12 | I/O | I | RESET | |
tcnt_reg<2> | 2 | 8 | FB2 | MC7 | STD | (b) | (b) | RESET | ||
stop | 2 | 8 | FB2 | MC8 | STD | 13 | I/O | I | RESET | |
psize_reg<3> | 2 | 8 | FB2 | MC9 | STD | (b) | (b) | RESET | ||
psize_reg<2> | 2 | 8 | FB2 | MC10 | STD | 14 | I/O | I | RESET | |
mask_reg<3> | 2 | 8 | FB2 | MC11 | STD | (b) | (b) | RESET | ||
mask_reg<2> | 2 | 8 | FB2 | MC12 | STD | 15 | I/O | I | RESET | |
mask_reg<11> | 2 | 8 | FB2 | MC13 | STD | (b) | (b) | RESET | ||
mask_reg<10> | 2 | 8 | FB2 | MC14 | STD | 16 | I/O | I | RESET | |
edge_reg<3> | 2 | 8 | FB2 | MC15 | STD | 17 | I/O | I | RESET | |
edge_reg<2> | 2 | 8 | FB2 | MC16 | STD | (b) | (b) | RESET | ||
edge_reg<11> | 2 | 8 | FB2 | MC17 | STD | 19 | I/O | I | RESET | |
edge_reg<10> | 2 | 8 | FB2 | MC18 | STD | (b) | (b) | RESET | ||
timebase_I/clk_cnt<10> | 12 | 25 | FB3 | MC5 | STD | (b) | (b) | RESET | ||
timebase_I/clk_cnt<7> | 13 | 25 | FB3 | MC6 | STD | (b) | (b) | RESET | ||
clk_ob | 24 | 16 | FB3 | MC10 | STD | FAST | 30 | I/O/GCK1 | GCK/O | |
clk_o | 11 | 13 | FB3 | MC14 | STD | FAST | 32 | I/O/GCK2 | GCK/O | |
st<1> | 3 | 4 | FB3 | MC15 | STD | FAST | 33 | I/O | O | RESET |
timebase_I/clk_cnt<3> | 12 | 25 | FB3 | MC17 | STD | (b) | (b) | RESET | ||
timebase_I/clk_cnt<6> | 11 | 25 | FB3 | MC18 | STD | (b) | (b) | RESET | ||
value_reg<7> | 2 | 8 | FB4 | MC1 | STD | (b) | (b) | RESET | ||
value_reg<4> | 2 | 8 | FB4 | MC2 | STD | 2 | I/O/GTS3 | I | RESET | |
value_reg<15> | 2 | 8 | FB4 | MC3 | STD | (b) | (b) | RESET | ||
value_reg<12> | 2 | 8 | FB4 | MC4 | STD | (b) | (b) | RESET | ||
tsel_reg<4> | 2 | 8 | FB4 | MC5 | STD | 3 | I/O/GTS4 | I | RESET | |
run | 2 | 8 | FB4 | MC6 | STD | 4 | I/O | I | RESET | |
pretrig_off | 2 | 8 | FB4 | MC7 | STD | (b) | (b) | RESET | ||
mask_reg<7> | 2 | 8 | FB4 | MC8 | STD | 5 | I/O/GTS1 | I | RESET | |
mask_reg<4> | 2 | 8 | FB4 | MC9 | STD | (b) | (b) | RESET | ||
mask_reg<1> | 2 | 8 | FB4 | MC10 | STD | (b) | (b) | RESET | ||
mask_reg<15> | 2 | 8 | FB4 | MC11 | STD | (b) | (b) | RESET | ||
mask_reg<12> | 2 | 8 | FB4 | MC12 | STD | 6 | I/O/GTS2 | I | RESET | |
inv_trig | 2 | 8 | FB4 | MC13 | STD | (b) | (b) | RESET | ||
epp_I/auto_inc | 2 | 8 | FB4 | MC14 | STD | 7 | I/O | I | RESET | |
edge_reg<7> | 2 | 8 | FB4 | MC15 | STD | (b) | (b) | RESET | ||
edge_reg<4> | 2 | 8 | FB4 | MC16 | STD | (b) | (b) | RESET | ||
edge_reg<15> | 2 | 8 | FB4 | MC17 | STD | (b) | (b) | RESET | ||
edge_reg<12> | 2 | 8 | FB4 | MC18 | STD | (b) | (b) | RESET | ||
st<2> | 3 | 4 | FB5 | MC2 | STD | FAST | 34 | I/O | O | RESET |
st<3> | 3 | 4 | FB5 | MC5 | STD | FAST | 35 | I/O | O | RESET |
trigcond_I/int_etrig_hit_reg | 25 | 41 | FB5 | MC8 | STD | 38 | I/O/GCK3 | GCK/I | RESET | |
trigcond_I/extrig_int | 1 | 1 | FB5 | MC10 | STD | 39 | I/O | (b) | RESET | |
trigcond_I/trig_on_d | 2 | 2 | FB5 | MC11 | STD | (b) | (b) | RESET | ||
sram_d<31> | 2 | 2 | FB5 | MC12 | STD | FAST | 40 | I/O | I/O | RESET |
trig_on | 2 | 3 | FB5 | MC13 | STD | (b) | (b) | RESET | ||
sram_d<30> | 2 | 2 | FB5 | MC14 | STD | FAST | 41 | I/O | I/O | RESET |
sram_d<29> | 2 | 2 | FB5 | MC15 | STD | FAST | 43 | I/O | I/O | RESET |
sram_I/sample_cnt_int<1> | 2 | 3 | FB5 | MC16 | STD | (b) | (b) | RESET | ||
sram_d<28> | 2 | 2 | FB5 | MC17 | STD | FAST | 44 | I/O | I/O | RESET |
sample_cnt_en | 2 | 2 | FB5 | MC18 | STD | (b) | (b) | RESET | ||
value_reg<9> | 2 | 8 | FB6 | MC1 | STD | (b) | (b) | RESET | ||
value_reg<8> | 2 | 8 | FB6 | MC2 | STD | 135 | I/O | I | RESET | |
value_reg<3> | 2 | 8 | FB6 | MC3 | STD | 136 | I/O | I | RESET | |
value_reg<1> | 2 | 8 | FB6 | MC4 | STD | (b) | (b) | RESET | ||
value_reg<11> | 2 | 8 | FB6 | MC5 | STD | 137 | I/O | I | RESET | |
value_reg<0> | 2 | 8 | FB6 | MC6 | STD | 138 | I/O | I | RESET | |
tsel_reg<3> | 2 | 8 | FB6 | MC7 | STD | (b) | (b) | RESET | ||
tsel_reg<1> | 2 | 8 | FB6 | MC8 | STD | 139 | I/O | I | RESET | |
tsel_reg<0> | 2 | 8 | FB6 | MC9 | STD | (b) | (b) | RESET | ||
tlen_reg<1> | 2 | 8 | FB6 | MC10 | STD | 140 | I/O | I | RESET | |
tlen_reg<0> | 2 | 8 | FB6 | MC11 | STD | (b) | (b) | RESET | ||
tcnt_reg<1> | 2 | 8 | FB6 | MC12 | STD | (b) | (b) | RESET | ||
tcnt_reg<0> | 2 | 8 | FB6 | MC13 | STD | (b) | (b) | RESET | ||
psize_reg<1> | 2 | 8 | FB6 | MC14 | STD | 142 | I/O | I | RESET | |
psize_reg<0> | 2 | 8 | FB6 | MC15 | STD | 143 | I/O/GSR | I | RESET | |
mask_reg<9> | 2 | 8 | FB6 | MC16 | STD | (b) | (b) | RESET | ||
mask_reg<8> | 2 | 8 | FB6 | MC17 | STD | (b) | (b) | RESET | ||
epp_I/adr<0> | 2 | 4 | FB6 | MC18 | STD | (b) | (b) | RESET | ||
value_reg<6> | 2 | 8 | FB7 | MC1 | STD | (b) | (b) | RESET | ||
value_reg<5> | 2 | 8 | FB7 | MC2 | STD | (b) | (b) | RESET | ||
sram_d<27> | 2 | 2 | FB7 | MC3 | STD | FAST | 45 | I/O | I/O | RESET |
value_reg<14> | 2 | 8 | FB7 | MC4 | STD | (b) | (b) | RESET | ||
sram_d<26> | 2 | 2 | FB7 | MC5 | STD | FAST | 46 | I/O | I/O | RESET |
value_reg<13> | 2 | 8 | FB7 | MC6 | STD | (b) | (b) | RESET | ||
mask_reg<6> | 2 | 8 | FB7 | MC7 | STD | (b) | (b) | RESET | ||
mask_reg<5> | 2 | 8 | FB7 | MC8 | STD | (b) | (b) | RESET | ||
mask_reg<14> | 2 | 8 | FB7 | MC9 | STD | (b) | (b) | RESET | ||
mask_reg<13> | 2 | 8 | FB7 | MC10 | STD | (b) | (b) | RESET | ||
edge_reg<6> | 2 | 8 | FB7 | MC11 | STD | (b) | (b) | RESET | ||
sram_d<25> | 2 | 2 | FB7 | MC12 | STD | FAST | 48 | I/O | I/O | RESET |
edge_reg<5> | 2 | 8 | FB7 | MC13 | STD | (b) | (b) | RESET | ||
edge_reg<14> | 2 | 8 | FB7 | MC14 | STD | (b) | (b) | RESET | ||
sram_d<24> | 2 | 2 | FB7 | MC15 | STD | FAST | 49 | I/O | I/O | RESET |
edge_reg<13> | 2 | 8 | FB7 | MC16 | STD | (b) | (b) | RESET | ||
clr | 2 | 8 | FB7 | MC17 | STD | (b) | (b) | RESET | ||
clk_falling_edge | 2 | 8 | FB7 | MC18 | STD | (b) | (b) | RESET | ||
epp_I/d_rd_i_d | 1 | 3 | FB8 | MC3 | STD | 131 | I/O | I | RESET | |
epp_I/WR_l_i | 1 | 1 | FB8 | MC4 | STD | (b) | (b) | RESET | ||
epp_I/RD_l_i | 1 | 1 | FB8 | MC5 | STD | 132 | I/O | I | RESET | |
epp_I/ALE_l_i | 1 | 1 | FB8 | MC6 | STD | (b) | (b) | RESET | ||
$OpTx$$OpTx$FX_DC$187_INV$520 | 1 | 2 | FB8 | MC7 | STD | (b) | (b) | |||
timebase_I/sw_read_clk_r | 2 | 2 | FB8 | MC8 | STD | 133 | I/O | I | RESET | |
timebase_I/sw_read_clk_f | 2 | 2 | FB8 | MC9 | STD | (b) | (b) | RESET | ||
timebase_I/clk_5f<2> | 2 | 3 | FB8 | MC10 | STD | 134 | I/O | I | RESET | |
timebase_I/clk_5f<0> | 2 | 4 | FB8 | MC11 | STD | (b) | (b) | RESET | ||
epp_I/adr<3> | 2 | 4 | FB8 | MC12 | STD | (b) | (b) | RESET | ||
epp_I/adr<2> | 2 | 4 | FB8 | MC13 | STD | (b) | (b) | RESET | ||
epp_I/adr<1> | 2 | 4 | FB8 | MC14 | STD | (b) | (b) | RESET | ||
$OpTx$trigcond_I/int_vtrig_comp<9>/trigcond_I/int_vtrig_comp<9>_D2_INV$532 | 2 | 3 | FB8 | MC15 | STD | (b) | (b) | |||
$OpTx$trigcond_I/int_vtrig_comp<8>/trigcond_I/int_vtrig_comp<8>_D2_INV$531 | 2 | 3 | FB8 | MC16 | STD | (b) | (b) | |||
$OpTx$trigcond_I/int_vtrig_comp<15>/trigcond_I/int_vtrig_comp<15>_D2_INV$525 | 2 | 3 | FB8 | MC17 | STD | (b) | (b) | |||
timebase_I/clk_5f<1> | 3 | 4 | FB8 | MC18 | STD | (b) | (b) | RESET | ||
sram_d<23> | 2 | 2 | FB9 | MC2 | STD | FAST | 50 | I/O | I/O | RESET |
sram_d<22> | 2 | 2 | FB9 | MC3 | STD | FAST | 51 | I/O | I/O | RESET |
sram_I/sample_cnt_int<6> | 2 | 8 | FB9 | MC4 | STD | (b) | (b) | RESET | ||
sram_d<21> | 2 | 2 | FB9 | MC5 | STD | FAST | 52 | I/O | I/O | RESET |
sram_d<20> | 2 | 2 | FB9 | MC6 | STD | FAST | 53 | I/O | I/O | RESET |
sram_I/sample_cnt_int<5> | 2 | 7 | FB9 | MC7 | STD | (b) | (b) | RESET | ||
sram_d<19> | 2 | 2 | FB9 | MC8 | STD | FAST | 54 | I/O | I/O | RESET |
sram_I/sample_cnt_int<4> | 2 | 6 | FB9 | MC9 | STD | (b) | (b) | RESET | ||
sram_I/sample_cnt_int<3> | 2 | 5 | FB9 | MC10 | STD | (b) | (b) | RESET | ||
sram_d<18> | 2 | 2 | FB9 | MC11 | STD | FAST | 56 | I/O | I/O | RESET |
sram_d<17> | 2 | 2 | FB9 | MC12 | STD | FAST | 57 | I/O | I/O | RESET |
sram_I/sample_cnt_int<2> | 2 | 4 | FB9 | MC13 | STD | (b) | (b) | RESET | ||
sram_d<16> | 2 | 2 | FB9 | MC14 | STD | FAST | 58 | I/O | I/O | RESET |
done | 2 | 3 | FB9 | MC15 | STD | (b) | (b) | RESET | ||
adr_cnt_en | 2 | 4 | FB9 | MC16 | STD | (b) | (b) | RESET | ||
sram_adr<5> | 2 | 6 | FB9 | MC17 | STD | FAST | 59 | I/O | O | RESET |
state_FFd1 | 15 | 32 | FB9 | MC18 | STD | (b) | (b) | RESET |