;Register #define var00 r22 #define var01 r23 #define var02 r24 #define var03 r25 #define var04 r18 #define var05 r19 #define var06 r20 #define var07 r21 #define var08 r26 #define var09 r27 #define var10 r28 #define var11 r30 #define var12 r31 ;-----------------------------------------------------------------------------: ; 32bit squareroot ; ; Register Variables ; Call: var[03:00] = Source (32bit) ; var[12:04] = *var08 and var12 must be high-regs. ; ; Result:var[01:00] = Result (16bit) ; var[12:02] = ; ; Size = 55 words ; Clock = 536..552 cycles (+ret = 541..559) ; Stack = 0 byte .global sqrt32 sqrt32: push r28 clr var04 clr var05 clr var06 clr var07 ldi var08,1 clr var09 clr var10 clr var11 ldi var12,16 sqrt32l: lsl var00 rol var01 rol var02 rol var03 rol var04 rol var05 rol var06 rol var07 lsl var00 rol var01 rol var02 rol var03 rol var04 rol var05 rol var06 rol var07 brpl hier1 add var04,var08 adc var05,var09 adc var06,var10 adc var07,var11 rjmp hier2 hier1: sub var04,var08 sbc var05,var09 sbc var06,var10 sbc var07,var11 hier2: lsl var08 rol var09 rol var10 andi var08,0b11111000 ori var08,0b00000101 sbrc var07,7 subi var08,2 dec var12 brne sqrt32l lsr var10 ror var09 ror var08 lsr var10 ror var09 ror var08 mov r25, var09 mov r24, var08 pop r28 ret