;Register
#define var00		r22
#define var01		r23
#define var02		r24
#define var03		r25
#define var04		r18
#define var05		r19
#define var06		r20
#define var07		r21
#define var08		r26
#define var09		r27
#define var10		r28
#define var11		r30
#define var12		r31

;-----------------------------------------------------------------------------:
; 16bit squareroot
;
; Register Variables
;  Call:  var[1:0] = Source (16bit)
;         var[6:2] = <work area>       * var4 and var6 must be high-regs.
;
;  Result:var[0]   = Result (8bit)
;         var[6:1] = <broken>
;
; Size  = 33 words
; Clock = 177..185 cycles (+ret = 184...192)
; Stack = 0 byte

.global sqrt16
sqrt16:		clr	var00
		clr	var01
		ldi	var04,1
		clr	var05
		ldi	var06,8
sqrt16l:	lsl	var02
		rol	var03
		rol	var00
		rol	var01
		lsl	var02
		rol	var03
		rol	var00
		rol	var01
		brpl	hier3
		add	var00,var04
		adc	var01,var05
		rjmp	hier4
hier3:
		sub	var00,var04
		sbc	var01,var05
hier4:
		lsl	var04
		rol	var05
		andi	var04,0b11111000
		ori	var04,0b00000101
		sbrc	var01,7
		subi	var04,2
		dec	var06
		brne	sqrt16l
		lsr	var05
		ror	var04
		lsr	var05
		ror	var04
		mov	var02, var04
		ret