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-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:37:17 05/30/2008 
-- Design Name: 
-- Module Name:    lcdcon - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity lcdcon is
    Port ( BUS_ADR : in  STD_LOGIC_VECTOR (15 downto 0);
           BUS_DAT : in  STD_LOGIC_VECTOR (7 downto 0);
			  BUS_WR : in  STD_LOGIC;
			  SRAM_ADR : out  STD_LOGIC_VECTOR (15 downto 0);
			  SRAM_WE : out  STD_LOGIC;
			  SRAM_OE : out  STD_LOGIC;
			  SRAM_DAT : inout  STD_LOGIC_VECTOR (7 downto 0);
           LCD_DAT : out  STD_LOGIC_VECTOR (3 downto 0);
           LCD_FLM : out  STD_LOGIC;
           LCD_LP : out  STD_LOGIC;
           LCD_CLK1 : out  STD_LOGIC;
           LCD_CLK2 : out  STD_LOGIC;
           CLK : in  STD_LOGIC);
end lcdcon;

architecture Behavioral of lcdcon is

	signal states: STD_LOGIC_VECTOR(1 downto 0):=(others=>'0');		-- Statmachine SRAM Timing
	signal radressL: STD_LOGIC_VECTOR(7 downto 0):=(others=>'0');	-- SRAM Adresse für LCD Ausgabe
	signal radressH: STD_LOGIC_VECTOR(7 downto 0):=(others=>'0');	-- SRAM Adresse für LCD Ausgabe
	signal sramdaten: STD_LOGIC_VECTOR(7 downto 0):=(others=>'0');	-- Lesedatenpuffer
	signal busdaten: STD_LOGIC_VECTOR(7 downto 0):=(others=>'0');	-- Schreibdatenpuffer
	signal busadr: STD_LOGIC_VECTOR(15 downto 0):=(others=>'0');	-- Schreibadresspuffer
	signal lcddat: STD_LOGIC_VECTOR(3 downto 0):=(others=>'0');		-- Ausgangsdatenpuffer

begin
	process (clk, states) begin							-- State Machine
		if rising_edge(clk) then
			states <= states+1;
		end if;	
	end process;	
	
	process (radressL, radressH, states, clk) begin	-- Timing Signale für LCD
		if rising_edge(clk) then
			if(radressL<90) then							-- Shiftclock: 1/2 CLK
				if (states=0) or (states=2) then
					LCD_CLK1<='1';
				else
					LCD_CLK1<='0';
				end if;
				LCD_CLK2<='0';
			else
				if (states=0) or (states=2) then
					LCD_CLK2<='1';
				else
					LCD_CLK2<='0';
				end if;
				LCD_CLK1<='0';
			end if;
			
			if (states=0) then							-- LCD Daten
				LCD_DAT<=SRAM_DAT(7 downto 4);
			elsif (states=2) then
				LCD_DAT<=SRAM_DAT(3 downto 0);
			end if;

			if (states=3) then
				if (radressL=179) then					-- X Counter
					radressL<=(others=>'0');
				else
					radressL<=radressL+1;
				end if;
				if (radressL=179) then					-- Y Counter
					if (radressH=199) then
						radressH<=(others=>'0');
					else
						radressH<=radressH+1;
					end if;
				end if;
			end if;
				
			if (radressL=179) and (states(1)='1') then	-- LP
				LCD_LP<='1';
			else
				LCD_LP<='0';
			end if;
			
			if (radressH=0) then							-- FLM
				LCD_FLM<='1';
			elsif (radressL=2) then
				LCD_FLM<='0';
			end if;
		end if;
	end process;
	
	process (BUS_WR, BUS_DAT, BUS_ADR) begin			-- Timing Signale für Businterface
		if rising_edge(BUS_WR) then
			busdaten<=BUS_DAT;
			busadr<=BUS_ADR;
		end if;
	end process;
		
	process (busadr, radressL, radressH, busdaten, states) begin		-- SRAM Timing
		if (states(1)='1') then
			SRAM_ADR<=busadr;
			SRAM_WE<='0';
			SRAM_OE<='1';
			SRAM_DAT<=busdaten;
		else
			SRAM_ADR(7 downto 0)<=radressL;
			SRAM_ADR(15 downto 8)<=radressH;
			SRAM_WE<='1';
			SRAM_OE<='0';
			SRAM_DAT<="ZZZZZZZZ";
			sramdaten <= SRAM_DAT;
		end if;
	end process;	
end Behavioral;